The 58 registers of TC2 (Timer Counter), from 0x40040000, with their reset value and every field. The PIC32CX1025MTSH128 has 2920 registers in 63 peripherals, one page each.
TC2 Timer Counter
TC_CHANNEL0.TC_CCRChannel Control Register
Address
0x40040000
Reset
0x00000000
Access
write only
Size
32-bit
3 fields
Field
Bits
What it does
SWTRG
2
Software Trigger Command
CLKDIS
1
Counter Clock Disable Command
CLKEN
0
Counter Clock Enable Command
TC_CHANNEL0.TC_CMRChannel Mode Register
Address
0x40040004
Reset
0x00000000
Access
read/write
Size
32-bit
26 fields
Field
Bits
What it does
BEEVT
29:28
External Event Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
BCPC
27:26
RC Compare Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
BCPB
25:24
RB Compare Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
ASWTRG
23:22
Software Trigger Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
SBSMPLR
22:20
Loading Edge Subsampling Ratio
0 Load a Capture register each selected edge
1 Load a Capture register every 2 selected edges
2 Load a Capture register every 4 selected edges
3 Load a Capture register every 8 selected edges
4 Load a Capture register every 16 selected edges
AEEVT
21:20
External Event Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
ACPC
19:18
RC Compare Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
LDRB
19:18
RB Loading Edge Selection
0 None
1 Rising edge of TIOAx
2 Falling edge of TIOAx
3 Each edge of TIOAx
ACPA
17:16
RA Compare Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
LDRA
17:16
RA Loading Edge Selection
0 None
1 Rising edge of TIOAx
2 Falling edge of TIOAx
3 Each edge of TIOAx
WAVE
15
Waveform Mode
WAVSEL
14:13
Waveform Selection
0 UP mode without automatic trigger on RC Compare
1 UPDOWN mode without automatic trigger on RC Compare
2 UP mode with automatic trigger on RC Compare
3 UPDOWN mode with automatic trigger on RC Compare
CPCTRG
14
RC Compare Trigger Enable
ENETRG
12
External Event Trigger Enable
EEVT
11:10
External Event Selection
0 TIOB
1 XC0
2 XC1
3 XC2
ABETRG
10
TIOAx or TIOBx External Trigger Selection
EEVTEDG
9:8
External Event Edge Selection
0 None
1 Rising edge
2 Falling edge
3 Each edge
ETRGEDG
9:8
External Trigger Edge Selection
0 The clock is not gated by an external signal.
1 Rising edge
2 Falling edge
3 Each edge
CPCDIS
7
Counter Clock Disable with RC Compare
LDBDIS
7
Counter Clock Disable with RB Loading
CPCSTOP
6
Counter Clock Stopped with RC Compare
LDBSTOP
6
Counter Clock Stopped with RB Loading
BURST
5:4
Burst Signal Selection
0 The clock is not gated by an external signal.
1 XC0 is ANDed with the selected clock.
2 XC1 is ANDed with the selected clock.
3 XC2 is ANDed with the selected clock.
CLKI
3
Clock Invert
TCCLKS
2:0
Clock Selection
0 Clock selected: internal GCLK [TC_ID] clock signal (from PMC)
1 Clock selected: internal MCK/8 clock signal (from PMC)
2 Clock selected: internal MCK/32 clock signal (from PMC)
3 Clock selected: internal MCK/128 clock signal (from PMC)
4 Clock selected: internal MD_SLCK clock signal (from PMC)
5 Clock selected: XC0
6 Clock selected: XC1
7 Clock selected: XC2
BSWTRG
31:30
Software Trigger Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
TC_CHANNEL0.TC_SMMRStepper Motor Mode Register
Address
0x40040008
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DOWN
1
Down Count
GCEN
0
Gray Count Enable
TC_CHANNEL0.TC_CVCounter Value
Address
0x40040010
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CV
31:0
Counter Value
TC_CHANNEL0.TC_RARegister A
Address
0x40040014
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RA
31:0
Register A
TC_CHANNEL0.TC_RBRegister B
Address
0x40040018
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RB
31:0
Register B
TC_CHANNEL0.TC_RCRegister C
Address
0x4004001C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RC
31:0
Register C
TC_CHANNEL0.TC_SRInterrupt Status Register
Address
0x40040020
Reset
0x00000000
Access
read only
Size
32-bit
14 fields
Field
Bits
What it does
MTIOB
18
TIOBx Mirror
MTIOA
17
TIOAx Mirror
CLKSTA
16
Clock Enabling Status
SECE
10
Security and/or Safety Event (cleared on read)
RXBUFF
9
Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR)
ENDRX
8
End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR)
ETRGS
7
External Trigger Status (cleared on read)
LDRBS
6
RB Loading Status (cleared on read)
LDRAS
5
RA Loading Status (cleared on read)
CPCS
4
RC Compare Status (cleared on read)
CPBS
3
RB Compare Status (cleared on read)
CPAS
2
RA Compare Status (cleared on read)
LOVRS
1
Load Overrun Status (cleared on read)
COVFS
0
Counter Overflow Status (cleared on read)
TC_CHANNEL0.TC_IERInterrupt Enable Register
Address
0x40040024
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Enable
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL0.TC_IDRInterrupt Disable Register
Address
0x40040028
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Disable
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL0.TC_IMRInterrupt Mask Register
Address
0x4004002C
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Mask
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL0.TC_EMRExtended Mode Register
Address
0x40040030
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
NODIVCLK
8
No Divided Clock
TRIGSRCB
5:4
Trigger Source for Input B
0 The trigger/capture input B is driven by external pin TIOBx
1 The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.
TRIGSRCA
1:0
Trigger Source for Input A
0 The trigger/capture input A is driven by external pin TIOAx
1 The trigger/capture input A is driven internally by PWMx
TC_CHANNEL0.TC_CSRChannel Status Register
Address
0x40040034
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
MTIOB
18
TIOBx Mirror
MTIOA
17
TIOAx Mirror
CLKSTA
16
Clock Enabling Status
TC_CHANNEL0.TC_SSRSafety Status Register
Address
0x40040038
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
Field
Bits
What it does
SWETYP
27:24
Software Error Type (cleared on read)
0 TC Channel x is enabled and a write-only register has been read (Warning).
1 TC Channel x is enabled and a write access has been performed on a read-only register (Warning).
2 Access to an undefined address of the TC (Warning).
3 TC_RAx or TC_RBx are written while channel is enabled and configured in capture mode (Error).
WPVSRC
23:8
Write Protection Violation Source (cleared on read)
SWE
3
Software Control Error (cleared on read)
SEQE
2
Internal Sequencer Error (cleared on read)
CGD
1
Clock Glitch Detected (cleared on read)
WPVS
0
Write Protection Violation Status (cleared on read)
ECLASS
31
Software Error Class
0 An abnormal access that does not have any impact.
1 An abnormal access that may have an impact.
TC_CHANNEL1.TC_CCRChannel Control Register
Address
0x40040040
Reset
0x00000000
Access
write only
Size
32-bit
3 fields
Field
Bits
What it does
SWTRG
2
Software Trigger Command
CLKDIS
1
Counter Clock Disable Command
CLKEN
0
Counter Clock Enable Command
TC_CHANNEL1.TC_CMRChannel Mode Register
Address
0x40040044
Reset
0x00000000
Access
read/write
Size
32-bit
26 fields
Field
Bits
What it does
BEEVT
29:28
External Event Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
BCPC
27:26
RC Compare Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
BCPB
25:24
RB Compare Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
ASWTRG
23:22
Software Trigger Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
SBSMPLR
22:20
Loading Edge Subsampling Ratio
0 Load a Capture register each selected edge
1 Load a Capture register every 2 selected edges
2 Load a Capture register every 4 selected edges
3 Load a Capture register every 8 selected edges
4 Load a Capture register every 16 selected edges
AEEVT
21:20
External Event Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
ACPC
19:18
RC Compare Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
LDRB
19:18
RB Loading Edge Selection
0 None
1 Rising edge of TIOAx
2 Falling edge of TIOAx
3 Each edge of TIOAx
ACPA
17:16
RA Compare Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
LDRA
17:16
RA Loading Edge Selection
0 None
1 Rising edge of TIOAx
2 Falling edge of TIOAx
3 Each edge of TIOAx
WAVE
15
Waveform Mode
WAVSEL
14:13
Waveform Selection
0 UP mode without automatic trigger on RC Compare
1 UPDOWN mode without automatic trigger on RC Compare
2 UP mode with automatic trigger on RC Compare
3 UPDOWN mode with automatic trigger on RC Compare
CPCTRG
14
RC Compare Trigger Enable
ENETRG
12
External Event Trigger Enable
EEVT
11:10
External Event Selection
0 TIOB
1 XC0
2 XC1
3 XC2
ABETRG
10
TIOAx or TIOBx External Trigger Selection
EEVTEDG
9:8
External Event Edge Selection
0 None
1 Rising edge
2 Falling edge
3 Each edge
ETRGEDG
9:8
External Trigger Edge Selection
0 The clock is not gated by an external signal.
1 Rising edge
2 Falling edge
3 Each edge
CPCDIS
7
Counter Clock Disable with RC Compare
LDBDIS
7
Counter Clock Disable with RB Loading
CPCSTOP
6
Counter Clock Stopped with RC Compare
LDBSTOP
6
Counter Clock Stopped with RB Loading
BURST
5:4
Burst Signal Selection
0 The clock is not gated by an external signal.
1 XC0 is ANDed with the selected clock.
2 XC1 is ANDed with the selected clock.
3 XC2 is ANDed with the selected clock.
CLKI
3
Clock Invert
TCCLKS
2:0
Clock Selection
0 Clock selected: internal GCLK [TC_ID] clock signal (from PMC)
1 Clock selected: internal MCK/8 clock signal (from PMC)
2 Clock selected: internal MCK/32 clock signal (from PMC)
3 Clock selected: internal MCK/128 clock signal (from PMC)
4 Clock selected: internal MD_SLCK clock signal (from PMC)
5 Clock selected: XC0
6 Clock selected: XC1
7 Clock selected: XC2
BSWTRG
31:30
Software Trigger Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
TC_CHANNEL1.TC_SMMRStepper Motor Mode Register
Address
0x40040048
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DOWN
1
Down Count
GCEN
0
Gray Count Enable
TC_CHANNEL1.TC_CVCounter Value
Address
0x40040050
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CV
31:0
Counter Value
TC_CHANNEL1.TC_RARegister A
Address
0x40040054
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RA
31:0
Register A
TC_CHANNEL1.TC_RBRegister B
Address
0x40040058
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RB
31:0
Register B
TC_CHANNEL1.TC_RCRegister C
Address
0x4004005C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RC
31:0
Register C
TC_CHANNEL1.TC_SRInterrupt Status Register
Address
0x40040060
Reset
0x00000000
Access
read only
Size
32-bit
14 fields
Field
Bits
What it does
MTIOB
18
TIOBx Mirror
MTIOA
17
TIOAx Mirror
CLKSTA
16
Clock Enabling Status
SECE
10
Security and/or Safety Event (cleared on read)
RXBUFF
9
Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR)
ENDRX
8
End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR)
ETRGS
7
External Trigger Status (cleared on read)
LDRBS
6
RB Loading Status (cleared on read)
LDRAS
5
RA Loading Status (cleared on read)
CPCS
4
RC Compare Status (cleared on read)
CPBS
3
RB Compare Status (cleared on read)
CPAS
2
RA Compare Status (cleared on read)
LOVRS
1
Load Overrun Status (cleared on read)
COVFS
0
Counter Overflow Status (cleared on read)
TC_CHANNEL1.TC_IERInterrupt Enable Register
Address
0x40040064
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Enable
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL1.TC_IDRInterrupt Disable Register
Address
0x40040068
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Disable
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL1.TC_IMRInterrupt Mask Register
Address
0x4004006C
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Mask
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL1.TC_EMRExtended Mode Register
Address
0x40040070
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
NODIVCLK
8
No Divided Clock
TRIGSRCB
5:4
Trigger Source for Input B
0 The trigger/capture input B is driven by external pin TIOBx
1 The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.
TRIGSRCA
1:0
Trigger Source for Input A
0 The trigger/capture input A is driven by external pin TIOAx
1 The trigger/capture input A is driven internally by PWMx
TC_CHANNEL1.TC_CSRChannel Status Register
Address
0x40040074
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
MTIOB
18
TIOBx Mirror
MTIOA
17
TIOAx Mirror
CLKSTA
16
Clock Enabling Status
TC_CHANNEL1.TC_SSRSafety Status Register
Address
0x40040078
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
Field
Bits
What it does
SWETYP
27:24
Software Error Type (cleared on read)
0 TC Channel x is enabled and a write-only register has been read (Warning).
1 TC Channel x is enabled and a write access has been performed on a read-only register (Warning).
2 Access to an undefined address of the TC (Warning).
3 TC_RAx or TC_RBx are written while channel is enabled and configured in capture mode (Error).
WPVSRC
23:8
Write Protection Violation Source (cleared on read)
SWE
3
Software Control Error (cleared on read)
SEQE
2
Internal Sequencer Error (cleared on read)
CGD
1
Clock Glitch Detected (cleared on read)
WPVS
0
Write Protection Violation Status (cleared on read)
ECLASS
31
Software Error Class
0 An abnormal access that does not have any impact.
1 An abnormal access that may have an impact.
TC_CHANNEL2.TC_CCRChannel Control Register
Address
0x40040080
Reset
0x00000000
Access
write only
Size
32-bit
3 fields
Field
Bits
What it does
SWTRG
2
Software Trigger Command
CLKDIS
1
Counter Clock Disable Command
CLKEN
0
Counter Clock Enable Command
TC_CHANNEL2.TC_CMRChannel Mode Register
Address
0x40040084
Reset
0x00000000
Access
read/write
Size
32-bit
26 fields
Field
Bits
What it does
BEEVT
29:28
External Event Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
BCPC
27:26
RC Compare Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
BCPB
25:24
RB Compare Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
ASWTRG
23:22
Software Trigger Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
SBSMPLR
22:20
Loading Edge Subsampling Ratio
0 Load a Capture register each selected edge
1 Load a Capture register every 2 selected edges
2 Load a Capture register every 4 selected edges
3 Load a Capture register every 8 selected edges
4 Load a Capture register every 16 selected edges
AEEVT
21:20
External Event Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
ACPC
19:18
RC Compare Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
LDRB
19:18
RB Loading Edge Selection
0 None
1 Rising edge of TIOAx
2 Falling edge of TIOAx
3 Each edge of TIOAx
ACPA
17:16
RA Compare Effect on TIOAx
0 None
1 Set
2 Clear
3 Toggle
LDRA
17:16
RA Loading Edge Selection
0 None
1 Rising edge of TIOAx
2 Falling edge of TIOAx
3 Each edge of TIOAx
WAVE
15
Waveform Mode
WAVSEL
14:13
Waveform Selection
0 UP mode without automatic trigger on RC Compare
1 UPDOWN mode without automatic trigger on RC Compare
2 UP mode with automatic trigger on RC Compare
3 UPDOWN mode with automatic trigger on RC Compare
CPCTRG
14
RC Compare Trigger Enable
ENETRG
12
External Event Trigger Enable
EEVT
11:10
External Event Selection
0 TIOB
1 XC0
2 XC1
3 XC2
ABETRG
10
TIOAx or TIOBx External Trigger Selection
EEVTEDG
9:8
External Event Edge Selection
0 None
1 Rising edge
2 Falling edge
3 Each edge
ETRGEDG
9:8
External Trigger Edge Selection
0 The clock is not gated by an external signal.
1 Rising edge
2 Falling edge
3 Each edge
CPCDIS
7
Counter Clock Disable with RC Compare
LDBDIS
7
Counter Clock Disable with RB Loading
CPCSTOP
6
Counter Clock Stopped with RC Compare
LDBSTOP
6
Counter Clock Stopped with RB Loading
BURST
5:4
Burst Signal Selection
0 The clock is not gated by an external signal.
1 XC0 is ANDed with the selected clock.
2 XC1 is ANDed with the selected clock.
3 XC2 is ANDed with the selected clock.
CLKI
3
Clock Invert
TCCLKS
2:0
Clock Selection
0 Clock selected: internal GCLK [TC_ID] clock signal (from PMC)
1 Clock selected: internal MCK/8 clock signal (from PMC)
2 Clock selected: internal MCK/32 clock signal (from PMC)
3 Clock selected: internal MCK/128 clock signal (from PMC)
4 Clock selected: internal MD_SLCK clock signal (from PMC)
5 Clock selected: XC0
6 Clock selected: XC1
7 Clock selected: XC2
BSWTRG
31:30
Software Trigger Effect on TIOBx
0 None
1 Set
2 Clear
3 Toggle
TC_CHANNEL2.TC_SMMRStepper Motor Mode Register
Address
0x40040088
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DOWN
1
Down Count
GCEN
0
Gray Count Enable
TC_CHANNEL2.TC_CVCounter Value
Address
0x40040090
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CV
31:0
Counter Value
TC_CHANNEL2.TC_RARegister A
Address
0x40040094
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RA
31:0
Register A
TC_CHANNEL2.TC_RBRegister B
Address
0x40040098
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RB
31:0
Register B
TC_CHANNEL2.TC_RCRegister C
Address
0x4004009C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RC
31:0
Register C
TC_CHANNEL2.TC_SRInterrupt Status Register
Address
0x400400A0
Reset
0x00000000
Access
read only
Size
32-bit
14 fields
Field
Bits
What it does
MTIOB
18
TIOBx Mirror
MTIOA
17
TIOAx Mirror
CLKSTA
16
Clock Enabling Status
SECE
10
Security and/or Safety Event (cleared on read)
RXBUFF
9
Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR)
ENDRX
8
End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR)
ETRGS
7
External Trigger Status (cleared on read)
LDRBS
6
RB Loading Status (cleared on read)
LDRAS
5
RA Loading Status (cleared on read)
CPCS
4
RC Compare Status (cleared on read)
CPBS
3
RB Compare Status (cleared on read)
CPAS
2
RA Compare Status (cleared on read)
LOVRS
1
Load Overrun Status (cleared on read)
COVFS
0
Counter Overflow Status (cleared on read)
TC_CHANNEL2.TC_IERInterrupt Enable Register
Address
0x400400A4
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Enable
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL2.TC_IDRInterrupt Disable Register
Address
0x400400A8
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Disable
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL2.TC_IMRInterrupt Mask Register
Address
0x400400AC
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
Field
Bits
What it does
SECE
10
Security and/or Safety Event Interrupt Mask
RXBUFF
9
Reception Buffer Full
ENDRX
8
End of Receiver Transfer
ETRGS
7
External Trigger
LDRBS
6
RB Loading
LDRAS
5
RA Loading
CPCS
4
RC Compare
CPBS
3
RB Compare
CPAS
2
RA Compare
LOVRS
1
Load Overrun
COVFS
0
Counter Overflow
TC_CHANNEL2.TC_EMRExtended Mode Register
Address
0x400400B0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
NODIVCLK
8
No Divided Clock
TRIGSRCB
5:4
Trigger Source for Input B
0 The trigger/capture input B is driven by external pin TIOBx
1 The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.
TRIGSRCA
1:0
Trigger Source for Input A
0 The trigger/capture input A is driven by external pin TIOAx
1 The trigger/capture input A is driven internally by PWMx
TC_CHANNEL2.TC_CSRChannel Status Register
Address
0x400400B4
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
MTIOB
18
TIOBx Mirror
MTIOA
17
TIOAx Mirror
CLKSTA
16
Clock Enabling Status
TC_CHANNEL2.TC_SSRSafety Status Register
Address
0x400400B8
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
Field
Bits
What it does
SWETYP
27:24
Software Error Type (cleared on read)
0 TC Channel x is enabled and a write-only register has been read (Warning).
1 TC Channel x is enabled and a write access has been performed on a read-only register (Warning).
2 Access to an undefined address of the TC (Warning).
3 TC_RAx or TC_RBx are written while channel is enabled and configured in capture mode (Error).
WPVSRC
23:8
Write Protection Violation Source (cleared on read)
SWE
3
Software Control Error (cleared on read)
SEQE
2
Internal Sequencer Error (cleared on read)
CGD
1
Clock Glitch Detected (cleared on read)
WPVS
0
Write Protection Violation Status (cleared on read)
ECLASS
31
Software Error Class
0 An abnormal access that does not have any impact.
1 An abnormal access that may have an impact.
TC_BCRBlock Control Register
Address
0x400400C0
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
SYNC
0
Synchro Command
TC_BMRBlock Mode Register
Address
0x400400C4
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
MAXFILT
25:20
Maximum Filter
IDXPHB
17
Index Pin is PHB Pin
SWAP
16
Swap PHA and PHB
INVIDX
15
Inverted Index
INVB
14
Inverted PHB
INVA
13
Inverted PHA
EDGPHA
12
Edge on PHA Count Mode
QDTRANS
11
Quadrature Decoding Transparent
SPEEDEN
10
Speed Enabled
POSEN
9
Position Enabled
QDEN
8
Quadrature Decoder Enabled
TC2XC2S
5:4
External Clock Signal 2 Selection
0 Signal connected to XC2: TCLK2
2 Signal connected to XC2: TIOA0
3 Signal connected to XC2: TIOA1
TC1XC1S
3:2
External Clock Signal 1 Selection
0 Signal connected to XC1: TCLK1
2 Signal connected to XC1: TIOA0
3 Signal connected to XC1: TIOA2
TC0XC0S
1:0
External Clock Signal 0 Selection
0 Signal connected to XC0: TCLK0
2 Signal connected to XC0: TIOA1
3 Signal connected to XC0: TIOA2
TC_QIERQDEC Interrupt Enable Register
Address
0x400400C8
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
Field
Bits
What it does
FMP
7
Filtered Missing Pulse
FIDX
6
Filtered Index Line
FPHB
5
Filtered Phase B Line
FPHA
4
Filtered Phase A Line
QERR
2
Quadrature Error
DIRCHG
1
Direction Change
IDX
0
Index
TC_QIDRQDEC Interrupt Disable Register
Address
0x400400CC
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
Field
Bits
What it does
FMP
7
Filtered Missing Pulse
FIDX
6
Filtered Index Line
FPHB
5
Filtered Phase B Line
FPHA
4
Filtered Phase A Line
QERR
2
Quadrature Error
DIRCHG
1
Direction Change
IDX
0
Index
TC_QIMRQDEC Interrupt Mask Register
Address
0x400400D0
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
Field
Bits
What it does
FMP
7
Filtered Missing Pulse
FIDX
6
Filtered Index Line
FPHB
5
Filtered Phase B Line
FPHA
4
Filtered Phase A Line
QERR
2
Quadrature Error
DIRCHG
1
Direction Change
IDX
0
Index
TC_QISRQDEC Interrupt Status Register
Address
0x400400D4
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
DIR
8
Direction
FMP
7
Filtered Missing Pulse
FIDX
6
Filtered Index Line
FPHB
5
Filtered Phase B Line
FPHA
4
Filtered Phase A Line
QERR
2
Quadrature Error
DIRCHG
1
Direction Change
IDX
0
Index
TC_FMRFault Mode Register
Address
0x400400D8
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ENCF1
1
Enable Compare Fault Channel 1
ENCF0
0
Enable Compare Fault Channel 0
TC_QSRQDEC Status Register
Address
0x400400DC
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DIR
8
Direction
TC_WPMRWrite Protection Mode Register
Address
0x400400E4
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
FIRSTE
4
First Error Report Enable
WPCREN
2
Write Protection Control Enable
WPITEN
1
Write Protection Interrupt Enable
WPEN
0
Write Protection Enable
WPKEY
31:8
Write Protection Key
5523789 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
TC_RPRReceive Pointer Register
Address
0x40040100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXPTR
31:0
Receive Pointer Register
TC_RCRReceive Counter Register
Address
0x40040104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXCTR
15:0
Receive Counter Register
TC_RNPRReceive Next Pointer Register
Address
0x40040110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNPTR
31:0
Receive Next Pointer
TC_RNCRReceive Next Counter Register
Address
0x40040114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNCTR
15:0
Receive Next Counter
TC_PTCRTransfer Control Register
Address
0x40040120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
Field
Bits
What it does
ERRCLR
24
Transfer Bus Error Clear
TXCBDIS
19
Transmitter Circular Buffer Disable
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBDIS
17
Receiver Circular Buffer Disable
RXCBEN
16
Receiver Circular Buffer Enable
TXTDIS
9
Transmitter Transfer Disable
TXTEN
8
Transmitter Transfer Enable
RXTDIS
1
Receiver Transfer Disable
RXTEN
0
Receiver Transfer Enable
TC_PTSRTransfer Status Register
Address
0x40040124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
ERR
24
Transfer Bus Error
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBEN
16
Receiver Circular Buffer Enable
TXTEN
8
Transmitter Transfer Enable
RXTEN
0
Receiver Transfer Enable
TC_PWPMRWrite Protection Mode Register
Address
0x40040128
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
WPCREN
2
Write Protection Control Register Enable
WPCTREN
1
Write Protection Counter Registers Enable
WPPTREN
0
Write Protection Pointer Registers Enable
WPKEY
31:8
Write Protection Key
5260355 Writing any other value in this field aborts the write operation. Always reads as 0.
BETA