The 24 registers of UART (Universal Asynchronous Receiver Transmitter), from 0x48010000, with their reset value and every field. The PIC32CX1025MTSH128 has 2920 registers in 63 peripherals, one page each.
UART Universal Asynchronous Receiver Transmitter
UART_CRControl Register
Address
0x48010000
Reset
0x00000000
Access
write only
Size
32-bit
11 fields
Field
Bits
What it does
OPT_SLEEP
14
Optical Logic Sleep Mode Command
REQCLR
12
Request Clear
STTTO
11
Start Time-out
RETTO
10
Rearm Time-out
RSTSTA
8
Reset Status
TXDIS
7
Transmitter Disable
TXEN
6
Transmitter Enable
RXDIS
5
Receiver Disable
RXEN
4
Receiver Enable
RSTTX
3
Reset Transmitter
RSTRX
2
Reset Receiver
UART_MRMode Register
Address
0x48010004
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
OPT_CMPTH
30:28
Receive Path Comparator Threshold
0 Comparator threshold is VDD3V3/2 volts.
1 Comparator threshold is VDD3V3/2.5 volts.
2 Comparator threshold is VDD3V3/3.3 volts.
3 Comparator threshold is VDD3V3/5 volts.
4 Comparator threshold is VDD3V3/10 volts.
OPT_DUTY
26:24
Optical Link Modulation Clock Duty Cycle
0 Modulation clock duty cycle Is 50%.
1 Modulation clock duty cycle Is 43.75%.
2 Modulation clock duty cycle Is 37.5%.
3 Modulation clock duty cycle Is 31.75%.
4 Modulation clock duty cycle Is 25%.
5 Modulation clock duty cycle Is 18.75%.
6 Modulation clock duty cycle Is 12.5%.
7 Modulation clock duty cycle Is 6.25%.
OPT_CLKDIV
20:16
Optical Link Clock Divider
CHMODE
15:14
Channel Mode
0 Normal mode
1 Automatic echo
2 Local loopback
3 Remote loopback
BRSRCCK
12
Baud Rate Source Clock
0 The baud rate is driven by the peripheral clock
1 The baud rate is driven by a PMC-programmable clock GCLK (see the section "Power Management Controller (PMC)").
PAR
11:9
Parity Type
0 Even Parity
1 Odd Parity
2 Space: parity forced to 0
3 Mark: parity forced to 1
4 No parity
OPT_WKUP
8
Optical Link Activity Wake-up Enable
0 To detect any activity on the output of analog comparator, the clock is always active and OPT_EN must be written to 1..
1 If OPT_EN=0 and a logical 1 is detected after inversion (if RXINV=1) on analog comparator output, the clock if automatically enabled for all UART sub-modules. After a period of inactivity on URXD (time-out) the software can instruct the UART to disabled the clock of all sub-modules to reduce power c
EDGESEL
7:6
Analog Comparator Output Edge Selection
0 The UART_SR.ACE is set if a rising edge is detected on analog comparator output.
1 The UART_SR.ACE is set if a falling edge is detected on analog comparator output.
2 The UART_SR.ACE is set as soon as an edge is detected on analog comparator output.
ACON
5
Analog Comparator Enable
0 The analog comparator is disabled. If OPT_EN=1, the analog comparator is enabled.
1 The analog comparator is enabled.
FILTER
4
Receiver Digital Filter
0 UART does not filter the receive line.
1 UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
OPT_DMOD
3
Optical Demodulation Enable
0 The optical demodulator is disabled. External demodulation must be enabled.
1 The optical demodulator is enabled.
OPT_MDINV
2
UART Modulated Data Inverted
0 The output of the modulator is not inverted.
1 The output of the modulator is inverted.
OPT_RXINV
1
UART Receive Data Inverted
0 The comparator data output is not inverted before entering UART.
1 The comparator data output is inverted before entering UART.
OPT_EN
0
UART Optical Interface Enable
0 Disables the UART optical link.
1 Enables the UART optical link.
UART_IERInterrupt Enable Register
Address
0x48010008
Reset
0x00000000
Access
write only
Size
32-bit
13 fields
Field
Bits
What it does
ACE
16
Enable Analog Comparator Event Interrupt
CMP
15
Enable Comparison Interrupt
RXBUFF
12
Enable Buffer Full Interrupt
TXBUFE
11
Enable Buffer Empty Interrupt
TXEMPTY
9
Enable TXEMPTY Interrupt
TIMEOUT
8
Enable Time-out Interrupt
PARE
7
Enable Parity Error Interrupt
FRAME
6
Enable Framing Error Interrupt
OVRE
5
Enable Overrun Error Interrupt
ENDTX
4
Enable End of Transmit Interrupt
ENDRX
3
Enable End of Receive Transfer Interrupt
TXRDY
1
Enable TXRDY Interrupt
RXRDY
0
Enable RXRDY Interrupt
UART_IDRInterrupt Disable Register
Address
0x4801000C
Reset
0x00000000
Access
write only
Size
32-bit
13 fields
Field
Bits
What it does
ACE
16
Disable Analog Comparator Event Interrupt
CMP
15
Disable Comparison Interrupt
RXBUFF
12
Disable Buffer Full Interrupt
TXBUFE
11
Disable Buffer Empty Interrupt
TXEMPTY
9
Disable TXEMPTY Interrupt
TIMEOUT
8
Disable Time-out Interrupt
PARE
7
Disable Parity Error Interrupt
FRAME
6
Disable Framing Error Interrupt
OVRE
5
Disable Overrun Error Interrupt
ENDTX
4
Disable End of Transmit Interrupt
ENDRX
3
Disable End of Receive Transfer Interrupt
TXRDY
1
Disable TXRDY Interrupt
RXRDY
0
Disable RXRDY Interrupt
UART_IMRInterrupt Mask Register
Address
0x48010010
Reset
0x00000000
Access
read only
Size
32-bit
13 fields
Field
Bits
What it does
ACE
16
Mask Analog Comparator Event Interrupt
CMP
15
Mask Comparison Interrupt
RXBUFF
12
Mask RXBUFF Interrupt
TXBUFE
11
Mask TXBUFE Interrupt
TXEMPTY
9
Mask TXEMPTY Interrupt
TIMEOUT
8
Mask Time-out Interrupt
PARE
7
Mask Parity Error Interrupt
FRAME
6
Mask Framing Error Interrupt
OVRE
5
Mask Overrun Error Interrupt
ENDTX
4
Mask End of Transmit Interrupt
ENDRX
3
Mask End of Receive Transfer Interrupt
TXRDY
1
Mask TXRDY Interrupt
RXRDY
0
Mask RXRDY Interrupt
UART_SRInterrupt Status Register
Address
0x48010014
Reset
0x00000000
Access
read only
Size
32-bit
13 fields
Field
Bits
What it does
ACE
16
Analog Comparator Event Interrupt (Cleared by writing UART_CR.RSTSTA)
CMP
15
Comparison Match (Cleared by writing the UART_CR.RSTSTA)
RXBUFF
12
Receive Buffer Full
TXBUFE
11
Transmission Buffer Empty
TXEMPTY
9
Transmitter Empty (Cleared by writing the UART_THR)
TIMEOUT
8
Receiver Time-out (Cleared by writing the UART_CR.STTTO)
PARE
7
Parity Error (Cleared by writing UART_CR.RSTSTA)
FRAME
6
Framing Error (Cleared by writing UART_CR.RSTSTA)
OVRE
5
Overrun Error (Cleared by writing UART_CR.RSTSTA)
ENDTX
4
End of Transmitter Transfer
ENDRX
3
End of Receiver Transfer
TXRDY
1
Transmitter Ready (Cleared by writing the UART_THR)
RXRDY
0
Receiver Ready (Cleared by reading the UART_RHR)
UART_RHRReceive Holding Register
Address
0x48010018
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
RXCHR
7:0
Received Character
UART_THRTransmit Holding Register
Address
0x4801001C
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
TXCHR
7:0
Character to be Transmitted
UART_BRGRBaud Rate Generator Register
Address
0x48010020
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CD
15:0
Clock Divisor
UART_CMPRComparison Register
Address
0x48010024
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
VAL2
23:16
Second Comparison Value for Received Character
CMPPAR
14
Compare Parity
CMPMODE
12
Comparison Mode
0 Any character is received and comparison function drives CMP flag.
1 Comparison condition must be met to start reception.
VAL1
7:0
First Comparison Value for Received Character
UART_RTORReceiver Time-out Register
Address
0x48010028
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TO
7:0
Time-out Value
UART_CSRCurrent Status Register
Address
0x4801002C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
ACO
0
Analog Comparator Output
UART_WPMRWrite Protection Mode Register
Address
0x480100E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
WPEN
0
Write Protection Enable
WPKEY
31:8
Write Protection Key
5587282 Writing any other value in this field aborts the write operation. Always reads as 0.
UART_RPRReceive Pointer Register
Address
0x48010100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXPTR
31:0
Receive Pointer Register
UART_RCRReceive Counter Register
Address
0x48010104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXCTR
15:0
Receive Counter Register
UART_TPRTransmit Pointer Register
Address
0x48010108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXPTR
31:0
Transmit Counter Register
UART_TCRTransmit Counter Register
Address
0x4801010C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXCTR
15:0
Transmit Counter Register
UART_RNPRReceive Next Pointer Register
Address
0x48010110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNPTR
31:0
Receive Next Pointer
UART_RNCRReceive Next Counter Register
Address
0x48010114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNCTR
15:0
Receive Next Counter
UART_TNPRTransmit Next Pointer Register
Address
0x48010118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNPTR
31:0
Transmit Next Pointer
UART_TNCRTransmit Next Counter Register
Address
0x4801011C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNCTR
15:0
Transmit Counter Next
UART_PTCRTransfer Control Register
Address
0x48010120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
Field
Bits
What it does
ERRCLR
24
Transfer Bus Error Clear
TXCBDIS
19
Transmitter Circular Buffer Disable
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBDIS
17
Receiver Circular Buffer Disable
RXCBEN
16
Receiver Circular Buffer Enable
TXTDIS
9
Transmitter Transfer Disable
TXTEN
8
Transmitter Transfer Enable
RXTDIS
1
Receiver Transfer Disable
RXTEN
0
Receiver Transfer Enable
UART_PTSRTransfer Status Register
Address
0x48010124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
ERR
24
Transfer Bus Error
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBEN
16
Receiver Circular Buffer Enable
TXTEN
8
Transmitter Transfer Enable
RXTEN
0
Receiver Transfer Enable
UART_PWPMRWrite Protection Mode Register
Address
0x48010128
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
WPCREN
2
Write Protection Control Register Enable
WPCTREN
1
Write Protection Counter Registers Enable
WPPTREN
0
Write Protection Pointer Registers Enable
WPKEY
31:8
Write Protection Key
5260355 Writing any other value in this field aborts the write operation. Always reads as 0.
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