PIC32CX1025SG60100 EVSYS Registers – 234 with their bits and fields

CTRLAControl

Address: 0x4100E000
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0SWRST

1 field

Field	Bits	What it does
SWRST	0	Software Reset

SWEVTSoftware Event

Address: 0x4100E004
Reset: 0x00000000
Access: write only
Size: 32-bit

32 fields

Field	Bits	What it does
CHANNEL30	30	Channel 30 Software Selection
CHANNEL29	29	Channel 29 Software Selection
CHANNEL28	28	Channel 28 Software Selection
CHANNEL27	27	Channel 27 Software Selection
CHANNEL26	26	Channel 26 Software Selection
CHANNEL25	25	Channel 25 Software Selection
CHANNEL24	24	Channel 24 Software Selection
CHANNEL23	23	Channel 23 Software Selection
CHANNEL22	22	Channel 22 Software Selection
CHANNEL21	21	Channel 21 Software Selection
CHANNEL20	20	Channel 20 Software Selection
CHANNEL19	19	Channel 19 Software Selection
CHANNEL18	18	Channel 18 Software Selection
CHANNEL17	17	Channel 17 Software Selection
CHANNEL16	16	Channel 16 Software Selection
CHANNEL15	15	Channel 15 Software Selection
CHANNEL14	14	Channel 14 Software Selection
CHANNEL13	13	Channel 13 Software Selection
CHANNEL12	12	Channel 12 Software Selection
CHANNEL11	11	Channel 11 Software Selection
CHANNEL10	10	Channel 10 Software Selection
CHANNEL9	9	Channel 9 Software Selection
CHANNEL8	8	Channel 8 Software Selection
CHANNEL7	7	Channel 7 Software Selection
CHANNEL6	6	Channel 6 Software Selection
CHANNEL5	5	Channel 5 Software Selection
CHANNEL4	4	Channel 4 Software Selection
CHANNEL3	3	Channel 3 Software Selection
CHANNEL2	2	Channel 2 Software Selection
CHANNEL1	1	Channel 1 Software Selection
CHANNEL0	0	Channel 0 Software Selection
CHANNEL31	31	Channel 31 Software Selection

PRICTRLPriority Control

Address: 0x4100E008
Reset: 0x00
Access: read/write

7RREN
6–
5–
4–
3PRI3
2PRI2
1PRI1
0PRI0

2 fields

Field	Bits	What it does
RREN	7	Round-Robin Scheduling Enable
PRI	3:0	Channel Priority Number

INTPENDChannel Pending Interrupt

Address: 0x4100E010
Reset: 0x4000
Access: read/write
Size: 16-bit

5 fields

Field	Bits	What it does
BUSY	15	Busy
READY	14	Ready
EVD	9	Channel Event Detected
OVR	8	Channel Overrun
ID	3:0	Channel ID

INTSTATUSInterrupt Status

Address: 0x4100E014
Reset: 0x00000000
Access: read only
Size: 32-bit

12 fields

Field	Bits	What it does
CHINT11	11	Channel 11 Pending Interrupt
CHINT10	10	Channel 10 Pending Interrupt
CHINT9	9	Channel 9 Pending Interrupt
CHINT8	8	Channel 8 Pending Interrupt
CHINT7	7	Channel 7 Pending Interrupt
CHINT6	6	Channel 6 Pending Interrupt
CHINT5	5	Channel 5 Pending Interrupt
CHINT4	4	Channel 4 Pending Interrupt
CHINT3	3	Channel 3 Pending Interrupt
CHINT2	2	Channel 2 Pending Interrupt
CHINT1	1	Channel 1 Pending Interrupt
CHINT0	0	Channel 0 Pending Interrupt

BUSYCHBusy Channels

Address: 0x4100E018
Reset: 0x00000000
Access: read only
Size: 32-bit

12 fields

Field	Bits	What it does
BUSYCH11	11	Busy Channel 11
BUSYCH10	10	Busy Channel 10
BUSYCH9	9	Busy Channel 9
BUSYCH8	8	Busy Channel 8
BUSYCH7	7	Busy Channel 7
BUSYCH6	6	Busy Channel 6
BUSYCH5	5	Busy Channel 5
BUSYCH4	4	Busy Channel 4
BUSYCH3	3	Busy Channel 3
BUSYCH2	2	Busy Channel 2
BUSYCH1	1	Busy Channel 1
BUSYCH0	0	Busy Channel 0

READYUSRReady Users

Address: 0x4100E01C
Reset: 0xFFFFFFFF
Access: read only
Size: 32-bit

12 fields

Field	Bits	What it does
READYUSR11	11	Ready User for Channel 11
READYUSR10	10	Ready User for Channel 10
READYUSR9	9	Ready User for Channel 9
READYUSR8	8	Ready User for Channel 8
READYUSR7	7	Ready User for Channel 7
READYUSR6	6	Ready User for Channel 6
READYUSR5	5	Ready User for Channel 5
READYUSR4	4	Ready User for Channel 4
READYUSR3	3	Ready User for Channel 3
READYUSR2	2	Ready User for Channel 2
READYUSR1	1	Ready User for Channel 1
READYUSR0	0	Ready User for Channel 0

CHANNEL0.CHANNELChannel n Control

Address: 0x4100E020
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL0.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E024
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL0.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E025
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL0.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E026
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL0.CHSTATUSChannel n Status

Address: 0x4100E027
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL1.CHANNELChannel n Control

Address: 0x4100E028
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL1.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E02C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL1.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E02D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL1.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E02E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL1.CHSTATUSChannel n Status

Address: 0x4100E02F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL2.CHANNELChannel n Control

Address: 0x4100E030
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL2.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E034
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL2.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E035
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL2.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E036
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL2.CHSTATUSChannel n Status

Address: 0x4100E037
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL3.CHANNELChannel n Control

Address: 0x4100E038
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL3.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E03C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL3.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E03D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL3.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E03E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL3.CHSTATUSChannel n Status

Address: 0x4100E03F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL4.CHANNELChannel n Control

Address: 0x4100E040
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL4.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E044
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL4.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E045
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL4.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E046
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL4.CHSTATUSChannel n Status

Address: 0x4100E047
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL5.CHANNELChannel n Control

Address: 0x4100E048
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL5.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E04C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL5.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E04D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL5.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E04E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL5.CHSTATUSChannel n Status

Address: 0x4100E04F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL6.CHANNELChannel n Control

Address: 0x4100E050
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL6.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E054
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL6.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E055
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL6.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E056
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL6.CHSTATUSChannel n Status

Address: 0x4100E057
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL7.CHANNELChannel n Control

Address: 0x4100E058
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL7.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E05C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL7.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E05D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL7.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E05E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL7.CHSTATUSChannel n Status

Address: 0x4100E05F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL8.CHANNELChannel n Control

Address: 0x4100E060
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL8.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E064
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL8.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E065
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL8.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E066
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL8.CHSTATUSChannel n Status

Address: 0x4100E067
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL9.CHANNELChannel n Control

Address: 0x4100E068
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL9.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E06C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL9.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E06D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL9.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E06E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL9.CHSTATUSChannel n Status

Address: 0x4100E06F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL10.CHANNELChannel n Control

Address: 0x4100E070
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL10.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E074
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL10.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E075
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL10.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E076
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL10.CHSTATUSChannel n Status

Address: 0x4100E077
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL11.CHANNELChannel n Control

Address: 0x4100E078
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL11.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E07C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL11.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E07D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL11.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E07E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL11.CHSTATUSChannel n Status

Address: 0x4100E07F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL12.CHANNELChannel n Control

Address: 0x4100E080
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL12.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E084
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL12.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E085
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL12.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E086
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL12.CHSTATUSChannel n Status

Address: 0x4100E087
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL13.CHANNELChannel n Control

Address: 0x4100E088
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL13.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E08C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL13.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E08D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL13.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E08E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL13.CHSTATUSChannel n Status

Address: 0x4100E08F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL14.CHANNELChannel n Control

Address: 0x4100E090
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL14.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E094
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL14.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E095
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL14.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E096
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL14.CHSTATUSChannel n Status

Address: 0x4100E097
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL15.CHANNELChannel n Control

Address: 0x4100E098
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL15.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E09C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL15.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E09D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL15.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E09E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL15.CHSTATUSChannel n Status

Address: 0x4100E09F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL16.CHANNELChannel n Control

Address: 0x4100E0A0
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL16.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0A4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL16.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0A5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL16.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0A6
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL16.CHSTATUSChannel n Status

Address: 0x4100E0A7
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL17.CHANNELChannel n Control

Address: 0x4100E0A8
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL17.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0AC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL17.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0AD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL17.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0AE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL17.CHSTATUSChannel n Status

Address: 0x4100E0AF
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL18.CHANNELChannel n Control

Address: 0x4100E0B0
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL18.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0B4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL18.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0B5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL18.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0B6
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL18.CHSTATUSChannel n Status

Address: 0x4100E0B7
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL19.CHANNELChannel n Control

Address: 0x4100E0B8
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL19.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0BC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL19.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0BD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL19.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0BE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL19.CHSTATUSChannel n Status

Address: 0x4100E0BF
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL20.CHANNELChannel n Control

Address: 0x4100E0C0
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL20.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0C4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL20.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0C5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL20.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0C6
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL20.CHSTATUSChannel n Status

Address: 0x4100E0C7
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL21.CHANNELChannel n Control

Address: 0x4100E0C8
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL21.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0CC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL21.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0CD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL21.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0CE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL21.CHSTATUSChannel n Status

Address: 0x4100E0CF
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL22.CHANNELChannel n Control

Address: 0x4100E0D0
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL22.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0D4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL22.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0D5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL22.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0D6
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL22.CHSTATUSChannel n Status

Address: 0x4100E0D7
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL23.CHANNELChannel n Control

Address: 0x4100E0D8
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL23.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0DC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL23.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0DD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL23.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0DE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL23.CHSTATUSChannel n Status

Address: 0x4100E0DF
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL24.CHANNELChannel n Control

Address: 0x4100E0E0
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL24.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0E4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL24.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0E5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL24.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0E6
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL24.CHSTATUSChannel n Status

Address: 0x4100E0E7
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL25.CHANNELChannel n Control

Address: 0x4100E0E8
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL25.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0EC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL25.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0ED
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL25.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0EE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL25.CHSTATUSChannel n Status

Address: 0x4100E0EF
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL26.CHANNELChannel n Control

Address: 0x4100E0F0
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL26.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0F4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL26.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0F5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL26.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0F6
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL26.CHSTATUSChannel n Status

Address: 0x4100E0F7
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL27.CHANNELChannel n Control

Address: 0x4100E0F8
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL27.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E0FC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL27.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E0FD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL27.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E0FE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL27.CHSTATUSChannel n Status

Address: 0x4100E0FF
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL28.CHANNELChannel n Control

Address: 0x4100E100
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL28.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E104
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL28.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E105
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL28.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E106
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL28.CHSTATUSChannel n Status

Address: 0x4100E107
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL29.CHANNELChannel n Control

Address: 0x4100E108
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL29.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E10C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL29.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E10D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL29.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E10E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL29.CHSTATUSChannel n Status

Address: 0x4100E10F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL30.CHANNELChannel n Control

Address: 0x4100E110
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL30.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E114
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL30.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E115
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL30.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E116
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL30.CHSTATUSChannel n Status

Address: 0x4100E117
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

CHANNEL31.CHANNELChannel n Control

Address: 0x4100E118
Reset: 0x00008000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
ONDEMAND	15	Generic Clock On Demand
RUNSTDBY	14	Run in standby
EDGSEL	11:10	Edge Detection Selection `0` No event output when using the resynchronized or synchronous path `1` Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path `2` Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path `3` Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
PATH	9:8	Path Selection `0` Synchronous path `1` Resynchronized path `2` Asynchronous path
EVGEN	6:0	Event Generator Selection

CHANNEL31.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100E11C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Disable
OVR	0	Channel Overrun Interrupt Disable

CHANNEL31.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100E11D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected Interrupt Enable
OVR	0	Channel Overrun Interrupt Enable

CHANNEL31.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100E11E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1EVD
0OVR

2 fields

Field	Bits	What it does
EVD	1	Channel Event Detected
OVR	0	Channel Overrun

CHANNEL31.CHSTATUSChannel n Status

Address: 0x4100E11F
Reset: 0x01
Access: read only

7–
6–
5–
4–
3–
2–
1BUSYCH
0RDYUSR

2 fields

Field	Bits	What it does
BUSYCH	1	Busy Channel
RDYUSR	0	Ready User

USER0User Multiplexer n

Address: 0x4100E120
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER1User Multiplexer n

Address: 0x4100E124
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER2User Multiplexer n

Address: 0x4100E128
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER3User Multiplexer n

Address: 0x4100E12C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER4User Multiplexer n

Address: 0x4100E130
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER5User Multiplexer n

Address: 0x4100E134
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER6User Multiplexer n

Address: 0x4100E138
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER7User Multiplexer n

Address: 0x4100E13C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER8User Multiplexer n

Address: 0x4100E140
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER9User Multiplexer n

Address: 0x4100E144
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER10User Multiplexer n

Address: 0x4100E148
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER11User Multiplexer n

Address: 0x4100E14C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER12User Multiplexer n

Address: 0x4100E150
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER13User Multiplexer n

Address: 0x4100E154
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER14User Multiplexer n

Address: 0x4100E158
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER15User Multiplexer n

Address: 0x4100E15C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER16User Multiplexer n

Address: 0x4100E160
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER17User Multiplexer n

Address: 0x4100E164
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER18User Multiplexer n

Address: 0x4100E168
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER19User Multiplexer n

Address: 0x4100E16C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER20User Multiplexer n

Address: 0x4100E170
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER21User Multiplexer n

Address: 0x4100E174
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER22User Multiplexer n

Address: 0x4100E178
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER23User Multiplexer n

Address: 0x4100E17C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER24User Multiplexer n

Address: 0x4100E180
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER25User Multiplexer n

Address: 0x4100E184
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER26User Multiplexer n

Address: 0x4100E188
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER27User Multiplexer n

Address: 0x4100E18C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER28User Multiplexer n

Address: 0x4100E190
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER29User Multiplexer n

Address: 0x4100E194
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER30User Multiplexer n

Address: 0x4100E198
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER31User Multiplexer n

Address: 0x4100E19C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER32User Multiplexer n

Address: 0x4100E1A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER33User Multiplexer n

Address: 0x4100E1A4
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER34User Multiplexer n

Address: 0x4100E1A8
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER35User Multiplexer n

Address: 0x4100E1AC
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER36User Multiplexer n

Address: 0x4100E1B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER37User Multiplexer n

Address: 0x4100E1B4
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER38User Multiplexer n

Address: 0x4100E1B8
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER39User Multiplexer n

Address: 0x4100E1BC
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER40User Multiplexer n

Address: 0x4100E1C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER41User Multiplexer n

Address: 0x4100E1C4
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER42User Multiplexer n

Address: 0x4100E1C8
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER43User Multiplexer n

Address: 0x4100E1CC
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER44User Multiplexer n

Address: 0x4100E1D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER45User Multiplexer n

Address: 0x4100E1D4
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER46User Multiplexer n

Address: 0x4100E1D8
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER47User Multiplexer n

Address: 0x4100E1DC
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER48User Multiplexer n

Address: 0x4100E1E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER49User Multiplexer n

Address: 0x4100E1E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER50User Multiplexer n

Address: 0x4100E1E8
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER51User Multiplexer n

Address: 0x4100E1EC
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER52User Multiplexer n

Address: 0x4100E1F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER53User Multiplexer n

Address: 0x4100E1F4
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER54User Multiplexer n

Address: 0x4100E1F8
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER55User Multiplexer n

Address: 0x4100E1FC
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER56User Multiplexer n

Address: 0x4100E200
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER57User Multiplexer n

Address: 0x4100E204
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER58User Multiplexer n

Address: 0x4100E208
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER59User Multiplexer n

Address: 0x4100E20C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER60User Multiplexer n

Address: 0x4100E210
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER61User Multiplexer n

Address: 0x4100E214
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER62User Multiplexer n

Address: 0x4100E218
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER63User Multiplexer n

Address: 0x4100E21C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER64User Multiplexer n

Address: 0x4100E220
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER65User Multiplexer n

Address: 0x4100E224
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

USER66User Multiplexer n

Address: 0x4100E228
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CHANNEL	5:0	Channel Event Selection

EVSYS Event System Interface