PIC32CX1025SG61100 DMAC registers

The 271 registers of DMAC (Direct Memory Access Controller), from 0x4100A000, with their reset value and every field. The PIC32CX1025SG61100 has 2953 registers in 69 peripherals, one page each.

DMAC Direct Memory Access Controller

CTRLControl

Address: 0x4100A000
Reset: 0x0000
Access: read/write
Size: 16-bit

6 fields

Field	Bits	What it does
LVLEN3	11	Priority Level 3 Enable
LVLEN2	10	Priority Level 2 Enable
LVLEN1	9	Priority Level 1 Enable
LVLEN0	8	Priority Level 0 Enable
DMAENABLE	1	DMA Enable
SWRST	0	Software Reset

CRCCTRLCRC Control

Address: 0x4100A002
Reset: 0x0000
Access: read/write
Size: 16-bit

4 fields

Field	Bits	What it does
CRCMODE	15:14	CRC Operating Mode `0` Default operating mode `2` Memory CRC monitor operating mode `3` Memory CRC generation operating mode
CRCSRC	13:8	CRC Input Source `0` CRC Disabled `1` I/O interface `32` DMA Channel 0 `33` DMA Channel 1 `34` DMA Channel 2 `35` DMA Channel 3 `36` DMA Channel 4 `37` DMA Channel 5 `38` DMA Channel 6 `39` DMA Channel 7 `40` DMA Channel 8 `41` DMA Channel 9 `42` DMA Channel 10 `43` DMA Channel 11 `44` DMA Channel 12 `45` DMA Channel 13 `46` DMA Channel 14 `47` DMA Channel 15 `48` DMA Channel 16 `49` DMA Channel 17 `50` DMA Channel 18 `51` DMA Channel 19 `52` DMA Channel 20 `53` DMA Channel 21 `54` DMA Channel 22 `55` DMA Channel 23 `56` DMA Channel 24 `57` DMA Channel 25 `58` DMA Channel 26 `59` DMA Channel 27 `60` DMA Channel 28 `61` DMA Channel 29 `62` DMA Channel 30 `63` DMA Channel 31
CRCPOLY	3:2	CRC Polynomial Type `0` CRC-16 (CRC-CCITT) `1` CRC32 (IEEE 802.3)
CRCBEATSIZE	1:0	CRC Beat Size `0` 8-bit bus transfer `1` 16-bit bus transfer `2` 32-bit bus transfer

CRCDATAINCRC Data Input

Address: 0x4100A004
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CRCDATAIN	31:0	CRC Data Input

CRCCHKSUMCRC Checksum

Address: 0x4100A008
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CRCCHKSUM	31:0	CRC Checksum

CRCSTATUSCRC Status

Address: 0x4100A00C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2CRCERR
1CRCZERO
0CRCBUSY

3 fields

Field	Bits	What it does
CRCERR	2	CRC Error
CRCZERO	1	CRC Zero
CRCBUSY	0	CRC Module Busy

DBGCTRLDebug Control

Address: 0x4100A00D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0DBGRUN

1 field

Field	Bits	What it does
DBGRUN	0	Debug Run

SWTRIGCTRLSoftware Trigger Control

Address: 0x4100A010
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
SWTRIG30	30	Channel 30 Software Trigger
SWTRIG29	29	Channel 29 Software Trigger
SWTRIG28	28	Channel 28 Software Trigger
SWTRIG27	27	Channel 27 Software Trigger
SWTRIG26	26	Channel 26 Software Trigger
SWTRIG25	25	Channel 25 Software Trigger
SWTRIG24	24	Channel 24 Software Trigger
SWTRIG23	23	Channel 23 Software Trigger
SWTRIG22	22	Channel 22 Software Trigger
SWTRIG21	21	Channel 21 Software Trigger
SWTRIG20	20	Channel 20 Software Trigger
SWTRIG19	19	Channel 19 Software Trigger
SWTRIG18	18	Channel 18 Software Trigger
SWTRIG17	17	Channel 17 Software Trigger
SWTRIG16	16	Channel 16 Software Trigger
SWTRIG15	15	Channel 15 Software Trigger
SWTRIG14	14	Channel 14 Software Trigger
SWTRIG13	13	Channel 13 Software Trigger
SWTRIG12	12	Channel 12 Software Trigger
SWTRIG11	11	Channel 11 Software Trigger
SWTRIG10	10	Channel 10 Software Trigger
SWTRIG9	9	Channel 9 Software Trigger
SWTRIG8	8	Channel 8 Software Trigger
SWTRIG7	7	Channel 7 Software Trigger
SWTRIG6	6	Channel 6 Software Trigger
SWTRIG5	5	Channel 5 Software Trigger
SWTRIG4	4	Channel 4 Software Trigger
SWTRIG3	3	Channel 3 Software Trigger
SWTRIG2	2	Channel 2 Software Trigger
SWTRIG1	1	Channel 1 Software Trigger
SWTRIG0	0	Channel 0 Software Trigger
SWTRIG31	31	Channel 31 Software Trigger

PRICTRL0Priority Control 0

Address: 0x4100A014
Reset: 0x40404040
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
QOS3	30:29	Level 3 Quality of Service `0` Regular delivery `1` Bandwidth shortage `2` Latency sensitive `3` Latency critical
LVLPRI3	28:24	Level 3 Channel Priority Number
RRLVLEN2	23	Level 2 Round-Robin Scheduling Enable
QOS2	22:21	Level 2 Quality of Service `0` Regular delivery `1` Bandwidth shortage `2` Latency sensitive `3` Latency critical
LVLPRI2	20:16	Level 2 Channel Priority Number
RRLVLEN1	15	Level 1 Round-Robin Scheduling Enable
QOS1	14:13	Level 1 Quality of Service `0` Regular delivery `1` Bandwidth shortage `2` Latency sensitive `3` Latency critical
LVLPRI1	12:8	Level 1 Channel Priority Number
RRLVLEN0	7	Level 0 Round-Robin Scheduling Enable
QOS0	6:5	Level 0 Quality of Service `0` Regular delivery `1` Bandwidth shortage `2` Latency sensitive `3` Latency critical
LVLPRI0	4:0	Level 0 Channel Priority Number
RRLVLEN3	31	Level 3 Round-Robin Scheduling Enable

INTPENDInterrupt Pending

Address: 0x4100A020
Reset: 0x0000
Access: read/write
Size: 16-bit

8 fields

Field	Bits	What it does
PEND	15	Pending
BUSY	14	Busy
FERR	13	Fetch Error
CRCERR	12	CRC Error
SUSP	10	Channel Suspend
TCMPL	9	Transfer Complete
TERR	8	Transfer Error
ID	4:0	Channel ID

INTSTATUSInterrupt Status

Address: 0x4100A024
Reset: 0x00000000
Access: read only
Size: 32-bit

32 fields

Field	Bits	What it does
CHINT30	30	Channel 30 Pending Interrupt
CHINT29	29	Channel 29 Pending Interrupt
CHINT28	28	Channel 28 Pending Interrupt
CHINT27	27	Channel 27 Pending Interrupt
CHINT26	26	Channel 26 Pending Interrupt
CHINT25	25	Channel 25 Pending Interrupt
CHINT24	24	Channel 24 Pending Interrupt
CHINT23	23	Channel 23 Pending Interrupt
CHINT22	22	Channel 22 Pending Interrupt
CHINT21	21	Channel 21 Pending Interrupt
CHINT20	20	Channel 20 Pending Interrupt
CHINT19	19	Channel 19 Pending Interrupt
CHINT18	18	Channel 18 Pending Interrupt
CHINT17	17	Channel 17 Pending Interrupt
CHINT16	16	Channel 16 Pending Interrupt
CHINT15	15	Channel 15 Pending Interrupt
CHINT14	14	Channel 14 Pending Interrupt
CHINT13	13	Channel 13 Pending Interrupt
CHINT12	12	Channel 12 Pending Interrupt
CHINT11	11	Channel 11 Pending Interrupt
CHINT10	10	Channel 10 Pending Interrupt
CHINT9	9	Channel 9 Pending Interrupt
CHINT8	8	Channel 8 Pending Interrupt
CHINT7	7	Channel 7 Pending Interrupt
CHINT6	6	Channel 6 Pending Interrupt
CHINT5	5	Channel 5 Pending Interrupt
CHINT4	4	Channel 4 Pending Interrupt
CHINT3	3	Channel 3 Pending Interrupt
CHINT2	2	Channel 2 Pending Interrupt
CHINT1	1	Channel 1 Pending Interrupt
CHINT0	0	Channel 0 Pending Interrupt
CHINT31	31	Channel 31 Pending Interrupt

BUSYCHBusy Channels

Address: 0x4100A028
Reset: 0x00000000
Access: read only
Size: 32-bit

32 fields

Field	Bits	What it does
BUSYCH30	30	Busy Channel 30
BUSYCH29	29	Busy Channel 29
BUSYCH28	28	Busy Channel 28
BUSYCH27	27	Busy Channel 27
BUSYCH26	26	Busy Channel 26
BUSYCH25	25	Busy Channel 25
BUSYCH24	24	Busy Channel 24
BUSYCH23	23	Busy Channel 23
BUSYCH22	22	Busy Channel 22
BUSYCH21	21	Busy Channel 21
BUSYCH20	20	Busy Channel 20
BUSYCH19	19	Busy Channel 19
BUSYCH18	18	Busy Channel 18
BUSYCH17	17	Busy Channel 17
BUSYCH16	16	Busy Channel 16
BUSYCH15	15	Busy Channel 15
BUSYCH14	14	Busy Channel 14
BUSYCH13	13	Busy Channel 13
BUSYCH12	12	Busy Channel 12
BUSYCH11	11	Busy Channel 11
BUSYCH10	10	Busy Channel 10
BUSYCH9	9	Busy Channel 9
BUSYCH8	8	Busy Channel 8
BUSYCH7	7	Busy Channel 7
BUSYCH6	6	Busy Channel 6
BUSYCH5	5	Busy Channel 5
BUSYCH4	4	Busy Channel 4
BUSYCH3	3	Busy Channel 3
BUSYCH2	2	Busy Channel 2
BUSYCH1	1	Busy Channel 1
BUSYCH0	0	Busy Channel 0
BUSYCH31	31	Busy Channel 31

PENDCHPending Channels

Address: 0x4100A02C
Reset: 0x00000000
Access: read only
Size: 32-bit

32 fields

Field	Bits	What it does
PENDCH30	30	Pending Channel 30
PENDCH29	29	Pending Channel 29
PENDCH28	28	Pending Channel 28
PENDCH27	27	Pending Channel 27
PENDCH26	26	Pending Channel 26
PENDCH25	25	Pending Channel 25
PENDCH24	24	Pending Channel 24
PENDCH23	23	Pending Channel 23
PENDCH22	22	Pending Channel 22
PENDCH21	21	Pending Channel 21
PENDCH20	20	Pending Channel 20
PENDCH19	19	Pending Channel 19
PENDCH18	18	Pending Channel 18
PENDCH17	17	Pending Channel 17
PENDCH16	16	Pending Channel 16
PENDCH15	15	Pending Channel 15
PENDCH14	14	Pending Channel 14
PENDCH13	13	Pending Channel 13
PENDCH12	12	Pending Channel 12
PENDCH11	11	Pending Channel 11
PENDCH10	10	Pending Channel 10
PENDCH9	9	Pending Channel 9
PENDCH8	8	Pending Channel 8
PENDCH7	7	Pending Channel 7
PENDCH6	6	Pending Channel 6
PENDCH5	5	Pending Channel 5
PENDCH4	4	Pending Channel 4
PENDCH3	3	Pending Channel 3
PENDCH2	2	Pending Channel 2
PENDCH1	1	Pending Channel 1
PENDCH0	0	Pending Channel 0
PENDCH31	31	Pending Channel 31

ACTIVEActive Channel and Levels

Address: 0x4100A030
Reset: 0x00000000
Access: read only
Size: 32-bit

7 fields

Field	Bits	What it does
ABUSY	15	Active Channel Busy
ID	12:8	Active Channel ID
LVLEX3	3	Level 3 Channel Trigger Request Executing
LVLEX2	2	Level 2 Channel Trigger Request Executing
LVLEX1	1	Level 1 Channel Trigger Request Executing
LVLEX0	0	Level 0 Channel Trigger Request Executing
BTCNT	31:16	Active Channel Block Transfer Count

BASEADDRDescriptor Memory Section Base Address

Address: 0x4100A034
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
BASEADDR	31:0	Descriptor Memory Base Address

WRBADDRWrite-Back Memory Section Base Address

Address: 0x4100A038
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
WRBADDR	31:0	Write-Back Memory Base Address

CHANNEL0.CHCTRLAChannel n Control A

Address: 0x4100A040
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL0.CHCTRLBChannel n Control B

Address: 0x4100A044
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL0.CHPRILVLChannel n Priority Level

Address: 0x4100A045
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL0.CHEVCTRLChannel n Event Control

Address: 0x4100A046
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL0.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A04C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL0.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A04D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL0.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A04E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL0.CHSTATUSChannel n Status

Address: 0x4100A04F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL1.CHCTRLAChannel n Control A

Address: 0x4100A050
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL1.CHCTRLBChannel n Control B

Address: 0x4100A054
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL1.CHPRILVLChannel n Priority Level

Address: 0x4100A055
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL1.CHEVCTRLChannel n Event Control

Address: 0x4100A056
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL1.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A05C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL1.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A05D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL1.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A05E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL1.CHSTATUSChannel n Status

Address: 0x4100A05F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL2.CHCTRLAChannel n Control A

Address: 0x4100A060
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL2.CHCTRLBChannel n Control B

Address: 0x4100A064
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL2.CHPRILVLChannel n Priority Level

Address: 0x4100A065
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL2.CHEVCTRLChannel n Event Control

Address: 0x4100A066
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL2.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A06C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL2.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A06D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL2.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A06E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL2.CHSTATUSChannel n Status

Address: 0x4100A06F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL3.CHCTRLAChannel n Control A

Address: 0x4100A070
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL3.CHCTRLBChannel n Control B

Address: 0x4100A074
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL3.CHPRILVLChannel n Priority Level

Address: 0x4100A075
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL3.CHEVCTRLChannel n Event Control

Address: 0x4100A076
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL3.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A07C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL3.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A07D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL3.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A07E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL3.CHSTATUSChannel n Status

Address: 0x4100A07F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL4.CHCTRLAChannel n Control A

Address: 0x4100A080
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL4.CHCTRLBChannel n Control B

Address: 0x4100A084
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL4.CHPRILVLChannel n Priority Level

Address: 0x4100A085
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL4.CHEVCTRLChannel n Event Control

Address: 0x4100A086
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL4.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A08C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL4.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A08D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL4.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A08E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL4.CHSTATUSChannel n Status

Address: 0x4100A08F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL5.CHCTRLAChannel n Control A

Address: 0x4100A090
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL5.CHCTRLBChannel n Control B

Address: 0x4100A094
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL5.CHPRILVLChannel n Priority Level

Address: 0x4100A095
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL5.CHEVCTRLChannel n Event Control

Address: 0x4100A096
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL5.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A09C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL5.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A09D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL5.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A09E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL5.CHSTATUSChannel n Status

Address: 0x4100A09F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL6.CHCTRLAChannel n Control A

Address: 0x4100A0A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL6.CHCTRLBChannel n Control B

Address: 0x4100A0A4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL6.CHPRILVLChannel n Priority Level

Address: 0x4100A0A5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL6.CHEVCTRLChannel n Event Control

Address: 0x4100A0A6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL6.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A0AC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL6.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A0AD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL6.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A0AE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL6.CHSTATUSChannel n Status

Address: 0x4100A0AF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL7.CHCTRLAChannel n Control A

Address: 0x4100A0B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL7.CHCTRLBChannel n Control B

Address: 0x4100A0B4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL7.CHPRILVLChannel n Priority Level

Address: 0x4100A0B5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL7.CHEVCTRLChannel n Event Control

Address: 0x4100A0B6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL7.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A0BC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL7.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A0BD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL7.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A0BE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL7.CHSTATUSChannel n Status

Address: 0x4100A0BF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL8.CHCTRLAChannel n Control A

Address: 0x4100A0C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL8.CHCTRLBChannel n Control B

Address: 0x4100A0C4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL8.CHPRILVLChannel n Priority Level

Address: 0x4100A0C5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL8.CHEVCTRLChannel n Event Control

Address: 0x4100A0C6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL8.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A0CC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL8.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A0CD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL8.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A0CE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL8.CHSTATUSChannel n Status

Address: 0x4100A0CF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL9.CHCTRLAChannel n Control A

Address: 0x4100A0D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL9.CHCTRLBChannel n Control B

Address: 0x4100A0D4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL9.CHPRILVLChannel n Priority Level

Address: 0x4100A0D5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL9.CHEVCTRLChannel n Event Control

Address: 0x4100A0D6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL9.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A0DC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL9.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A0DD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL9.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A0DE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL9.CHSTATUSChannel n Status

Address: 0x4100A0DF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL10.CHCTRLAChannel n Control A

Address: 0x4100A0E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL10.CHCTRLBChannel n Control B

Address: 0x4100A0E4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL10.CHPRILVLChannel n Priority Level

Address: 0x4100A0E5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL10.CHEVCTRLChannel n Event Control

Address: 0x4100A0E6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL10.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A0EC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL10.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A0ED
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL10.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A0EE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL10.CHSTATUSChannel n Status

Address: 0x4100A0EF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL11.CHCTRLAChannel n Control A

Address: 0x4100A0F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL11.CHCTRLBChannel n Control B

Address: 0x4100A0F4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL11.CHPRILVLChannel n Priority Level

Address: 0x4100A0F5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL11.CHEVCTRLChannel n Event Control

Address: 0x4100A0F6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL11.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A0FC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL11.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A0FD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL11.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A0FE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL11.CHSTATUSChannel n Status

Address: 0x4100A0FF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL12.CHCTRLAChannel n Control A

Address: 0x4100A100
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL12.CHCTRLBChannel n Control B

Address: 0x4100A104
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL12.CHPRILVLChannel n Priority Level

Address: 0x4100A105
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL12.CHEVCTRLChannel n Event Control

Address: 0x4100A106
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL12.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A10C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL12.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A10D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL12.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A10E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL12.CHSTATUSChannel n Status

Address: 0x4100A10F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL13.CHCTRLAChannel n Control A

Address: 0x4100A110
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL13.CHCTRLBChannel n Control B

Address: 0x4100A114
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL13.CHPRILVLChannel n Priority Level

Address: 0x4100A115
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL13.CHEVCTRLChannel n Event Control

Address: 0x4100A116
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL13.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A11C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL13.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A11D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL13.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A11E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL13.CHSTATUSChannel n Status

Address: 0x4100A11F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL14.CHCTRLAChannel n Control A

Address: 0x4100A120
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL14.CHCTRLBChannel n Control B

Address: 0x4100A124
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL14.CHPRILVLChannel n Priority Level

Address: 0x4100A125
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL14.CHEVCTRLChannel n Event Control

Address: 0x4100A126
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL14.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A12C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL14.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A12D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL14.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A12E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL14.CHSTATUSChannel n Status

Address: 0x4100A12F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL15.CHCTRLAChannel n Control A

Address: 0x4100A130
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL15.CHCTRLBChannel n Control B

Address: 0x4100A134
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL15.CHPRILVLChannel n Priority Level

Address: 0x4100A135
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL15.CHEVCTRLChannel n Event Control

Address: 0x4100A136
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL15.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A13C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL15.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A13D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL15.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A13E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL15.CHSTATUSChannel n Status

Address: 0x4100A13F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL16.CHCTRLAChannel n Control A

Address: 0x4100A140
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL16.CHCTRLBChannel n Control B

Address: 0x4100A144
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL16.CHPRILVLChannel n Priority Level

Address: 0x4100A145
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL16.CHEVCTRLChannel n Event Control

Address: 0x4100A146
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL16.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A14C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL16.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A14D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL16.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A14E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL16.CHSTATUSChannel n Status

Address: 0x4100A14F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL17.CHCTRLAChannel n Control A

Address: 0x4100A150
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL17.CHCTRLBChannel n Control B

Address: 0x4100A154
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL17.CHPRILVLChannel n Priority Level

Address: 0x4100A155
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL17.CHEVCTRLChannel n Event Control

Address: 0x4100A156
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL17.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A15C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL17.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A15D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL17.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A15E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL17.CHSTATUSChannel n Status

Address: 0x4100A15F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL18.CHCTRLAChannel n Control A

Address: 0x4100A160
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL18.CHCTRLBChannel n Control B

Address: 0x4100A164
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL18.CHPRILVLChannel n Priority Level

Address: 0x4100A165
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL18.CHEVCTRLChannel n Event Control

Address: 0x4100A166
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL18.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A16C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL18.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A16D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL18.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A16E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL18.CHSTATUSChannel n Status

Address: 0x4100A16F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL19.CHCTRLAChannel n Control A

Address: 0x4100A170
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL19.CHCTRLBChannel n Control B

Address: 0x4100A174
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL19.CHPRILVLChannel n Priority Level

Address: 0x4100A175
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL19.CHEVCTRLChannel n Event Control

Address: 0x4100A176
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL19.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A17C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL19.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A17D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL19.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A17E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL19.CHSTATUSChannel n Status

Address: 0x4100A17F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL20.CHCTRLAChannel n Control A

Address: 0x4100A180
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL20.CHCTRLBChannel n Control B

Address: 0x4100A184
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL20.CHPRILVLChannel n Priority Level

Address: 0x4100A185
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL20.CHEVCTRLChannel n Event Control

Address: 0x4100A186
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL20.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A18C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL20.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A18D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL20.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A18E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL20.CHSTATUSChannel n Status

Address: 0x4100A18F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL21.CHCTRLAChannel n Control A

Address: 0x4100A190
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL21.CHCTRLBChannel n Control B

Address: 0x4100A194
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL21.CHPRILVLChannel n Priority Level

Address: 0x4100A195
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL21.CHEVCTRLChannel n Event Control

Address: 0x4100A196
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL21.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A19C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL21.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A19D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL21.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A19E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL21.CHSTATUSChannel n Status

Address: 0x4100A19F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL22.CHCTRLAChannel n Control A

Address: 0x4100A1A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL22.CHCTRLBChannel n Control B

Address: 0x4100A1A4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL22.CHPRILVLChannel n Priority Level

Address: 0x4100A1A5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL22.CHEVCTRLChannel n Event Control

Address: 0x4100A1A6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL22.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A1AC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL22.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A1AD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL22.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A1AE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL22.CHSTATUSChannel n Status

Address: 0x4100A1AF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL23.CHCTRLAChannel n Control A

Address: 0x4100A1B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL23.CHCTRLBChannel n Control B

Address: 0x4100A1B4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL23.CHPRILVLChannel n Priority Level

Address: 0x4100A1B5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL23.CHEVCTRLChannel n Event Control

Address: 0x4100A1B6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL23.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A1BC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL23.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A1BD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL23.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A1BE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL23.CHSTATUSChannel n Status

Address: 0x4100A1BF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL24.CHCTRLAChannel n Control A

Address: 0x4100A1C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL24.CHCTRLBChannel n Control B

Address: 0x4100A1C4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL24.CHPRILVLChannel n Priority Level

Address: 0x4100A1C5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL24.CHEVCTRLChannel n Event Control

Address: 0x4100A1C6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL24.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A1CC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL24.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A1CD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL24.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A1CE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL24.CHSTATUSChannel n Status

Address: 0x4100A1CF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL25.CHCTRLAChannel n Control A

Address: 0x4100A1D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL25.CHCTRLBChannel n Control B

Address: 0x4100A1D4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL25.CHPRILVLChannel n Priority Level

Address: 0x4100A1D5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL25.CHEVCTRLChannel n Event Control

Address: 0x4100A1D6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL25.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A1DC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL25.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A1DD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL25.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A1DE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL25.CHSTATUSChannel n Status

Address: 0x4100A1DF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL26.CHCTRLAChannel n Control A

Address: 0x4100A1E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL26.CHCTRLBChannel n Control B

Address: 0x4100A1E4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL26.CHPRILVLChannel n Priority Level

Address: 0x4100A1E5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL26.CHEVCTRLChannel n Event Control

Address: 0x4100A1E6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL26.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A1EC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL26.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A1ED
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL26.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A1EE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL26.CHSTATUSChannel n Status

Address: 0x4100A1EF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL27.CHCTRLAChannel n Control A

Address: 0x4100A1F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL27.CHCTRLBChannel n Control B

Address: 0x4100A1F4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL27.CHPRILVLChannel n Priority Level

Address: 0x4100A1F5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL27.CHEVCTRLChannel n Event Control

Address: 0x4100A1F6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL27.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A1FC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL27.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A1FD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL27.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A1FE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL27.CHSTATUSChannel n Status

Address: 0x4100A1FF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL28.CHCTRLAChannel n Control A

Address: 0x4100A200
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL28.CHCTRLBChannel n Control B

Address: 0x4100A204
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL28.CHPRILVLChannel n Priority Level

Address: 0x4100A205
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL28.CHEVCTRLChannel n Event Control

Address: 0x4100A206
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL28.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A20C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL28.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A20D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL28.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A20E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL28.CHSTATUSChannel n Status

Address: 0x4100A20F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL29.CHCTRLAChannel n Control A

Address: 0x4100A210
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL29.CHCTRLBChannel n Control B

Address: 0x4100A214
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL29.CHPRILVLChannel n Priority Level

Address: 0x4100A215
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL29.CHEVCTRLChannel n Event Control

Address: 0x4100A216
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL29.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A21C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL29.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A21D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL29.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A21E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL29.CHSTATUSChannel n Status

Address: 0x4100A21F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL30.CHCTRLAChannel n Control A

Address: 0x4100A220
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL30.CHCTRLBChannel n Control B

Address: 0x4100A224
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL30.CHPRILVLChannel n Priority Level

Address: 0x4100A225
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL30.CHEVCTRLChannel n Event Control

Address: 0x4100A226
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL30.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A22C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL30.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A22D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL30.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A22E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL30.CHSTATUSChannel n Status

Address: 0x4100A22F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL31.CHCTRLAChannel n Control A

Address: 0x4100A230
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	14:8	Trigger Source `0` Only software/event triggers
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL31.CHCTRLBChannel n Control B

Address: 0x4100A234
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL31.CHPRILVLChannel n Priority Level

Address: 0x4100A235
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL31.CHEVCTRLChannel n Event Control

Address: 0x4100A236
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL31.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100A23C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL31.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100A23D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL31.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100A23E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL31.CHSTATUSChannel n Status

Address: 0x4100A23F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending