PIC32CX2051BZ66048 CFG registers

The 64 registers of CFG, from 0x44000000, with their reset value and every field. The PIC32CX2051BZ66048 has 3597 registers in 73 peripherals, one page each.

CFG

CFGCON0

Address: 0x44000000
Reset: 0x7900000B
Access: read/write
Size: 32-bit

25 fields

Field	Bits	What it does
FRECCDIS	30	Flex RAM ECC Control
FECCCON	29:28	Flash ECC Control
CMEN	27	SPA/DPA Countermeasures Enable
INT0P	26	INT0P Polarity
INT0E	25	INT0 Enable
PCM	24	PCHE I/D Cacheable Mode
SMBUS3EN2	23	SMBus3 Enable for SERCOM2
VBUSONIO	22	USB VBUS_ON Selection bit
USBIDIO	21	USB USBID Selection bit
HPLUGDIS	20	Hot Plugging Disable (Outside Fuse Loading)
UPLLHWMD	19	UWPLL HW Control Mode for PWDN and RESET
EPLLHWMD	18	EWPLL HW Control Mode for PWDN and RESET
USBSSEN	17	USB Suspend Sleep Enable
CFGCLOCK	15:14	Configuration Register Lock
IOLOCK	13	IO LOCK
PMDLOCK	12	Peripheral Module Disable (PMD) LOCK
PGLCOK	11	Permission Group LOCK
PMULOCK	10	PMU Controller Register LOCK
RTCOUT_ALTEN	9	RTCOUT Alternate Enable
RTCIN0_ALTEN	8	RTCIN0 Alternate Enable
CPENFILT	7	ADC CP Filter Enable
ADCPOVR	4	ADC Charge Pump Override
JTAGEN	3	JTAG Enable
TROEN	2	Trace Output Enable
SWOEN	1	SWO enable on 2-wire debug interface

CFGCON0CLRBit clear register

Address: 0x44000004
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON0SETBit set register

Address: 0x44000008
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON0INVBit invert register

Address: 0x4400000C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON1

Address: 0x44000010
Reset: 0x1F00403B
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
CLKZBREF	30	External Reference Clock ZB Enable
QSPIDDRM	29	QSPI DDR Mode Clock Enable
WDTPSS	28:24	Watchdog Timer Post-scale Select Sleep
QSCHE_EN	15	QSPI Address Space Cache Attribute
SMCLR	14	Selects CRU handling of MCLR Control
SCOM2_HSEN	13	SERCOM2 Direct (High Speed) Pin Enable
SCOM1_HSEN	12	SERCOM1 Direct (High Speed) Pin Enable
SCOM0_HSEN	11	SERCOM0 Direct (High Speed) Pin Enable
QSPI_HSEN	10	QSPI (Direct) Enable
CMP1_OE	9	Analog Comparator-1 Output Enable
CMP0_OE	8	Analog Comparator-0 Output Enable
ZBTWKSYS	7	ZBT Subsystem External Wake-up source
CCL_OE	6	CCL Pads (via PPS) Output Enable
TRCEN	5	Trace Enable
CAN0_PIN_EN	2	CAN0 Pin Enable
CAN1_PIN_EN	31	CAN1 Pin Enable

CFGCON1CLRBit clear register

Address: 0x44000014
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON1SETBit set register

Address: 0x44000018
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON1INVBit invert register

Address: 0x4400001C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON2

Address: 0x44000020
Reset: 0x7F7FFF38
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
DMTCNT	30:26	Dead Man Timer Count Select
WDTWINSZ	25:24	Watchdog Timer Window Size
WDTEN	23	Watchdog Timer Enable
WINDIS	22	Windowed Watchdog Timer Disable
WDTSPGM	21	Watchdog Timer Stop during Flash Programming
WDTPSR	20:16	Watchdog Timer Post-scale Select Run
FSCMEN	15	Fail-Safe Clock Monitor Enable
CKSWEN	14	Software Clock Switching Enable
WAKE2SPD	13	2-Speed startup enabled in Sleep mode
SOSCSEL	12	SOSC Selection Configuration
WDTRMCS	11:10	WDT RUN Mode Clock Select
POSCMOD	9:8	Primary Oscillator Configuration
PMUTEST_VDD_EN	7	PMU Test Output or VDD/2 Enable via ADC IE12
DMTINTV	5:3	Dead Man Timer Count Window Interval
ACMP_CYCLE	2:0	AC SIB Comparator Result Wait Cycles
DMTEN	31	Dead Man Timer Enable

CFGCON2CLRBit clear register

Address: 0x44000024
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON2SETBit set register

Address: 0x44000028
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON2INVBit invert register

Address: 0x4400002C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON4

Address: 0x44000040
Reset: 0x840E4000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
LPOSCEN	30	Low Power (Secondary) Oscillator Enable
UVREGROVR	29	ULPVREG Retention Mode Override
DSEN	28	Deep Sleep Bit Enable
DSWDTEN	27	Deep Sleep Watchdog Timer Enable
DSWDTOSC	26	Deep Sleep Watchdog Timer Reference Clock Select
DSWDTPS	25:21	Deep Sleep Watchdog Timer Postscale Select
DSZPBOREN	20	Deep Sleep Zero-Power BOR Enable
CPEN_DLY	19:17	Charge-pump ready digital delay
RTCEVTYPE	16	RTC Event Type
LPCLK_MOD	15	LPCLK modifier in counter/delay mode
VBKP_DIVSEL	14	VDDBUKPCORE LPCLK Clock Divider Selection
VBKP_32KCSEL	13:12	VDDBUKPCORE 32KHz clock source selection
VBKP_1KCSEL	11	VDDBUKPCORE LPCLK Clock Selection
RTCEVENT_EN	10	Pad Output Enable for MCHP legacy RTC event output
RTCEVENT_SEL	9:8	RTC Event Selection
SOSC_CFG	7:0	SOSC Configuration
RTCNTM_CSEL	31	RTC Counter Mode Clock Select

CFGCON4CLRBit clear register

Address: 0x44000044
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON4SETBit set register

Address: 0x44000048
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGCON4INVBit invert register

Address: 0x4400004C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPGQOS1

Address: 0x44000050
Reset: 0xE040004C
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
FCQOS	29:28	FC Controller QOS Control
DSUPG	25:24	DSU Permission Group
CRYPTOQOS	23:22	Crypto QOS Control
CRYPTOPG	21:20	Crypto Permission Group
DMAPG	9:8	DMA (Rd/Wr) Permission Group
CPUQOS	3:2	CPU I/D and System Bus QOS Control
CPUPG	1:0	CPU (Code) Permission Group
WISIBQOS	31:30	Wireless SIB QOS Control

CFGPGQOS1CLRBit clear register

Address: 0x44000054
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPGQOS1SETBit set register

Address: 0x44000058
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPGQOS1INVBit invert register

Address: 0x4400005C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPGQOS2

Address: 0x44000060
Reset: 0x00004404
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CAN1QOS	15:14	CAN1 QOS Control bits
CAN1PG	13:12	CAN1 Permission Group
CAN0QOS	11:10	CAN0 QOS Control bits
CAN0PG	9:8	CAN0 Permission Group
ADCQOS	3:2	ADC QOS Control bits
ADCPG	1:0	ADC Permission Group

CFGPGQOS2CLRBit clear register

Address: 0x44000064
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPGQOS2SETBit set register

Address: 0x44000068
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPGQOS2INVBit invert register

Address: 0x4400006C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGI2C

Address: 0x44000070
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
SLRTEN6	30	SLRT Enable for SERCOM6
SLRTEN2	26	SLRT Enable for SERCOM2
SLRTEN1	25	SLRT Enable for SERCOM1
SLRTEN0	24	SLRT Enable for SERCOM0
SLRCTRL6	22	I2C Slew Rate Control for SERCOM6
SLRCTRL2	18	I2C Slew Rate Control for SERCOM2
SLRCTRL1	17	I2C Slew Rate Control for SERCOM1
SLRCTRL0	16	I2C Slew Rate Control for SERCOM0
I2CDSEL6	14	I2C Delay Select for SERCOM6
I2CDSEL2	10	I2C Delay Select for SERCOM2
I2CDSEL1	9	I2C Delay Select for SERCOM1
I2CDSEL0	8	I2C Delay Select for SERCOM0
SMBUSEN6	6	SMBus Enable for SERCOM6
SMBUSEN2	2	SMBus Enable for SERCOM2
SMBUSEN1	1	SMBus Enable for SERCOM1
SMBUSEN0	0	SMBus Enable for SERCOM0

CFGI2CCLRBit clear register

Address: 0x44000074
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGI2CSETBit set register

Address: 0x44000078
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGI2CINVBit invert register

Address: 0x4400007C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN1

Address: 0x44000080
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
CM4TCSEL	30:28	CM4T Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
SERCOM_3_4_5_CD	27	SERCOM3/4/5 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
SERCOM_3_4_5_CSEL	26:24	SERCOM3/4/5 Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
TCC_1_2_CD	23	TCC1/2 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
TCC_1_2_CSEL	22:20	TCC1/2 Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
SERCOM_6_CD	19	SERCOM6 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
SERCOM_6_CSEL	18:16	SERCOM6 Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
SERCOM_0_1_2_CD	15	SERCOM0/1/2 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
SERCOM_0_1_2_CSEL	14:12	SERCOM0/1/2 Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
FREQM_MSR_CD	11	FREQMMC Clock Disable `0` Disable PGCLK `1` Enable PGCLK
FREQM_MSR_CSEL	10:8	FREQMMC Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
FREQM_REF_CD	7	FREQMRC Clock Disable `0` Disable PGCLK `1` Enable PGCLK
FREQM_REF_CSEL	6:4	FREQMRC Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EIC__CCL_CD	3	EIC/CCL Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EIC__CCL_CSEL	2:0	EIC/CCL Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
CM4TCD	31	CM4T Clock Disable `0` Disable PGCLK `1` Enable PGCLK

CFGPCLKGEN1CLRBit clear register

Address: 0x44000084
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN1SETBit set register

Address: 0x44000088
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN1INVBit invert register

Address: 0x4400008C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN2

Address: 0x44000090
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
EVSYS_8_CSEL	30:28	EVSYSC8 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_7_CD	27	EVSYSC7 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_7_CSEL	26:24	EVSYSC7 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_6_CD	23	EVSYSC6 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_6_CSEL	22:20	EVSYSC6 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_5_CD	19	EVSYSC5 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_5_CSEL	18:16	EVSYSC5 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_4_CD	15	EVSYSC4 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_4_CSEL	14:12	EVSYSC4 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_3_CD	11	EVSYSC3 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_3_CSEL	10:8	EVSYSC3 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_2_CD	7	EVSYSC2 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_2_CSEL	6:4	EVSYSC2 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_1_CD	3	EVSYSC1 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_1_CSEL	2:0	EVSYSC1 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_8_CD	31	EVSYSC8 Clock Disable `0` Disable PGCLK `1` Enable PGCLK

CFGPCLKGEN2CLRBit clear register

Address: 0x44000094
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN2SETBit set register

Address: 0x44000098
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN2INVBit invert register

Address: 0x4400009C
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN3

Address: 0x440000A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
CVDCSEL	30:28	CVD Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
ETHCD	27	Ethernet Clock Disable `0` Disable PGCLK `1` Enable PGCLK
ETHCSEL	26:24	Ethernet Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
TCC_0_CD	23	TCC0 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
TCC_0_CSEL	22:20	TCC0 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
ACCD	19	AC Clock Disable `0` Disable PGCLK `1` Enable PGCLK
ACCSEL	18:16	AC Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_12_CD	15	EVSYSC12 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_12_CSEL	14:12	EVSYSC12 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_11_CD	11	EVSYSC11 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_11_CSEL	10:8	EVSYSC11 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_10_CD	7	EVSYSC10 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_10_CSEL	6:4	EVSYSC10 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
EVSYS_9_CD	3	EVSYSC9 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
EVSYS_9_CSEL	2:0	EVSYSC9 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
CVDCD	31	CVD Clock Disable `0` Disable PGCLK `1` Enable PGCLK

CFGPCLKGEN3CLRBit clear register

Address: 0x440000A4
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN3SETBit set register

Address: 0x440000A8
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN3INVBit invert register

Address: 0x440000AC
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN4

Address: 0x440000B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
CAN_1_CSEL	30:28	CAN1 Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
CAN_0_CD	27	CAN0 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
CAN_0_CSEL	26:24	CAN0 Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
TC_8_9_CD	23	TC89 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
TC_8_9_CSEL	22:20	TC89 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
TC_6_7_CD	19	TC67 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
TC_6_7_CSEL	18:16	TC67 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
TC_4_5_CD	15	TC45 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
TC_4_5_CSEL	14:12	TC45 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
TC_2_3_CD	11	TC23 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
TC_2_3_CSEL	10:8	TC23 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
TC_1_CD	7	TC1 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
TC_1_CSEL	6:4	TC1 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
TC_0_CD	3	TC0 Clock Disable `0` Disable PGCLK `1` Enable PGCLK
TC_0_CSEL	2:0	TC0 Peripheral Clock Selection `0` No Clock `1` Reference Clock 1 `2` Reference Clock 2 `3` Reference Clock 3 `4` Reference Clock 4 `5` Reference Clock 5 `6` Reference Clock 6 `7` 32 KHz Low Power Clock
CAN_1_CD	31	CAN1 Clock Disable `0` Disable PGCLK `1` Enable PGCLK

CFGPCLKGEN4CLRBit clear register

Address: 0x440000B4
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN4SETBit set register

Address: 0x440000B8
Reset: 0x00000000
Access: read/write
Size: 32-bit

CFGPCLKGEN4INVBit invert register

Address: 0x440000BC
Reset: 0x00000000
Access: read/write
Size: 32-bit

USER_ID

Address: 0x440000C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
USER_ID	15:0	User unique ID, readable using the SWD USER_ID instruction

USER_IDCLRBit clear register

Address: 0x440000C4
Reset: 0x00000000
Access: read/write
Size: 32-bit

USER_IDSETBit set register

Address: 0x440000C8
Reset: 0x00000000
Access: read/write
Size: 32-bit

USER_IDINVBit invert register

Address: 0x440000CC
Reset: 0x00000000
Access: read/write
Size: 32-bit

SYSKEY

Address: 0x440000D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SYSKEY	31:0	System Key

PMD1

Address: 0x440000E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
SQIMD	29	SQI Module Disable
RTCCMD	16	RTCC Module Disable
ADCSARSHRMD	10	Shared ADC SAR Core Module Disable
CVDMD	9	ADC CVD Module Disable
ADCSARMD	8	ADC SAR Core Module Disable
ADCMD	7	ADC Controller Module Disable
ACMD	6	AC Module Disable
DACMD	5	DAC Module Disable

PMD1CLRBit clear register

Address: 0x440000E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

PMD1SETBit set register

Address: 0x440000E8
Reset: 0x00000000
Access: read/write
Size: 32-bit

PMD1INVBit invert register

Address: 0x440000EC
Reset: 0x00000000
Access: read/write
Size: 32-bit

PMD2

Address: 0x440000F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
REFO3MD	30	Reference (Clock) Out 3 Module Disable
REFO2MD	29	Reference (Clock) Out 2 Module Disable
REFO1MD	28	Reference (Clock) Out 1 Module Disable
REFO6MD	25	Reference (Clock) Out 6 Module Disable
REFO5MD	24	Reference (Clock) Out 5 Module Disable
REFO4MD	31	Reference (Clock) Out 4 Module Disable

PMD2CLRBit clear register

Address: 0x440000F4
Reset: 0x00000000
Access: read/write
Size: 32-bit

PMD2SETBit set register

Address: 0x440000F8
Reset: 0x00000000
Access: read/write
Size: 32-bit

PMD2INVBit invert register

Address: 0x440000FC
Reset: 0x00000000
Access: read/write
Size: 32-bit

PMD3

Address: 0x44000100
Reset: 0x00000000
Access: read/write
Size: 32-bit

25 fields

Field	Bits	What it does
CAN1MD	27	CAN1 Module Disable
CAN0MD	26	CAN0 Module Disable
ETHMD	25	Ethernet Module Disable
USBMD	24	USB Module Disable
TCC2MD	22	TCC2 Module Disable
TCC1MD	21	TCC1 Module Disable
TCC0MD	20	TCC0 Module Disable
TC9MD	17	TC9 Module Disable
TC8MD	16	TC8 Module Disable
TC7MD	15	TC7 Module Disable
TC6MD	14	TC6 Module Disable
TC5MD	13	TC5 Module Disable
TC4MD	12	TC4 Module Disable
TC3MD	11	TC3 Module Disable
TC2MD	10	TC2 Module Disable
TC1MD	9	TC1 Module Disable
TC0MD	8	TC0 Module Disable
QEIMD	7	QEI Module Disable
SER6MD	6	SERCOM6 Module Disable
SER5MD	5	SERCOM5 Module Disable
SER4MD	4	SERCOM4 Module Disable
SER3MD	3	SERCOM3 Module Disable
SER2MD	2	SERCOM2 Module Disable
SER1MD	1	SERCOM1 Module Disable
SER0MD	0	SERCOM0 Module Disable

PMD3CLRBit clear register

Address: 0x44000104
Reset: 0x00000000
Access: read/write
Size: 32-bit

PMD3SETBit set register

Address: 0x44000108
Reset: 0x00000000
Access: read/write
Size: 32-bit

PMD3INVBit invert register

Address: 0x4400010C
Reset: 0x00000000
Access: read/write
Size: 32-bit

MISCSTAT

Address: 0x44000120
Reset: 0x01000081
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CM4SWRST_EN	11	CM4 SW Reset Enable
CLDORDY	9	CLDO Ready

IDDevice ID

Address: 0x44000160
Reset: 0x00000000
Access: read only
Size: 32-bit

BCFG0

Address: 0x44000200
Reset: 0x00000000
Access: read only
Size: 32-bit

4 fields

Field	Bits	What it does
SIGN	29	Flash SIGN
CP	28	Boot Code Protect
PCSCMODE	1	PCHE Single cache Mode
BINFOVALID0	31	First 256-bit BCFG information Valid