PIC32CX2051BZ66048 CRU registers

The 104 registers of CRU, from 0x44000A00, with their reset value and every field. The PIC32CX2051BZ66048 has 3597 registers in 73 peripherals, one page each.

CRU

OSCCONCRU OSCILLATOR CONTROL REGISTER

Address: 0x44000A00
Reset: 0x00200001
Access: read/write
Size: 32-bit

10 fields

Field	Bits	What it does
FRCDIV	26:24	Fast RC Clock Divider bits `0` FRC Divide by 1 `1` FRC Divide by 2 `2` FRC Divide by 4 `3` FRC Divide by 8 `4` FRC Divide by 16 `5` FRC Divide by 32 `6` FRC Divide by 64 `7` FRC Divide by 256
DRMEN	23	Enable Dream Mode bit `0` DMA transfer has no effect `1` When the cpu_si_sleep input is asserted and SLPEN = 1, DMA transfer complete causes SLEEP Mode to be entered
WAKE2SPD	21	2-Speed startup enabled in Sleep mode bit `0` When the device EXITS Sleep Mode, the sys_clk will be from the selected clock. `1` When the device EXITS Sleep Mode, the sys_clk will be from FRC until the selected clock is ready
COSC	15:12	Current Oscillator Selection bits (Read-only) `0` Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV (Supports FRC/16 and FRC/1) `1` System PLL (SPLL1 Module) (input clock and divider set by SPLLCON) `2` Primary Oscillator- POSC `3` Secondary Oscillator (SOSC) `4` Low Power RC Oscillator (LPRC) `5` Ethernet PLL Clock-2 (EPLL Module) (input clock and divider set by APLLCON) `6` USB PLL Clock (UPLL Module) (input clock and divider set by UPLLCON)
NOSC	11:8	New Oscillator Selection bits `0` Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV ( Supports FRC/16 and FRC/1) `1` System PLL (SPLL1 Module) (input clock and divider set by SPLLCON) `2` Primary Oscillator `3` Secondary Oscillator (SOSC) `4` Low Power RC Oscillator (LPRC) `5` Ethernet PLL Clock-2 (EPLL Module) (input clock and divider set by APLLCON) `6` USB PLL Clock (UPLL Module) (input clock and divider set by UPLLCON)
CLKLOCK	7	Clock Lock Enabled bit `0` Clock and PLL selection registers are not locked, configurations may be modified `1` All clock and PLL configuration registers are locked. These include OSCCON, OSCTRIM, SPLLCON, UPLLCON, PBxDIV
SLPEN	4	Enable SLEEP Mode bit `0` When a WAIT instruction is executed device will enter IDLE Mode `1` When a WAIT Instruction is executed device will enter SLEEP Mode
CF	3	Clock Fail Detect bit (Read / writable / Clearable by application) `0` FSCM has not detected clock failure `1` FSCM has detected clock failure
SOSCEN	1	32 kHz Secondary (LP) Oscillator Enable bit `0` Disable Secondary Oscillator `1` Enable Secondary Oscillator
OSWEN	0	Oscillator Switch Enable bit `0` Oscillator switch is complete `1` Request oscillator switch to selection specified by NOSC[3:0] bits

OSCCONCLR

Address: 0x44000A04
Reset: 0x00000000
Access: read/write
Size: 32-bit

OSCCONSET

Address: 0x44000A08
Reset: 0x00000000
Access: read/write
Size: 32-bit

OSCCONINV

Address: 0x44000A0C
Reset: 0x00000000
Access: read/write
Size: 32-bit

OSCTUNCRU OSCILLATOR TRIMMING REGISTER

Address: 0x44000A10
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TUN	5:0	Internal Fast RC (FRC) Oscillator Tuning bits `0` Center Frequency, oscillator is running at calibrated frequency `31` Maximum Frequency `32` Minimum Frequency

OSCTUNCLR

Address: 0x44000A14
Reset: 0x00000000
Access: read/write
Size: 32-bit

OSCTUNSET

Address: 0x44000A18
Reset: 0x00000000
Access: read/write
Size: 32-bit

OSCTUNINV

Address: 0x44000A1C
Reset: 0x00000000
Access: read/write
Size: 32-bit

SPLLCONSPLL CONTROL REGISTER

Address: 0x44000A20
Reset: 0xC0010008
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
SPLLPOSTDIV2	19:16	SPLL Clock 2 Divide Value, 1 to 15 `0` Disable `1` Second post divide by 1 `2` Second post divide by 2 `3` Second post divide by 3 `4` Second post divide by 4 `5` Second post divide by 5 `6` Second post divide by 6 `7` Second post divide by 7 `8` Second post divide by 8 `9` Second post divide by 9 `10` Second post divide by 10 `11` Second post divide by 11 `12` Second post divide by 12 `13` Second post divide by 13 `14` Second post divide by 14 `15` Second post divide by 15
SPLLPOSTDIV1	15:8	SPLL Clock 1 Divide Value, 1 to 255
SPLLRST	5	System PLL Reset `0` De-assert the reset to the SPLL `1` Assert the reset to the SPLL
SPLLFLOCK	4	System PLL Force Lock `0` Do not force the SPLL lock signal to be asserted `1` Force the SPLL lock signal to be asserted
SPLLPWDN	3	PLL Power Down Register bit `0` PLL is active `1` PLL is powered down
SPLL_BYP	31:30	SPLL Clock 2 Source `0` SPLL3 (RFPLL) Clock is the clock source for ADC CP Clock Generation. `2` POSC is used as clock source for ADC CP Clock Generation. `3` FRC is used as clock source for ADC CP Clock Generation.

SPLLCONCLR

Address: 0x44000A24
Reset: 0x00000000
Access: read/write
Size: 32-bit

SPLLCONSET

Address: 0x44000A28
Reset: 0x00000000
Access: read/write
Size: 32-bit

SPLLCONINV

Address: 0x44000A2C
Reset: 0x00000000
Access: read/write
Size: 32-bit

UPLLCONUPLL CONTROL REGISTER

Address: 0x44000A30
Reset: 0x80000808
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
UPLLREFDIV	27:22	Reference Frequency Divide in between 1 and 63, value of 0 is unused.
UPLLFBDIV	21:12	PLL feedback divider in between 16 and 1023, values of 0 to 15 are unused
UPLLRST	11	USB PLL Reset `0` De-assert the reset to the UPLL `1` Assert the reset to the UPLL
UPLLFLOCK	10	USB PLL Force Lock `0` Do not force the SPLL lock signal to be asserted `1` Force the UPLL lock signal to be asserted
UPLLPOSTDIV1	9:4	First Post Divide Value in between 1 and 63, value of 0 is unused.
UPLLPWDN	3	UPLL Power Down Register bit `0` UPLL is active `1` UPLL is powered down
UPLLBSWSEL	2:0	UPLL Bandwidth Select `1` UPLL closed loop bandwith 400KHz `2` UPLL closed loop bandwith 1MHz `3` UPLL closed loop bandwith 2MHz `4` UPLL closed loop bandwith 3MHz
UPLL_BYP	31	The input clock REF bypasses PLL to PLLOUTx `0` The input clock dont bypass `1` UPLL Bypass; when this bit is set, the input clock REF bypasses PLL to PLLOUTx

UPLLCONCLR

Address: 0x44000A34
Reset: 0x00000000
Access: read/write
Size: 32-bit

UPLLCONSET

Address: 0x44000A38
Reset: 0x00000000
Access: read/write
Size: 32-bit

UPLLCONINV

Address: 0x44000A3C
Reset: 0x00000000
Access: read/write
Size: 32-bit

EPLLCONEPLL CONTROL REGISTER

Address: 0x44000A40
Reset: 0x80000808
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
ECLKOUTEN	28	Ethernet Clock Out pin Enable `0` ETH_CLK_OUT Pin is disabled `1` ETH_CLK_OUT Pin is enabled
EPLLREFDIV	27:22	Reference Frequency Divide in between 1 and 63, value of 0 is unused.
EPLLFBDIV	21:12	PLL feedback divider in between 16 and 1023, values of 0 to 15 are unused
EPLLRST	11	Ethernet PLL Reset `0` De-assert the reset to the EPLL `1` Assert the reset to the EPLL
EPLLFLOCK	10	Ethernet PLL Force Lock `0` Do not force the SPLL lock signal to be asserted `1` Force the EPLL lock signal to be asserted
EPLLPOSTDIV1	9:4	First Post Divide Value in between 1 and 63, value of 0 is unused.
EPLLPWDN	3	EPLL Power Down Register bit `0` EPLL is active `1` EPLL is powered down
EPLLBSWSEL	2:0	EPLL Bandwidth Select `1` EPLL closed loop bandwith 400KHz `2` EPLL closed loop bandwith 1MHz `3` EPLL closed loop bandwith 2MHz `4` EPLL closed loop bandwith 3MHz
EPLL_BYP	31	The input clock REF bypasses PLL to PLLOUTx `0` The input clock dont bypass `1` EPLL Bypass; when this bit is set, the input clock REF bypasses PLL to PLLOUTx

EPLLCONCLR

Address: 0x44000A44
Reset: 0x00000000
Access: read/write
Size: 32-bit

EPLLCONSET

Address: 0x44000A48
Reset: 0x00000000
Access: read/write
Size: 32-bit

EPLLCONINV

Address: 0x44000A4C
Reset: 0x00000000
Access: read/write
Size: 32-bit

APLLCONAPLL CONTROL REGISTER

Address: 0x44000A50
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
EPLLPOSTIDIV2	5:0	EPLL Post Divider bits for controlling second PLL clock output, value of 0 is unused.

APLLCONCLR

Address: 0x44000A54
Reset: 0x00000000
Access: read/write
Size: 32-bit

APLLCONSET

Address: 0x44000A58
Reset: 0x00000000
Access: read/write
Size: 32-bit

APLLCONINV

Address: 0x44000A5C
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO1CONREFERENCE OSCILLATOR 1 CONTROL REGISTER

Address: 0x44000AA0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
RODIV	30:16	Reference Clock Divider bits `0` REFO1 clock is same frequency as Base clock (no divider) `1` REFO1 clock is Base clock frequency divided by 2 (12) `2` REFO1 clock is Base clock frequency divided by 4 (22) `32767` REFO1 clock is Base clock frequency divided by 65,534 (32,767 *2)
ON	15	Output Enable bit `0` Reference Oscillator Module disabled `1` Reference Oscillator Module enabled
FRZ	14	Freeze in Debug mode bit `0` When emulator is in Debug mode, module continues operation `1` When emulator is in Debug mode, module freezes operation
SIDL	13	Peripheral Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
OE	12	Reference Clock Output Enable bit `0` Reference clock is not driven out on REFO1 pin. `1` Reference clock is driven out on REFO1 pin
RSLP	11	Reference Oscillator Run in Sleep bit `0` Reference Oscillator output is disabled in Sleep `1` Reference Oscillator output continues to run in Sleep
DIVSWEN	9	Clock RODIV/ROTRIM switch enabled. `0` Clock Divider Switch has completed. `1` Clock Divider Switching currently in progress.
ACTIVE	8	Reference Clock Request Status bit `0` Reference clock request is not active (User can update this REFOCON register) `1` Reference clock request is active (User should not update this REFOCON register)
ROSEL	3:0	Reference Clock Source Select bits `0` FRC `1` System PLL1 (Clock-1) `2` POSC `3` SOSC `4` LPRC `5` Ethernet PLL2 (Clock-2) `6` USB PLL `7` System PLL3 (Clock-3) `8` Ethernet PLL1 (Clock-1) `9` Peripheral clock 1 (reference clock reflects any peripheral clock switching) `10` System clock (reference clock reflects any device clock switching) `11` REFI Pin

REFO1CONCLR

Address: 0x44000AA4
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO1CONSET

Address: 0x44000AA8
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO1CONINV

Address: 0x44000AAC
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO1TRIMREFERENCE OSCILLATOR 1 TRIM REGISTER

Address: 0x44000AB0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ROTRIM	31:23	Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock `0` 0/512 (0.0) divisor added to RODIV value `1` 1/512 (0.001953125) divisor added to RODIV value `2` 2/512 (0.00390625) divisor added to RODIV value `256` 256/512 (0.5000) divisor added to RODIV value `511` 511/512 (0.998046875) divisor added to RODIV value

REFO1TRIMCLR

Address: 0x44000AB4
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO1TRIMSET

Address: 0x44000AB8
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO1TRIMINV

Address: 0x44000ABC
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO2CONREFERENCE OSCILLATOR 2 CONTROL REGISTER

Address: 0x44000AC0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
RODIV	30:16	Reference Clock Divider bits `0` REFO2 clock is same frequency as Base clock (no divider) `1` REFO2 clock is Base clock frequency divided by 2 (12) `2` REFO2 clock is Base clock frequency divided by 4 (22) `32767` REFO2 clock is Base clock frequency divided by 65,534 (32,767 *2)
ON	15	Output Enable bit `0` Reference Oscillator Module disabled `1` Reference Oscillator Module enabled
FRZ	14	Freeze in Debug mode bit `0` When emulator is in Debug mode, module continues operation `1` When emulator is in Debug mode, module freezes operation
SIDL	13	Peripheral Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
OE	12	Reference Clock Output Enable bit `0` Reference clock is not driven out on REFO2 pin. `1` Reference clock is driven out on REFO2 pin
RSLP	11	Reference Oscillator Run in Sleep bit `0` Reference Oscillator output is disabled in Sleep `1` Reference Oscillator output continues to run in Sleep
DIVSWEN	9	Clock RODIV/ROTRIM switch enabled. `0` Clock Divider Switch has completed. `1` Clock Divider Switching currently in progress.
ACTIVE	8	Reference Clock Request Status bit `0` Reference clock request is not active (User can update this REFOCON register) `1` Reference clock request is active (User should not update this REFOCON register)
ROSEL	3:0	Reference Clock Source Select bits `0` FRC `1` System PLL1 (Clock-1) `2` POSC `3` SOSC `4` LPRC `5` Ethernet PLL2 (Clock-2) `6` USB PLL `7` System PLL3 (Clock-3) `8` Ethernet PLL1 (Clock-1) `9` Peripheral clock 1 (reference clock reflects any peripheral clock switching) `10` System clock (reference clock reflects any device clock switching) `11` REFI Pin

REFO2CONCLR

Address: 0x44000AC4
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO2CONSET

Address: 0x44000AC8
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO2CONINV

Address: 0x44000ACC
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO2TRIMREFERENCE OSCILLATOR 2 TRIM REGISTER

Address: 0x44000AD0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ROTRIM	31:23	Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock `0` 0/512 (0.0) divisor added to RODIV value `1` 1/512 (0.001953125) divisor added to RODIV value `2` 2/512 (0.00390625) divisor added to RODIV value `256` 256/512 (0.5000) divisor added to RODIV value `511` 511/512 (0.998046875) divisor added to RODIV value

REFO2TRIMCLR

Address: 0x44000AD4
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO2TRIMSET

Address: 0x44000AD8
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO2TRIMINV

Address: 0x44000ADC
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO3CONREFERENCE OSCILLATOR 3 CONTROL REGISTER

Address: 0x44000AE0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
RODIV	30:16	Reference Clock Divider bits `0` REFO3 clock is same frequency as Base clock (no divider) `1` REFO3 clock is Base clock frequency divided by 2 (12) `2` REFO3 clock is Base clock frequency divided by 4 (22) `32767` REFO3 clock is Base clock frequency divided by 65,534 (32,767 *2)
ON	15	Output Enable bit `0` Reference Oscillator Module disabled `1` Reference Oscillator Module enabled
FRZ	14	Freeze in Debug mode bit `0` When emulator is in Debug mode, module continues operation `1` When emulator is in Debug mode, module freezes operation
SIDL	13	Peripheral Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
OE	12	Reference Clock Output Enable bit `0` Reference clock is not driven out on REFO3 pin. `1` Reference clock is driven out on REFO3 pin
RSLP	11	Reference Oscillator Run in Sleep bit `0` Reference Oscillator output is disabled in Sleep `1` Reference Oscillator output continues to run in Sleep
DIVSWEN	9	Clock RODIV/ROTRIM switch enabled. `0` Clock Divider Switch has completed. `1` Clock Divider Switching currently in progress.
ACTIVE	8	Reference Clock Request Status bit `0` Reference clock request is not active (User can update this REFOCON register) `1` Reference clock request is active (User should not update this REFOCON register)
ROSEL	3:0	Reference Clock Source Select bits `0` FRC `1` System PLL1 (Clock-1) `2` POSC `3` SOSC `4` LPRC `5` Ethernet PLL2 (Clock-2) `6` USB PLL `7` System PLL3 (Clock-3) `8` Ethernet PLL1 (Clock-1) `9` Peripheral clock 1 (reference clock reflects any peripheral clock switching) `10` System clock (reference clock reflects any device clock switching) `11` REFI Pin

REFO3CONCLR

Address: 0x44000AE4
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO3CONSET

Address: 0x44000AE8
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO3CONINV

Address: 0x44000AEC
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO3TRIMREFERENCE OSCILLATOR 3 TRIM REGISTER

Address: 0x44000AF0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ROTRIM	31:23	Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock `0` 0/512 (0.0) divisor added to RODIV value `1` 1/512 (0.001953125) divisor added to RODIV value `2` 2/512 (0.00390625) divisor added to RODIV value `256` 256/512 (0.5000) divisor added to RODIV value `511` 511/512 (0.998046875) divisor added to RODIV value

REFO3TRIMCLR

Address: 0x44000AF4
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO3TRIMSET

Address: 0x44000AF8
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO3TRIMINV

Address: 0x44000AFC
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO4CONREFERENCE OSCILLATOR 4 CONTROL REGISTER

Address: 0x44000B00
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
RODIV	30:16	Reference Clock Divider bits `0` REFO4 clock is same frequency as Base clock (no divider) `1` REFO4 clock is Base clock frequency divided by 2 (12) `2` REFO4 clock is Base clock frequency divided by 4 (22) `32767` REFO4 clock is Base clock frequency divided by 65,534 (32,767 *2)
ON	15	Output Enable bit `0` Reference Oscillator Module disabled `1` Reference Oscillator Module enabled
FRZ	14	Freeze in Debug mode bit `0` When emulator is in Debug mode, module continues operation `1` When emulator is in Debug mode, module freezes operation
SIDL	13	Peripheral Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
OE	12	Reference Clock Output Enable bit `0` Reference clock is not driven out on REFO4 pin. `1` Reference clock is driven out on REFO4 pin
RSLP	11	Reference Oscillator Run in Sleep bit `0` Reference Oscillator output is disabled in Sleep `1` Reference Oscillator output continues to run in Sleep
DIVSWEN	9	Clock RODIV/ROTRIM switch enabled. `0` Clock Divider Switch has completed. `1` Clock Divider Switching currently in progress.
ACTIVE	8	Reference Clock Request Status bit `0` Reference clock request is not active (User can update this REFOCON register) `1` Reference clock request is active (User should not update this REFOCON register)
ROSEL	3:0	Reference Clock Source Select bits `0` FRC `1` System PLL1 (Clock-1) `2` POSC `3` SOSC `4` LPRC `5` Ethernet PLL2 (Clock-2) `6` USB PLL `7` System PLL3 (Clock-3) `8` Ethernet PLL1 (Clock-1) `9` Peripheral clock 1 (reference clock reflects any peripheral clock switching) `10` System clock (reference clock reflects any device clock switching) `11` REFI Pin

REFO4CONCLR

Address: 0x44000B04
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO4CONSET

Address: 0x44000B08
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO4CONINV

Address: 0x44000B0C
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO4TRIMREFERENCE OSCILLATOR 4 TRIM REGISTER

Address: 0x44000B10
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ROTRIM	31:23	Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock `0` 0/512 (0.0) divisor added to RODIV value `1` 1/512 (0.001953125) divisor added to RODIV value `2` 2/512 (0.00390625) divisor added to RODIV value `256` 256/512 (0.5000) divisor added to RODIV value `511` 511/512 (0.998046875) divisor added to RODIV value

REFO4TRIMCLR

Address: 0x44000B14
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO4TRIMSET

Address: 0x44000B18
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO4TRIMINV

Address: 0x44000B1C
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO5CONREFERENCE OSCILLATOR 5 CONTROL REGISTER

Address: 0x44000B20
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
RODIV	30:16	Reference Clock Divider bits `0` REFO5 clock is same frequency as Base clock (no divider) `1` REFO5 clock is Base clock frequency divided by 2 (12) `2` REFO5 clock is Base clock frequency divided by 4 (22) `32767` REFO5 clock is Base clock frequency divided by 65,534 (32,767 *2)
ON	15	Output Enable bit `0` Reference Oscillator Module disabled `1` Reference Oscillator Module enabled
FRZ	14	Freeze in Debug mode bit `0` When emulator is in Debug mode, module continues operation `1` When emulator is in Debug mode, module freezes operation
SIDL	13	Peripheral Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
OE	12	Reference Clock Output Enable bit `0` Reference clock is not driven out on REFO5 pin. `1` Reference clock is driven out on REFO5 pin
RSLP	11	Reference Oscillator Run in Sleep bit `0` Reference Oscillator output is disabled in Sleep `1` Reference Oscillator output continues to run in Sleep
DIVSWEN	9	Clock RODIV/ROTRIM switch enabled. `0` Clock Divider Switch has completed. `1` Clock Divider Switching currently in progress.
ACTIVE	8	Reference Clock Request Status bit `0` Reference clock request is not active (User can update this REFOCON register) `1` Reference clock request is active (User should not update this REFOCON register)
ROSEL	3:0	Reference Clock Source Select bits `0` FRC `1` System PLL1 (Clock-1) `2` POSC `3` SOSC `4` LPRC `5` Ethernet PLL2 (Clock-2) `6` USB PLL `7` System PLL3 (Clock-3) `8` Ethernet PLL1 (Clock-1) `9` Peripheral clock 1 (reference clock reflects any peripheral clock switching) `10` System clock (reference clock reflects any device clock switching) `11` REFI Pin

REFO5CONCLR

Address: 0x44000B24
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO5CONSET

Address: 0x44000B28
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO5CONINV

Address: 0x44000B2C
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO5TRIMREFERENCE OSCILLATOR 5 TRIM REGISTER

Address: 0x44000B30
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ROTRIM	31:23	Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock `0` 0/512 (0.0) divisor added to RODIV value `1` 1/512 (0.001953125) divisor added to RODIV value `2` 2/512 (0.00390625) divisor added to RODIV value `256` 256/512 (0.5000) divisor added to RODIV value `511` 511/512 (0.998046875) divisor added to RODIV value

REFO5TRIMCLR

Address: 0x44000B34
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO5TRIMSET

Address: 0x44000B38
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO5TRIMINV

Address: 0x44000B3C
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO6CONREFERENCE OSCILLATOR 6 CONTROL REGISTER

Address: 0x44000B40
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
RODIV	30:16	Reference Clock Divider bits `0` REFO6 clock is same frequency as Base clock (no divider) `1` REFO6 clock is Base clock frequency divided by 2 (12) `2` REFO6 clock is Base clock frequency divided by 4 (22) `32767` REFO6 clock is Base clock frequency divided by 65,534 (32,767 *2)
ON	15	Output Enable bit `0` Reference Oscillator Module disabled `1` Reference Oscillator Module enabled
FRZ	14	Freeze in Debug mode bit `0` When emulator is in Debug mode, module continues operation `1` When emulator is in Debug mode, module freezes operation
SIDL	13	Peripheral Stop in Idle Mode bit `0` Continue module operation in Idle mode `1` Discontinue module operation when device enters Idle mode
OE	12	Reference Clock Output Enable bit `0` Reference clock is not driven out on REFO6 pin. `1` Reference clock is driven out on REFO6 pin
RSLP	11	Reference Oscillator Run in Sleep bit `0` Reference Oscillator output is disabled in Sleep `1` Reference Oscillator output continues to run in Sleep
DIVSWEN	9	Clock RODIV/ROTRIM switch enabled. `0` Clock Divider Switch has completed. `1` Clock Divider Switching currently in progress.
ACTIVE	8	Reference Clock Request Status bit `0` Reference clock request is not active (User can update this REFOCON register) `1` Reference clock request is active (User should not update this REFOCON register)
ROSEL	3:0	Reference Clock Source Select bits `0` FRC `1` System PLL1 (Clock-1) `2` POSC `3` SOSC `4` LPRC `5` Ethernet PLL2 (Clock-2) `6` USB PLL `7` System PLL3 (Clock-3) `8` Ethernet PLL1 (Clock-1) `9` Peripheral clock 1 (reference clock reflects any peripheral clock switching) `10` System clock (reference clock reflects any device clock switching) `11` REFI Pin

REFO6CONCLR

Address: 0x44000B44
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO6CONSET

Address: 0x44000B48
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO6CONINV

Address: 0x44000B4C
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO6TRIMREFERENCE OSCILLATOR 6 TRIM REGISTER

Address: 0x44000B50
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ROTRIM	31:23	Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock `0` 0/512 (0.0) divisor added to RODIV value `1` 1/512 (0.001953125) divisor added to RODIV value `2` 2/512 (0.00390625) divisor added to RODIV value `256` 256/512 (0.5000) divisor added to RODIV value `511` 511/512 (0.998046875) divisor added to RODIV value

REFO6TRIMCLR

Address: 0x44000B54
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO6TRIMSET

Address: 0x44000B58
Reset: 0x00000000
Access: read/write
Size: 32-bit

REFO6TRIMINV

Address: 0x44000B5C
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB1DIVPB1 CLOCK DIVISOR CONTROL REGISTER

Address: 0x44000B60
Reset: 0x00008801
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PBDIVON	15	Output Enable bit `0` PB1 Output clock is disabled `1` PB1 Output clock is enabled
PBDIVRDY	11	PB1 Peripheral Clock Divisor Ready `0` Indicates the PB clock divisor logic is currently switching values and the PB1DIV cannot be written. `1` Indicates the PB clock divisor logic is not switching divisors and the PB1DIV may be written.
PBDIV	6:0	PB1 Peripheral Clock Divisor Control value `0` Divide by 1 PB1 Clock same frequency as sys_clk `1` Divide by 2 PB1 Clock is 1/2 of sys_clk `2` Divide by 3 PB1 Clock is 1/3 of sys_clk `15` Divide by 16 PB1 Clock is 1/16 of sys_clk `16` Divide by 17 PB1 Clock is 1/17 of sys_clk `126` Divide by 127 PB1 Clock is 1/127 of sys_clk `127` Divide by 128 PB1 Clock is 1/128 of sys_clk

PB1DIVCLR

Address: 0x44000B64
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB1DIVSET

Address: 0x44000B68
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB1DIVINV

Address: 0x44000B6C
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB2DIVPB2 CLOCK DIVISOR CONTROL REGISTER

Address: 0x44000B70
Reset: 0x00008801
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PBDIVON	15	Output Enable bit `0` PB2 Output clock is disabled `1` PB2 Output clock is enabled
PBDIVRDY	11	PB2 Peripheral Clock Divisor Ready `0` Indicates the PB clock divisor logic is currently switching values and the PB2DIV cannot be written. `1` Indicates the PB clock divisor logic is not switching divisors and the PB2DIV may be written.
PBDIV	6:0	PB2 Peripheral Clock Divisor Control value `0` Divide by 1 PB2 Clock same frequency as sys_clk `1` Divide by 2 PB2 Clock is 1/2 of sys_clk `2` Divide by 3 PB2 Clock is 1/3 of sys_clk `15` Divide by 16 PB2 Clock is 1/16 of sys_clk `16` Divide by 17 PB2 Clock is 1/17 of sys_clk `126` Divide by 127 PB2 Clock is 1/127 of sys_clk `127` Divide by 128 PB2 Clock is 1/128 of sys_clk

PB2DIVCLR

Address: 0x44000B74
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB2DIVSET

Address: 0x44000B78
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB2DIVINV

Address: 0x44000B7C
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB3DIVPB3 CLOCK DIVISOR CONTROL REGISTER

Address: 0x44000B80
Reset: 0x00008813
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PBDIVON	15	Output Enable bit `0` PB3 Output clock is disabled `1` PB3 Output clock is enabled
PBDIVRDY	11	PB3 Peripheral Clock Divisor Ready `0` Indicates the PB clock divisor logic is currently switching values and the PB3DIV cannot be written. `1` Indicates the PB clock divisor logic is not switching divisors and the PB3DIV may be written.
PBDIV	6:0	PB3 Peripheral Clock Divisor Control value `0` Divide by 1 PB3 Clock same frequency as sys_clk `1` Divide by 2 PB3 Clock is 1/2 of sys_clk `2` Divide by 3 PB3 Clock is 1/3 of sys_clk `15` Divide by 16 PB3 Clock is 1/16 of sys_clk `16` Divide by 17 PB3 Clock is 1/17 of sys_clk `126` Divide by 127 PB3 Clock is 1/127 of sys_clk `127` Divide by 128 PB3 Clock is 1/128 of sys_clk

PB3DIVCLR

Address: 0x44000B84
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB3DIVSET

Address: 0x44000B88
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB3DIVINV

Address: 0x44000B8C
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB4DIVPB4 CLOCK DIVISOR CONTROL REGISTER

Address: 0x44000B90
Reset: 0x00008801
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PBDIVON	15	Output Enable bit `0` PB4 Output clock is disabled `1` PB4 Output clock is enabled
PBDIVRDY	11	PB4 Peripheral Clock Divisor Ready `0` Indicates the PB clock divisor logic is currently switching values and the PB4DIV cannot be written. `1` Indicates the PB clock divisor logic is not switching divisors and the PB4DIV may be written.
PBDIV	6:0	PB4 Peripheral Clock Divisor Control value `0` Divide by 1 PB4 Clock same frequency as sys_clk `1` Divide by 2 PB4 Clock is 1/2 of sys_clk `2` Divide by 3 PB4 Clock is 1/3 of sys_clk `15` Divide by 16 PB4 Clock is 1/16 of sys_clk `16` Divide by 17 PB4 Clock is 1/17 of sys_clk `126` Divide by 127 PB4 Clock is 1/127 of sys_clk `127` Divide by 128 PB4 Clock is 1/128 of sys_clk

PB4DIVCLR

Address: 0x44000B94
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB4DIVSET

Address: 0x44000B98
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB4DIVINV

Address: 0x44000B9C
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB5DIVPB5 CLOCK DIVISOR CONTROL REGISTER

Address: 0x44000BA0
Reset: 0x00008801
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PBDIVON	15	Output Enable bit `0` PB5 Output clock is disabled `1` PB5 Output clock is enabled
PBDIVRDY	11	PB5 Peripheral Clock Divisor Ready `0` Indicates the PB clock divisor logic is currently switching values and the PB5DIV cannot be written. `1` Indicates the PB clock divisor logic is not switching divisors and the PB5DIV may be written.
PBDIV	6:0	PB5 Peripheral Clock Divisor Control value `0` Divide by 1 PB5 Clock same frequency as sys_clk `1` Divide by 2 PB5 Clock is 1/2 of sys_clk `2` Divide by 3 PB5 Clock is 1/3 of sys_clk `15` Divide by 16 PB5 Clock is 1/16 of sys_clk `16` Divide by 17 PB5 Clock is 1/17 of sys_clk `126` Divide by 127 PB5 Clock is 1/127 of sys_clk `127` Divide by 128 PB5 Clock is 1/128 of sys_clk

PB5DIVCLR

Address: 0x44000BA4
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB5DIVSET

Address: 0x44000BA8
Reset: 0x00000000
Access: read/write
Size: 32-bit

PB5DIVINV

Address: 0x44000BAC
Reset: 0x00000000
Access: read/write
Size: 32-bit

SLEWCONSLEW RATE CONTROL FOR CLOCK SWITCHING REGISTER

Address: 0x44000BB0
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
SLWDLY	27:24	Number of clocks generated at each slew step for a clock switch `0` 1 clock will be generated at each slew step `1` 2 clocks will be generated at each slew step `2` 3 clocks will be generated at each slew step `3` 4 clocks will be generated at each slew step `4` 5 clocks will be generated at each slew step `5` 6 clocks will be generated at each slew step `6` 7 clocks will be generated at each slew step `7` 8 clocks will be generated at each slew step `8` 9 clocks will be generated at each slew step `9` 10 clocks will be generated at each slew step `10` 11 clocks will be generated at each slew step `11` 12 clocks will be generated at each slew step `12` 13 clocks will be generated at each slew step `13` 14 clocks will be generated at each slew step `14` 15 clocks will be generated at each slew step `15` 16 clocks will be generated at each slew step
SYSDIV	19:16	PBx Peripheral Clock Divisor Control value `0` Divide by 1- sys_clk_out same frequency as sys_clk source - Default `1` Divide by 2- sys_clk_out is 1/2 of sys_clk source `2` Divide by 3- sys_clk_out is 1/3 of sys_clk source `3` Divide by 4- sys_clk_out is 1/4 of sys_clk source `4` Divide by 5- sys_clk_out is 1/5 of sys_clk source `5` Divide by 6- sys_clk_out is 1/6 of sys_clk source `6` Divide by 7- sys_clk_out is 1/7 of sys_clk source `7` Divide by 8- sys_clk_out is 1/8 of sys_clk source `8` Divide by 9- sys_clk_out is 1/9 of sys_clk source `9` Divide by 10- sys_clk_out is 1/10 of sys_clk source `10` Divide by 11- sys_clk_out is 1/11 of sys_clk source `11` Divide by 12- sys_clk_out is 1/12 of sys_clk source `12` Divide by 13- sys_clk_out is 1/13 of sys_clk source `13` Divide by 14- sys_clk_out is 1/14 of sys_clk source `14` Divide by 15- sys_clk_out is 1/15 of sys_clk source `15` Divide by 16- sys_clk_out is 1/16 of sys_clk source
SLWDIV	10:8	Divisor steps used when doing slewed clock switches `0` No Divisor used `1` Divide by 2, then no divisor `2` Divide by 4, then by 2, then no divisor `3` Divide by 8, then by 4, then by 2, then no divisor `4` Divide by 16, then by 8, then by 4, then by 2, then no divisor `5` Divide by 32, then by 16, then by 8, then by 4, then by 2, then no divisor `6` Divide by 64, then by 32, then by 16, then by 8, then by 4, then by 2, then no divisor `7` Divide by 128, then by 64, then by 32, then by 16, then by 8, then by 4, then by 2, then no divisor
UPEN	2	Clock slew enable for switching up to faster clocks `0` Clock Slewing disabled `1` Clock Slewing enabled on a clock switch OR exit from SLEEP
DNEN	1	Clock slew enable for switching down to slower clocks `0` Clock Slewing disabled `1` Clock Slewing enabled on a clock switch
BUSY	0	Clock Switch Slewing Active Status Bit - Read-Only `0` Clock Switch has reached its final value `1` Clock frequency is being actively Slewed

SLEWCONCLR

Address: 0x44000BB4
Reset: 0x00000000
Access: read/write
Size: 32-bit

SLEWCONSET

Address: 0x44000BB8
Reset: 0x00000000
Access: read/write
Size: 32-bit

SLEWCONINV

Address: 0x44000BBC
Reset: 0x00000000
Access: read/write
Size: 32-bit

CLKSTATCLOCK STATUS REGISTER

Address: 0x44000BC0
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
PB1RDY	10	PB1 Clock Ready Status value `0` PB1 clock is not stable and not ready `1` PB1 clock is stable and ready
SYSRDY	9	System Clock Ready Status value `0` System clock is not stable and not ready `1` System clock is stable and ready
EPLL1RDY	8	Ethernet PLL1 Ready Status value `0` EPLL1 is not stable and not ready `1` EPLL1 is stable and ready
SPLLRDY	7	System PLL Ready Status value `0` SPLL is not stable and not ready `1` SPLL is stable and ready
UPLLRDY	6	USB PLL Ready Status value `0` UPLL is not stable and not ready `1` UPLL is stable and ready
EPLL2RDY	5	Ethernet PLL2 Ready Status value `0` EPLL2 is not stable and not ready `1` EPLL2 is stable and ready
LPRCRDY	4	LPRC Ready Status value `0` LPRC is not stable and not ready `1` LPRC is stable and ready
SOSCRDY	3	SOSC Ready Status value `0` SOSC is not stable and not ready `1` SOSC is stable and ready
POSCRDY	2	Primary Oscillator Ready Status value `0` POSC is not stable and not ready `1` POSC is stable and ready
SPLL1RDY	1	System PLL1 Ready Status value `0` SPLL1 Primary Output is not stable and not ready `1` SPLL1 Primary Output is stable and ready
FRCRDY	0	FRC Ready Status value `0` FRC is not stable and not ready `1` FRC is stable and ready

CLKSTATCLR

Address: 0x44000BC4
Reset: 0x00000000
Access: read/write
Size: 32-bit

CLKSTATSET

Address: 0x44000BC8
Reset: 0x00000000
Access: read/write
Size: 32-bit

CLKSTATINV

Address: 0x44000BCC
Reset: 0x00000000
Access: read/write
Size: 32-bit

CLKDIAGUSER CLK DIAGNOSTICS CONTROL REGISTER

Address: 0x44000BE0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
UPLLSTOP	6	UPLL Clock Stop Control value `0` UPLL clock source runs as normal `1` UPLL clock source is stopped
EPLLSTOP	5	EPLL Clock Stop Control value `0` EPLL clock source runs as normal `1` EPLL clock source is stopped
SPLL1STOP	4	SPLL1 Clock Stop Control value `0` SPLL1 clock source runs as normal `1` SPLL1 clock source is stopped
LPRCSTOP	3	LPRC Clock Stop Control value `0` LPRC clock source runs as normal `1` LPRC clock source is stopped
FRCSTOP	2	FRC Clock Stop Control value `0` FRC clock source runs as normal `1` FRC clock source is stopped
SOSCSTOP	1	SOSC Clock Stop Control value `0` SOSC clock source runs as normal `1` SOSC clock source is stopped
POSCSTOP	0	POSC Clock Stop Control value `0` POSC clock source runs as normal `1` POSC clock source is stopped
NMICNT	31:16	NMI Counter value

CLKDIAGCLR

Address: 0x44000BE4
Reset: 0x00000000
Access: read/write
Size: 32-bit

CLKDIAGSET

Address: 0x44000BE8
Reset: 0x00000000
Access: read/write
Size: 32-bit

CLKDIAGINV

Address: 0x44000BEC
Reset: 0x00000000
Access: read/write
Size: 32-bit