PIC32CX2051BZ66048 DMAC registers

The 143 registers of DMAC (Direct Memory Access Controller), from 0x41004000, with their reset value and every field. The PIC32CX2051BZ66048 has 3597 registers in 73 peripherals, one page each.

DMAC Direct Memory Access Controller

CTRLControl

Address: 0x41004000
Reset: 0x0000
Access: read/write
Size: 16-bit

7 fields

Field	Bits	What it does
LVLEN3	11	Priority Level 3 Enable
LVLEN2	10	Priority Level 2 Enable
LVLEN1	9	Priority Level 1 Enable
LVLEN0	8	Priority Level 0 Enable
CRCENABLE	2	CRC Enable
DMAENABLE	1	DMA Enable
SWRST	0	Software Reset

CRCCTRLCRC Control

Address: 0x41004002
Reset: 0x0000
Access: read/write
Size: 16-bit

4 fields

Field	Bits	What it does
CRCMODE	15:14	CRC Operating Mode `0` Default operating mode `2` Memory CRC monitor operating mode `3` Memory CRC generation operating mode
CRCSRC	13:8	CRC Input Source `0` CRC Disabled `1` I/O interface
CRCPOLY	3:2	CRC Polynomial Type `0` CRC-16 (CRC-CCITT) `1` CRC32 (IEEE 802.3)
CRCBEATSIZE	1:0	CRC Beat Size `0` 8-bit bus transfer `1` 16-bit bus transfer `2` 32-bit bus transfer

CRCDATAINCRC Data Input

Address: 0x41004004
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CRCDATAIN	31:0	CRC Data Input

CRCCHKSUMCRC Checksum

Address: 0x41004008
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CRCCHKSUM	31:0	CRC Checksum

CRCSTATUSCRC Status

Address: 0x4100400C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2CRCERR
1CRCZERO
0CRCBUSY

3 fields

Field	Bits	What it does
CRCERR	2	CRC Error
CRCZERO	1	CRC Zero
CRCBUSY	0	CRC Module Busy

DBGCTRLDebug Control

Address: 0x4100400D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1–
0DBGRUN

1 field

Field	Bits	What it does
DBGRUN	0	Debug Run

SWTRIGCTRLSoftware Trigger Control

Address: 0x41004010
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
SWTRIG15	15	Channel 15 Software Trigger
SWTRIG14	14	Channel 14 Software Trigger
SWTRIG13	13	Channel 13 Software Trigger
SWTRIG12	12	Channel 12 Software Trigger
SWTRIG11	11	Channel 11 Software Trigger
SWTRIG10	10	Channel 10 Software Trigger
SWTRIG9	9	Channel 9 Software Trigger
SWTRIG8	8	Channel 8 Software Trigger
SWTRIG7	7	Channel 7 Software Trigger
SWTRIG6	6	Channel 6 Software Trigger
SWTRIG5	5	Channel 5 Software Trigger
SWTRIG4	4	Channel 4 Software Trigger
SWTRIG3	3	Channel 3 Software Trigger
SWTRIG2	2	Channel 2 Software Trigger
SWTRIG1	1	Channel 1 Software Trigger
SWTRIG0	0	Channel 0 Software Trigger

PRICTRL0Priority Control 0

Address: 0x41004014
Reset: 0x40404040
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
QOS3	30:29	Level 3 Quality of Service `0` Regular delivery `1` Bandwidth shortage `2` Latency sensitive `3` Latency critical
LVLPRI3	28:24	Level 3 Channel Priority Number
RRLVLEN2	23	Level 2 Round-Robin Scheduling Enable
QOS2	22:21	Level 2 Quality of Service `0` Regular delivery `1` Bandwidth shortage `2` Latency sensitive `3` Latency critical
LVLPRI2	20:16	Level 2 Channel Priority Number
RRLVLEN1	15	Level 1 Round-Robin Scheduling Enable
QOS1	14:13	Level 1 Quality of Service `0` Regular delivery `1` Bandwidth shortage `2` Latency sensitive `3` Latency critical
LVLPRI1	12:8	Level 1 Channel Priority Number
RRLVLEN0	7	Level 0 Round-Robin Scheduling Enable
QOS0	6:5	Level 0 Quality of Service `0` Regular delivery `1` Bandwidth shortage `2` Latency sensitive `3` Latency critical
LVLPRI0	4:0	Level 0 Channel Priority Number
RRLVLEN3	31	Level 3 Round-Robin Scheduling Enable

INTPENDInterrupt Pending

Address: 0x41004020
Reset: 0x0000
Access: read/write
Size: 16-bit

8 fields

Field	Bits	What it does
PEND	15	Pending
BUSY	14	Busy
FERR	13	Fetch Error
CRCERR	12	CRC Error
SUSP	10	Channel Suspend
TCMPL	9	Transfer Complete
TERR	8	Transfer Error
ID	4:0	Channel ID

INTSTATUSInterrupt Status

Address: 0x41004024
Reset: 0x00000000
Access: read only
Size: 32-bit

16 fields

Field	Bits	What it does
CHINT15	15	Channel 15 Pending Interrupt
CHINT14	14	Channel 14 Pending Interrupt
CHINT13	13	Channel 13 Pending Interrupt
CHINT12	12	Channel 12 Pending Interrupt
CHINT11	11	Channel 11 Pending Interrupt
CHINT10	10	Channel 10 Pending Interrupt
CHINT9	9	Channel 9 Pending Interrupt
CHINT8	8	Channel 8 Pending Interrupt
CHINT7	7	Channel 7 Pending Interrupt
CHINT6	6	Channel 6 Pending Interrupt
CHINT5	5	Channel 5 Pending Interrupt
CHINT4	4	Channel 4 Pending Interrupt
CHINT3	3	Channel 3 Pending Interrupt
CHINT2	2	Channel 2 Pending Interrupt
CHINT1	1	Channel 1 Pending Interrupt
CHINT0	0	Channel 0 Pending Interrupt

BUSYCHBusy Channels

Address: 0x41004028
Reset: 0x00000000
Access: read only
Size: 32-bit

16 fields

Field	Bits	What it does
BUSYCH15	15	Busy Channel 15
BUSYCH14	14	Busy Channel 14
BUSYCH13	13	Busy Channel 13
BUSYCH12	12	Busy Channel 12
BUSYCH11	11	Busy Channel 11
BUSYCH10	10	Busy Channel 10
BUSYCH9	9	Busy Channel 9
BUSYCH8	8	Busy Channel 8
BUSYCH7	7	Busy Channel 7
BUSYCH6	6	Busy Channel 6
BUSYCH5	5	Busy Channel 5
BUSYCH4	4	Busy Channel 4
BUSYCH3	3	Busy Channel 3
BUSYCH2	2	Busy Channel 2
BUSYCH1	1	Busy Channel 1
BUSYCH0	0	Busy Channel 0

PENDCHPending Channels

Address: 0x4100402C
Reset: 0x00000000
Access: read only
Size: 32-bit

16 fields

Field	Bits	What it does
PENDCH15	15	Pending Channel 15
PENDCH14	14	Pending Channel 14
PENDCH13	13	Pending Channel 13
PENDCH12	12	Pending Channel 12
PENDCH11	11	Pending Channel 11
PENDCH10	10	Pending Channel 10
PENDCH9	9	Pending Channel 9
PENDCH8	8	Pending Channel 8
PENDCH7	7	Pending Channel 7
PENDCH6	6	Pending Channel 6
PENDCH5	5	Pending Channel 5
PENDCH4	4	Pending Channel 4
PENDCH3	3	Pending Channel 3
PENDCH2	2	Pending Channel 2
PENDCH1	1	Pending Channel 1
PENDCH0	0	Pending Channel 0

ACTIVEActive Channel and Levels

Address: 0x41004030
Reset: 0x00000000
Access: read only
Size: 32-bit

7 fields

Field	Bits	What it does
ABUSY	15	Active Channel Busy
ID	12:8	Active Channel ID
LVLEX3	3	Level 3 Channel Trigger Request Executing
LVLEX2	2	Level 2 Channel Trigger Request Executing
LVLEX1	1	Level 1 Channel Trigger Request Executing
LVLEX0	0	Level 0 Channel Trigger Request Executing
BTCNT	31:16	Active Channel Block Transfer Count

BASEADDRDescriptor Memory Section Base Address

Address: 0x41004034
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
BASEADDR	31:0	Descriptor Memory Base Address

WRBADDRWrite-Back Memory Section Base Address

Address: 0x41004038
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
WRBADDR	31:0	Write-Back Memory Base Address

CHANNEL0.CHCTRLAChannel n Control A

Address: 0x41004040
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL0.CHCTRLBChannel n Control B

Address: 0x41004044
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL0.CHPRILVLChannel n Priority Level

Address: 0x41004045
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL0.CHEVCTRLChannel n Event Control

Address: 0x41004046
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL0.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100404C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL0.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100404D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL0.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100404E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL0.CHSTATUSChannel n Status

Address: 0x4100404F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL1.CHCTRLAChannel n Control A

Address: 0x41004050
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL1.CHCTRLBChannel n Control B

Address: 0x41004054
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL1.CHPRILVLChannel n Priority Level

Address: 0x41004055
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL1.CHEVCTRLChannel n Event Control

Address: 0x41004056
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL1.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100405C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL1.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100405D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL1.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100405E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL1.CHSTATUSChannel n Status

Address: 0x4100405F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL2.CHCTRLAChannel n Control A

Address: 0x41004060
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL2.CHCTRLBChannel n Control B

Address: 0x41004064
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL2.CHPRILVLChannel n Priority Level

Address: 0x41004065
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL2.CHEVCTRLChannel n Event Control

Address: 0x41004066
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL2.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100406C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL2.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100406D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL2.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100406E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL2.CHSTATUSChannel n Status

Address: 0x4100406F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL3.CHCTRLAChannel n Control A

Address: 0x41004070
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL3.CHCTRLBChannel n Control B

Address: 0x41004074
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL3.CHPRILVLChannel n Priority Level

Address: 0x41004075
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL3.CHEVCTRLChannel n Event Control

Address: 0x41004076
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL3.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100407C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL3.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100407D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL3.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100407E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL3.CHSTATUSChannel n Status

Address: 0x4100407F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL4.CHCTRLAChannel n Control A

Address: 0x41004080
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL4.CHCTRLBChannel n Control B

Address: 0x41004084
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL4.CHPRILVLChannel n Priority Level

Address: 0x41004085
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL4.CHEVCTRLChannel n Event Control

Address: 0x41004086
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL4.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100408C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL4.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100408D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL4.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100408E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL4.CHSTATUSChannel n Status

Address: 0x4100408F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL5.CHCTRLAChannel n Control A

Address: 0x41004090
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL5.CHCTRLBChannel n Control B

Address: 0x41004094
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL5.CHPRILVLChannel n Priority Level

Address: 0x41004095
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL5.CHEVCTRLChannel n Event Control

Address: 0x41004096
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL5.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100409C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL5.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100409D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL5.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100409E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL5.CHSTATUSChannel n Status

Address: 0x4100409F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL6.CHCTRLAChannel n Control A

Address: 0x410040A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL6.CHCTRLBChannel n Control B

Address: 0x410040A4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL6.CHPRILVLChannel n Priority Level

Address: 0x410040A5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL6.CHEVCTRLChannel n Event Control

Address: 0x410040A6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL6.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x410040AC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL6.CHINTENSETChannel n Interrupt Enable Set

Address: 0x410040AD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL6.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x410040AE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL6.CHSTATUSChannel n Status

Address: 0x410040AF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL7.CHCTRLAChannel n Control A

Address: 0x410040B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL7.CHCTRLBChannel n Control B

Address: 0x410040B4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL7.CHPRILVLChannel n Priority Level

Address: 0x410040B5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL7.CHEVCTRLChannel n Event Control

Address: 0x410040B6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL7.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x410040BC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL7.CHINTENSETChannel n Interrupt Enable Set

Address: 0x410040BD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL7.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x410040BE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL7.CHSTATUSChannel n Status

Address: 0x410040BF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL8.CHCTRLAChannel n Control A

Address: 0x410040C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL8.CHCTRLBChannel n Control B

Address: 0x410040C4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL8.CHPRILVLChannel n Priority Level

Address: 0x410040C5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL8.CHEVCTRLChannel n Event Control

Address: 0x410040C6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL8.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x410040CC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL8.CHINTENSETChannel n Interrupt Enable Set

Address: 0x410040CD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL8.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x410040CE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL8.CHSTATUSChannel n Status

Address: 0x410040CF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL9.CHCTRLAChannel n Control A

Address: 0x410040D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL9.CHCTRLBChannel n Control B

Address: 0x410040D4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL9.CHPRILVLChannel n Priority Level

Address: 0x410040D5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL9.CHEVCTRLChannel n Event Control

Address: 0x410040D6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL9.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x410040DC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL9.CHINTENSETChannel n Interrupt Enable Set

Address: 0x410040DD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL9.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x410040DE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL9.CHSTATUSChannel n Status

Address: 0x410040DF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL10.CHCTRLAChannel n Control A

Address: 0x410040E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL10.CHCTRLBChannel n Control B

Address: 0x410040E4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL10.CHPRILVLChannel n Priority Level

Address: 0x410040E5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL10.CHEVCTRLChannel n Event Control

Address: 0x410040E6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL10.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x410040EC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL10.CHINTENSETChannel n Interrupt Enable Set

Address: 0x410040ED
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL10.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x410040EE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL10.CHSTATUSChannel n Status

Address: 0x410040EF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL11.CHCTRLAChannel n Control A

Address: 0x410040F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL11.CHCTRLBChannel n Control B

Address: 0x410040F4
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL11.CHPRILVLChannel n Priority Level

Address: 0x410040F5
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL11.CHEVCTRLChannel n Event Control

Address: 0x410040F6
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL11.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x410040FC
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL11.CHINTENSETChannel n Interrupt Enable Set

Address: 0x410040FD
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL11.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x410040FE
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL11.CHSTATUSChannel n Status

Address: 0x410040FF
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL12.CHCTRLAChannel n Control A

Address: 0x41004100
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL12.CHCTRLBChannel n Control B

Address: 0x41004104
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL12.CHPRILVLChannel n Priority Level

Address: 0x41004105
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL12.CHEVCTRLChannel n Event Control

Address: 0x41004106
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL12.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100410C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL12.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100410D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL12.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100410E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL12.CHSTATUSChannel n Status

Address: 0x4100410F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL13.CHCTRLAChannel n Control A

Address: 0x41004110
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL13.CHCTRLBChannel n Control B

Address: 0x41004114
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL13.CHPRILVLChannel n Priority Level

Address: 0x41004115
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL13.CHEVCTRLChannel n Event Control

Address: 0x41004116
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL13.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100411C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL13.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100411D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL13.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100411E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL13.CHSTATUSChannel n Status

Address: 0x4100411F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL14.CHCTRLAChannel n Control A

Address: 0x41004120
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL14.CHCTRLBChannel n Control B

Address: 0x41004124
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL14.CHPRILVLChannel n Priority Level

Address: 0x41004125
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL14.CHEVCTRLChannel n Event Control

Address: 0x41004126
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL14.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100412C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL14.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100412D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL14.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100412E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL14.CHSTATUSChannel n Status

Address: 0x4100412F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending

CHANNEL15.CHCTRLAChannel n Control A

Address: 0x41004130
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
THRESHOLD	29:28	FIFO Threshold `0` Destination write starts after each beat source address read `1` Destination write starts after 2-beats source address read `2` Destination write starts after 4-beats source address read `3` Destination write starts after 8-beats source address read
BURSTLEN	27:24	Burst Length `0` Single-beat burst length `1` 2-beats burst length `2` 3-beats burst length `3` 4-beats burst length `4` 5-beats burst length `5` 6-beats burst length `6` 7-beats burst length `7` 8-beats burst length `8` 9-beats burst length `9` 10-beats burst length `10` 11-beats burst length `11` 12-beats burst length `12` 13-beats burst length `13` 14-beats burst length `14` 15-beats burst length `15` 16-beats burst length
TRIGACT	21:20	Trigger Action `0` One trigger required for each block transfer `2` One trigger required for each burst transfer `3` One trigger required for each transaction
TRIGSRC	15:8	Trigger Source `0` Only software/event triggers `1` Trigger source is RTC `2` Trigger source is DSU DCC0 `3` Trigger source is DSU DCC1 `4` Trigger source is SERCOM0 RX `5` Trigger source is SERCOM0 TX `6` Trigger source is SERCOM1 RX `7` Trigger source is SERCOM1 TX `8` Trigger source is SERCOM2 RX `9` Trigger source is SERCOM2 TX `10` Trigger source is SERCOM3 RX `11` Trigger source is SERCOM3 TX `16` Trigger source is SERCOM6 RX `17` Trigger source is SERCOM6 TX `18` Trigger source is TCC0 OVF `19` Trigger source is TCC0 MC0 `20` Trigger source is TCC0 MC1 `21` Trigger source is TCC0 MC2 `22` Trigger source is TCC0 MC3 `23` Trigger source is TCC0 MC4 `24` Trigger source is TCC0 MC5 `25` Trigger source is TCC1 OVF `26` Trigger source is TCC1 MC0 `27` Trigger source is TCC1 MC1 `28` Trigger source is TCC1 MC2 `29` Trigger source is TCC1 MC3 `30` Trigger source is TCC1 MC4 `31` Trigger source is TCC1 MC5 `32` Trigger source is TCC2 OVF `33` Trigger source is TCC2 MC0 `34` Trigger source is TCC2 MC1 `35` Trigger source is TCO OVF `36` Trigger source is TC0 MC0 `37` Trigger source is TC0 MC1 `38` Trigger source is TC1 OVF `39` Trigger source is TC1 MC0 `40` Trigger source is TC1 MC1 `41` Trigger source is TC2 OVF `42` Trigger source is TC2 MC0 `43` Trigger source is TC2 MC1 `44` Trigger source is TC3 OVF `45` Trigger source is TC3 MC0 `46` Trigger source is TC3 MC1 `47` Trigger source is TC4 OVF `48` Trigger source is TC4 MC0 `49` Trigger source is TC4 MC1 `50` Trigger source is TC5 OVF `51` Trigger source is TC5 MC0 `52` Trigger source is TC5 MC1 `53` Trigger source is TC6 OVF `54` Trigger source is TC6 MC0 `55` Trigger source is TC6 MC1 `56` Trigger source is TC7 OVF `57` Trigger source is TC7 MC0 `58` Trigger source is TC7 MC1 `59` Trigger source is TC8 OVF `60` Trigger source is TC8 MC0 `61` Trigger source is TC8 MC1 `62` Trigger source is TC9 OVF `63` Trigger source is TC9 MC0 `64` Trigger source is TC9 MC1 `65` Trigger source is QSPI RX `66` Trigger source is QSPI TX
RUNSTDBY	6	Channel Run in Standby
ENABLE	1	Channel Enable
SWRST	0	Channel Software Reset

CHANNEL15.CHCTRLBChannel n Control B

Address: 0x41004134
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1CMD1
0CMD0

1 field

Field	Bits	What it does
CMD	1:0	Software Command `0` No action `1` Channel suspend operation `2` Channel resume operation

CHANNEL15.CHPRILVLChannel n Priority Level

Address: 0x41004135
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1PRILVL1
0PRILVL0

1 field

Field	Bits	What it does
PRILVL	1:0	Channel Priority Level `0` Channel Priority Level 0 (Lowest Level) `1` Channel Priority Level 1 `2` Channel Priority Level 2 `3` Channel Priority Level 3 (Highest Level)

CHANNEL15.CHEVCTRLChannel n Event Control

Address: 0x41004136
Reset: 0x00
Access: read/write

7EVOE
6EVIE
5EVOMODE1
4EVOMODE0
3–
2EVACT2
1EVACT1
0EVACT0

4 fields

Field	Bits	What it does
EVOE	7	Channel Event Output Enable
EVIE	6	Channel Event Input Enable
EVOMODE	5:4	Channel Event Output Mode `0` Block event output selection. Refer to BTCTRL.EVOSEL for available selections. `1` Ongoing trigger action
EVACT	2:0	Channel Event Input Action `0` No action `1` Transfer and periodic transfer trigger `2` Conditional transfer trigger `3` Conditional block transfer `4` Channel suspend operation `5` Channel resume operation `6` Skip next block suspend action `7` Increase priority

CHANNEL15.CHINTENCLRChannel n Interrupt Enable Clear

Address: 0x4100413C
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL15.CHINTENSETChannel n Interrupt Enable Set

Address: 0x4100413D
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend Interrupt Enable
TCMPL	1	Channel Transfer Complete Interrupt Enable
TERR	0	Channel Transfer Error Interrupt Enable

CHANNEL15.CHINTFLAGChannel n Interrupt Flag Status and Clear

Address: 0x4100413E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SUSP
1TCMPL
0TERR

3 fields

Field	Bits	What it does
SUSP	2	Channel Suspend
TCMPL	1	Channel Transfer Complete
TERR	0	Channel Transfer Error

CHANNEL15.CHSTATUSChannel n Status

Address: 0x4100413F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3CRCERR
2FERR
1BUSY
0PEND

4 fields

Field	Bits	What it does
CRCERR	3	Channel CRC Error
FERR	2	Channel Fetch Error
BUSY	1	Channel Busy
PEND	0	Channel Pending