PIC32CX2051BZ66048 QEI registers The 52 registers of QEI, from 0x44005000, with their reset value and every field. The PIC32CX2051BZ66048 has 3597 registers in 73 peripherals, one page each.
QEI QEICONQEI Control Register
Address 0x44005000
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does ON 15 Quadrature Encoder Interface Module Counter Enable bit0 Module counters are disabled1 Module counters are enabled FRZ 14 Quadrature Encoder Interface Freeze debug mode QEISIDL 13 Stop in Idle Mode bit0 Continue module operation in Idle mode1 Discontinue module operation when device enters Idle mode PIMOD 12:10 Position Counter Initialization Mode Select bits0 Index input event does not affect position counter1 Every Index input event resets the position counter2 Next index input event initializes the position counter with contents of QEIICCH register3 First index event after home event initializes position counter with contents of QEIICCH register4 Second index event after home event initializes position counter with contents of QEIICCHregister5 Resets the position counter when the position counter equals QEIICCH register6 Modulo Count mode for position counter7 Modulo Count mode for position counter and every index event resets the position counter IMV 9:8 Index Match Value bits0 Index match occurs when QEB is 0 and QEA is 01 Index match occurs when QEB is 0 and QEA is 12 Index match occurs when QEB is 1 and QEA is 03 Index match occurs when QEB is 1 and QEA is 1 INTDIV 6:4 Timer Input Clock Prescale Select bits 0 1:1 prescale value1 1:2 prescale value2 1:4 prescale value3 1:8 prescale value4 1:16 prescale value5 1:32 prescale value6 1:64 prescale value7 1:128 prescale value CNTPOL 3 Position and Index Counter/Timer Direction Select bit0 Counter direction is positive unless modified by external Up/Down signal1 Counter direction is negative unless modified by external Up/Down signal GATEN 2 External Count Gate Enable bit0 External gate signal has no affect on position counter/timer operation1 External gate signal controls position counter operation CCM 1:0 Counter Control Mode Selection bits0 Quadrature Encoder Interface Count mode (x4 mode)1 External clock count with external Up/Dn direction selection2 External clock count with optional external count gating3 Internal timer mode with optional external count enable
QEICONCLRBit clear register
Address 0x44005004
Reset 0x00000000
Access read/write
Size 32-bit QEICONSETBit set register
Address 0x44005008
Reset 0x00000000
Access read/write
Size 32-bit QEICONINVBit invert register
Address 0x4400500C
Reset 0x00000000
Access read/write
Size 32-bit QEIIOCQEI I/O Control Register
Address 0x44005010
Reset 0x00000000
Access read/write
Size 32-bit 14 fields
Field Bits What it does HCAPEN 16 Position Counter Input Capture by Home Event Enable bit0 HOMEx input event (positive edge) does not trigger a position capture event1 HOMEx input event (positive edge) triggers a position capture event QCAPEN 15 Position Counter Input Capture Enable bit0 Home input event (positive edge) does not trigger a capture even1 Positive edge detect of Home input triggers position capture function FLTREN 14 QEA/QEB/INDX/HOMEx Digital Filter Enable bit0 Input Pin Digital filter is disabled (bypassed)1 Input Pin Digital filter is enabled QFDIV 13:11 QEA/QEB/INDX/HOMEx Digital Input Filter Clock Divide Select bits0 1:1 clock divide1 1:2 clock divide2 1:4 clock divide3 1:8 clock divide4 1:16 clock divide5 1:32 clock divide6 1:64 clock divide7 1:128 clock divide OUTFNC 10:9 QEI Module Output Function Mode Select bits0 Output is disabled1 The position counter greater than or equal to the range of ICCH and ICCL2 The position counter less than or equal to the range of CMPLH and CMPLL3 The position coutner is either case SWPAB 8 Swap QEA and QEB Inputs bit0 QEAx and QEBx are not swapped1 QEAx and QEBx are swapped prior to quadrature decoder logic HOMPOL 7 HOMEx Input Polarity Select bit0 Input is not inverted1 Input is inverted IDXPOL 6 INDXx Input Polarity Select bit0 Input is not inverted1 Input is inverted QEBPOL 5 QEBx Input Polarity Select bit0 Input is not inverted1 Input is inverted QEAPOL 4 QEAx Input Polarity Select bit0 Input is not inverted1 Input is inverted HOME 3 Status of HOMEx Input Pin after Polarity Control bit INDEX 2 Status of INDXx Input Pin after Polarity Control bit QEB 1 Status of QEBx Input Pin after Polarity Control and SWPAB Pin Swapping bit0 Status of QEB input pin after polarity control and SWPAB pin swapping1 Status of QEB input pin after polarity control and SWPAB pin swapping QEA 0 Status of QEAx Input Pin after Polarity Control and SWPAB Pin Swapping bit0 Status of QEA input pin after polarity control and SWPAB pin swapping1 Status of QEA input pin after polarity control and SWPAB pin swapping
QQEIIOCCLRBit clear register
Address 0x44005014
Reset 0x00000000
Access read/write
Size 32-bit QEIIOCSETBit set register
Address 0x44005018
Reset 0x00000000
Access read/write
Size 32-bit QEIIOCINVBit invert register
Address 0x4400501C
Reset 0x00000000
Access read/write
Size 32-bit QEISTATQEI Status Register
Address 0x44005020
Reset 0x00000000
Access read/write
Size 32-bit 14 fields
Field Bits What it does PCHEQIRQ 13 Position Counter Greater Than or Equal Compare Status bit0 POSxCNT less than QEIICCH1 POSxCNT greater than or equal to QEIICCH PCHEQIEN 12 Position Counter Greater Than or Equal Compare Interrupt Enable bit0 Interrupt is disabled1 Interrupt is enabled PCLEQIRQ 11 Position Counter Less Than or Equal Compare Status bit0 POSxCNT greater than QEICMPL1 POSxCNT less than or equal to QEICMPL PCLEQIEN 10 Position Counter Less Than or Equal Compare Interrupt Enable bit0 Interrupt is disabled1 Interrupt is enabled POSOVIRQ 9 Position Counter Overflow Status bit0 No overflow has occurred1 Overflow has occurred POSOVIEN 8 Position Counter Overflow Interrupt Enable bit0 Interrupt is disabled1 Interrupt is enabled PCIIRQ 7 Position Counter Initialization Process Complete Status bit0 POSxCNT was not reinitialized1 POSxCNT was reinitialized PCIIEN 6 Position Counter Initialization Process Complete Interrupt Enable bit0 Interrupt is disabled1 Interrupt is enabled VELOVIRQ 5 Velocity Counter Overflow Status bit0 No overflow has not occurred1 Overflow has occurred VELOVIEN 4 Velocity Counter Overflow Interrupt Enable bit0 Interrupt is disabled1 Interrupt is enabled HOMIRQ 3 Status Flag for Home Event Status bit0 No Home event has occurred1 Home event has occurred HOMIEN 2 Home Input Event Interrupt Enable bit0 Interrupt is disabled1 Interrupt is enabled IDXIRQ 1 Status Flag for Index Event Status bit0 No Index event has occurred1 Index event has occurred IDXIEN 0 Index Input Event Interrupt Enable bit0 Interrupt is disabled1 Interrupt is enabled
QEISTATCLRBit clear register
Address 0x44005024
Reset 0x00000000
Access read/write
Size 32-bit QEISTATSETBit set register
Address 0x44005028
Reset 0x00000000
Access read/write
Size 32-bit QEISTATINVBit invert register
Address 0x4400502C
Reset 0x00000000
Access read/write
Size 32-bit POSCNTPosition Counter Register
Address 0x44005030
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does POSCNT 31:0 Position Counter
POSCNTCLRBit clear register
Address 0x44005034
Reset 0x00000000
Access read/write
Size 32-bit POSCNTSETBit set register
Address 0x44005038
Reset 0x00000000
Access read/write
Size 32-bit POSCNTINVBit invert register
Address 0x4400503C
Reset 0x00000000
Access read/write
Size 32-bit POSHLDPosition Count Hold Register
Address 0x44005040
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does POSHLD 31:0 Position Count Hold
POSHLDCLRBit clear register
Address 0x44005044
Reset 0x00000000
Access read/write
Size 32-bit POSHLDSETBit set register
Address 0x44005048
Reset 0x00000000
Access read/write
Size 32-bit POSHLDINVBit invert register
Address 0x4400504C
Reset 0x00000000
Access read/write
Size 32-bit VELCNTVelocity Counter Register
Address 0x44005050
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does VELCNT 31:0 Velocity Counter
VELCNTCLRBit clear register
Address 0x44005054
Reset 0x00000000
Access read/write
Size 32-bit VELCNTSETBit set register
Address 0x44005058
Reset 0x00000000
Access read/write
Size 32-bit VELCNTINVBit invert register
Address 0x4400505C
Reset 0x00000000
Access read/write
Size 32-bit VELHLDVelocity Counter Holding Register
Address 0x44005060
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does VELHLD 31:0 Velocity Cout Hold
VELHLDCLRBit clear register
Address 0x44005064
Reset 0x00000000
Access read/write
Size 32-bit VELHLDSETBit set register
Address 0x44005068
Reset 0x00000000
Access read/write
Size 32-bit VELHLDINVBit invert register
Address 0x4400506C
Reset 0x00000000
Access read/write
Size 32-bit INTTMRInterval Timer Register
Address 0x44005070
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does INTTMR 31:0 Interval Timer
INTTMRCLRBit clear register
Address 0x44005074
Reset 0x00000000
Access read/write
Size 32-bit INTTMRSETBit set register
Address 0x44005078
Reset 0x00000000
Access read/write
Size 32-bit INTTMRINVBit invert register
Address 0x4400507C
Reset 0x00000000
Access read/write
Size 32-bit INTHLDInterval Timer Holding Register
Address 0x44005080
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does INTHLD 31:0 Interval Count Hold
INTHLDCLRBit clear register
Address 0x44005084
Reset 0x00000000
Access read/write
Size 32-bit INTHLDSETBit set register
Address 0x44005088
Reset 0x00000000
Access read/write
Size 32-bit INTHLDINVBit invert register
Address 0x4400508C
Reset 0x00000000
Access read/write
Size 32-bit INDXCNTIndex Counter Register
Address 0x44005090
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does INDXCNT 31:0 Index Counter
INDXCNTCLRBit clear register
Address 0x44005094
Reset 0x00000000
Access read/write
Size 32-bit INDXCNTSETBit set register
Address 0x44005098
Reset 0x00000000
Access read/write
Size 32-bit INDXCNTINVBit invert register
Address 0x4400509C
Reset 0x00000000
Access read/write
Size 32-bit INDXHLDIndex Counter Holding Register
Address 0x440050A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does INDXHLD 31:0 Index Count Hold
INDXHLDCLRBit clear register
Address 0x440050A4
Reset 0x00000000
Access read/write
Size 32-bit INDXHLDSETBit set register
Address 0x440050A8
Reset 0x00000000
Access read/write
Size 32-bit INDXHLDINVBit invert register
Address 0x440050AC
Reset 0x00000000
Access read/write
Size 32-bit QEIICCQEI Initialize/Capture/Compare Register
Address 0x440050B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does QEIICC 31:0 32-bit Initialize/Capture/Compare High bits
QEIICCCLRBit clear register
Address 0x440050B4
Reset 0x00000000
Access read/write
Size 32-bit QEIICCSETBit set register
Address 0x440050B8
Reset 0x00000000
Access read/write
Size 32-bit QEIICCINVBit invert register
Address 0x440050BC
Reset 0x00000000
Access read/write
Size 32-bit QEICMPLCapture Low Register
Address 0x440050C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does QEICMPL 31:0 32-bit Compare Low Value bits
QEICMPLCLRBit clear register
Address 0x440050C4
Reset 0x00000000
Access read/write
Size 32-bit QEICMPLSETBit set register
Address 0x440050C8
Reset 0x00000000
Access read/write
Size 32-bit QEICMPLINVBit invert register
Address 0x440050CC
Reset 0x00000000
Access read/write
Size 32-bit 
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