The 45 registers of ADC (Analog-to-Digital Converter), from 0x40024000, with their reset value and every field. The PIC32CX2051MTG128 has 2875 registers in 60 peripherals, one page each.
ADC Analog-to-Digital Converter
ADC_CRControl Register
Address
0x40024000
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
Field
Bits
What it does
CMPRST
4
Comparison Restart
SWFIFO
3
Software FIFO Reset
START
1
Start Conversion
SWRST
0
Software Reset
ADC_MRMode Register
Address
0x40024004
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
ALWAYS1
30
TRANSFER
29:28
Transfer Time
TRACKTIM
27:24
Tracking Time
ANACH
23
Analog Change
0 No analog change on channel switching: DIFF0 is used for all channels.
1 Allows different analog settings for each channel. See ADC Channel Configuration Register.
STARTUP
19:16
Startup Time
0 0 period of ADCCLK
1 8 periods of ADCCLK
2 16 periods of ADCCLK
3 24 periods of ADCCLK
4 64 periods of ADCCLK
5 80 periods of ADCCLK
6 96 periods of ADCCLK
7 112 periods of ADCCLK
8 512 periods of ADCCLK
9 576 periods of ADCCLK
10 640 periods of ADCCLK
11 704 periods of ADCCLK
12 768 periods of ADCCLK
13 832 periods of ADCCLK
14 896 periods of ADCCLK
15 960 periods of ADCCLK
PRESCAL
15:8
Prescaler Rate Selection
FWUP
6
Fast Wake-up
0 If SLEEP is 1, then both ADC core and reference voltage circuitry are off between conversions.
1 If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is on between conversions and ADC core is off.
SLEEP
5
Sleep Mode
0 Normal mode: The ADC core and reference voltage circuitry are kept on between conversions.
1 Sleep mode: The wake-up time can be modified by programming the FWUP bit.
TRGSEL
3:1
Trigger Selection
0 PWM event line 0
1 TIOA0 TC0
2 TIOA1 TC0
3 TIOA2 TC0
4 TIOA0 TC1
5 TIOA1 TC1
6 RTCOUT0
USEQ
31
User Sequence Enable
0 Normal mode: The controller converts channels in a simple numeric order depending only on the channel index.
1 User Sequence mode: The sequence respects what is defined in ADC_SEQR1and can be used to convert the same channel several times.
ADC_SEQR1Channel Sequence Register 1
Address
0x40024008
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
USCH7
27:24
User Sequence Number 7
USCH6
23:20
User Sequence Number 6
USCH5
19:16
User Sequence Number 5
USCH4
15:12
User Sequence Number 4
USCH3
11:8
User Sequence Number 3
USCH2
7:4
User Sequence Number 2
USCH1
3:0
User Sequence Number 1
USCH8
31:28
User Sequence Number 8
ADC_CHERChannel Enable Register
Address
0x40024010
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
Field
Bits
What it does
CH7
7
Channel 7 Enable
CH6
6
Channel 6 Enable
CH5
5
Channel 5 Enable
CH4
4
Channel 4 Enable
CH3
3
Channel 3 Enable
CH2
2
Channel 2 Enable
CH1
1
Channel 1 Enable
CH0
0
Channel 0 Enable
ADC_CHDRChannel Disable Register
Address
0x40024014
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
Field
Bits
What it does
CH7
7
Channel 7 Disable
CH6
6
Channel 6 Disable
CH5
5
Channel 5 Disable
CH4
4
Channel 4 Disable
CH3
3
Channel 3 Disable
CH2
2
Channel 2 Disable
CH1
1
Channel 1 Disable
CH0
0
Channel 0 Disable
ADC_CHSRChannel Status Register
Address
0x40024018
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
CH7
7
Channel 7 Status
CH6
6
Channel 6 Status
CH5
5
Channel 5 Status
CH4
4
Channel 4 Status
CH3
3
Channel 3 Status
CH2
2
Channel 2 Status
CH1
1
Channel 1 Status
CH0
0
Channel 0 Status
ADC_LCDRLast Converted Data Register
Address
0x40024020
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
CHNBOSR
28:24
Channel Number in Oversampling Mode
LDATA
15:0
Last Data Converted
NO_OSR_CHNB
15:12
Channel Number when No Oversampling
NO_OSR_LDATA
11:0
Last Data Converted when No Oversampling
ADC_IERInterrupt Enable Register
Address
0x40024024
Reset
0x00000000
Access
write only
Size
32-bit
14 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Enable
ENDRX
27
End of Receive Transfer Interrupt Enable
COMPE
26
Comparison Event Interrupt Enable
GOVRE
25
General Overrun Error Interrupt Enable
DRDY
24
Data Ready Interrupt Enable
TEMPCHG
19
Temperature Change Interrupt Enable
EOS
18
End Of Sequence Interrupt Enable
SMEV
6
Supply Monitor Event Interrupt Enable
RXOVR
5
Receive Over Flow Interrupt Enable
RXUDR
4
Receive Under Flow Interrupt Enable
RXCHUNK
3
Receive FIFO Chunk Interrupt Enable
RXFULL
2
Receive FIFO Full Interrupt Enable
RXEMPTY
1
Receive FIFO Empty Interrupt Enable
RXRDY
0
Receive Ready Interrupt Enable
ADC_IDRInterrupt Disable Register
Address
0x40024028
Reset
0x00000000
Access
write only
Size
32-bit
14 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Disable
ENDRX
27
End of Receive Transfer Interrupt Disable
COMPE
26
Comparison Event Interrupt Disable
GOVRE
25
General Overrun Error Interrupt Disable
DRDY
24
Data Ready Interrupt Disable
TEMPCHG
19
Temperature Change Interrupt Disable
EOS
18
End Of Sequence Interrupt Disable
SMEV
6
Supply Monitor Event Interrupt Disable
RXOVR
5
Receive Over Flow Interrupt Disable
RXUDR
4
Receive Under Flow Interrupt Disable
RXCHUNK
3
Receive FIFO Chunk Interrupt Disable
RXFULL
2
Receive FIFO Full Interrupt Disable
RXEMPTY
1
Receive FIFO Empty Interrupt Disable
RXRDY
0
Receive Ready Interrupt Disable
ADC_IMRInterrupt Mask Register
Address
0x4002402C
Reset
0x00000000
Access
read only
Size
32-bit
14 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full Interrupt Mask
ENDRX
27
End of Receive Transfer Interrupt Mask
COMPE
26
Comparison Event Interrupt Mask
GOVRE
25
General Overrun Error Interrupt Mask
DRDY
24
Data Ready Interrupt Mask
TEMPCHG
19
Temperature Change Interrupt Mask
EOS
18
End Of Sequence Interrupt Mask
SMEV
6
Supply Monitor Event Interrupt Mask
RXOVR
5
Receive Over Flow Interrupt Mask
RXUDR
4
Receive Under Flow Interrupt Mask
RXCHUNK
3
Receive FIFO Chunk Interrupt Mask
RXFULL
2
Receive FIFO Full Interrupt Mask
RXEMPTY
1
Receive FIFO Empty Interrupt Mask
RXRDY
0
Receive Ready Interrupt Mask
ADC_ISRInterrupt Status Register
Address
0x40024030
Reset
0x00000000
Access
read only
Size
32-bit
14 fields
Field
Bits
What it does
RXBUFF
28
Receive Buffer Full (cleared by writing ADC_RCR or ADC_RNCR)
ENDRX
27
End of Receive Transfer (cleared by writing ADC_RCR or ADC_RNCR)
COMPE
26
Comparison Event (cleared on read)
GOVRE
25
General Overrun Error (cleared on read)
DRDY
24
Data Ready (automatically set / cleared)
TEMPCHG
19
Temperature Change (cleared on read)
EOS
18
End Of Sequence (cleared on read)
SMEV
6
Supply Monitor Event (cleared on read)
RXOVR
5
Receive Over Flow (cleared on read)
RXUDR
4
Receive Under Flow (cleared on read)
RXCHUNK
3
Receive FIFO Chunk (cleared on read)
RXFULL
2
Receive FIFO Full (cleared on read)
RXEMPTY
1
Receive FIFO Empty (cleared on read)
RXRDY
0
Receive Ready (cleared on read)
ADC_EOC_IEREnd Of Conversion Interrupt Enable Register
Address
0x40024034
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
Field
Bits
What it does
EOC7
7
End of Conversion Interrupt Enable 7
EOC6
6
End of Conversion Interrupt Enable 6
EOC5
5
End of Conversion Interrupt Enable 5
EOC4
4
End of Conversion Interrupt Enable 4
EOC3
3
End of Conversion Interrupt Enable 3
EOC2
2
End of Conversion Interrupt Enable 2
EOC1
1
End of Conversion Interrupt Enable 1
EOC0
0
End of Conversion Interrupt Enable 0
ADC_EOC_IDREnd Of Conversion Interrupt Disable Register
Address
0x40024038
Reset
0x00000000
Access
write only
Size
32-bit
8 fields
Field
Bits
What it does
EOC7
7
End of Conversion Interrupt Disable 7
EOC6
6
End of Conversion Interrupt Disable 6
EOC5
5
End of Conversion Interrupt Disable 5
EOC4
4
End of Conversion Interrupt Disable 4
EOC3
3
End of Conversion Interrupt Disable 3
EOC2
2
End of Conversion Interrupt Disable 2
EOC1
1
End of Conversion Interrupt Disable 1
EOC0
0
End of Conversion Interrupt Disable 0
ADC_EOC_IMREnd Of Conversion Interrupt Mask Register
Address
0x4002403C
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
EOC7
7
End of Conversion Interrupt Mask 7
EOC6
6
End of Conversion Interrupt Mask 6
EOC5
5
End of Conversion Interrupt Mask 5
EOC4
4
End of Conversion Interrupt Mask 4
EOC3
3
End of Conversion Interrupt Mask 3
EOC2
2
End of Conversion Interrupt Mask 2
EOC1
1
End of Conversion Interrupt Mask 1
EOC0
0
End of Conversion Interrupt Mask 0
ADC_EOC_ISREnd Of Conversion Interrupt Status Register
Address
0x40024040
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
EOC7
7
End of Conversion 7 (automatically set / cleared)
EOC6
6
End of Conversion 6 (automatically set / cleared)
EOC5
5
End of Conversion 5 (automatically set / cleared)
EOC4
4
End of Conversion 4 (automatically set / cleared)
EOC3
3
End of Conversion 3 (automatically set / cleared)
EOC2
2
End of Conversion 2 (automatically set / cleared)
EOC1
1
End of Conversion 1 (automatically set / cleared)
EOC0
0
End of Conversion 0 (automatically set / cleared)
ADC_TEMPMRTemperature Sensor Mode Register
Address
0x40024044
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TEMPCMPMOD
5:4
Temperature Comparison Mode
0 Generates the TEMPCHG flag in ADC_ISR when the converted data is lower than the low threshold of the window.
1 Generates the TEMPCHG flag in ADC_ISR when the converted data is higher than the high threshold of the window.
2 Generates the TEMPCHG flag in ADC_ISR when the converted data is in the comparison window.
3 Generates the TEMPCHG flag in ADC_ISR when the converted data is out of the comparison window.
TEMPON
0
Temperature Sensor On
ADC_TEMPCWRTemperature Compare Window Register
Address
0x40024048
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
THIGHTHRES
27:16
Temperature High Threshold
TLOWTHRES
11:0
Temperature Low Threshold
ADC_OVEROverrun Status Register
Address
0x4002404C
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
OVRE7
7
Overrun Error 7
OVRE6
6
Overrun Error 6
OVRE5
5
Overrun Error 5
OVRE4
4
Overrun Error 4
OVRE3
3
Overrun Error 3
OVRE2
2
Overrun Error 2
OVRE1
1
Overrun Error 1
OVRE0
0
Overrun Error 0
ADC_EMRExtended Mode Register
Address
0x40024050
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
ADCMODE
29:28
ADC Running Mode
0 Normal mode of operation.
1 Offset Error mode to measure the offset error. See Table 6-6 "ADC Running Modes".
2 Gain Error mode to measure the gain error. See Table 6-6 "ADC Running Modes".
3 Gain Error mode to measure the gain error. See Table 6-6 "ADC Running Modes".
SIGNMODE
26:25
Sign Mode
0 Single-ended channels: unsigned conversions Differential channels: signed conversions
1 Single-ended channels: signed conversions Differential channels: unsigned conversions
2 All channels: unsigned conversions
3 All channels: signed conversions
TAG
24
ADC_LCDR Tag
TRACKX
23:22
Tracking Time x4, x8 or x16
0 ADC_MR.TRACKTIM effect is multiplied by 1.
1 ADC_MR.TRACKTIM effect is multiplied by 4.
2 ADC_MR.TRACKTIM effect is multiplied by 8
3 ADC_MR.TRACKTIM effect is multiplied by 16.
SRCCLK
21
External Clock Selection
0 The peripheral clock is the source for the ADC prescaler.
1 GCLK is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock.
ASTE
20
Averaging on Single Trigger Event
0 The average requests several trigger events.
1 The average requests only one trigger event.
OSR
18:16
Over Sampling Rate
0 No averaging. ADC sample rate is maximum.
1 1-bit enhanced resolution by averaging. ADC sample rate divided by 4.
2 2-bit enhanced resolution by averaging. ADC sample rate divided by 16.
3 1-bit enhanced resolution by averaging. ADC sample rate divided by 64
4 2-bit enhanced resolution by averaging. ADC sample rate divided by 256.
CMPFILTER
13:12
Compare Event Filtering
CMPALL
9
Compare All Channels
CMPSEL
8:4
Comparison Selected Channel
CMPTYPE
2
Comparison Type
0 Any conversion is performed and comparison function drives the COMPE flag.
1 Comparison conditions must be met to start the storage of all conversions until ADC_CR.CMPRST is set.
CMPMODE
1:0
Comparison Mode
0 When the converted data is lower than the low threshold of the window, generates the COMPE flag in ADC_ISR or, in Partial Wake-up mode, defines the conditions to exit the system from Wait mode.
1 When the converted data is higher than the high threshold of the window, generates the COMPE flag in ADC_ISR or, in Partial Wake-up mode, defines the conditions to exit the system from Wait mode.
2 When the converted data is in the comparison window, generates the COMPE flag in ADC_ISR or, in Partial Wake-up mode, defines the conditions to exit the system from Wait mode.
3 When the converted data is out of the comparison window, generates the COMPE flag in ADC_ISR or, in Partial Wake-up mode, defines the conditions to exit the system from Wait mode.
ADC_CWRCompare Window Register
Address
0x40024054
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
LOWTHRES
15:0
Low Threshold
HIGHTHRES
31:16
High Threshold
ADC_CCRChannel Configuration Register
Address
0x4002405C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DIFF7
7
Differential Inputs for Channel 7
DIFF6
6
Differential Inputs for Channel 6
DIFF5
5
Differential Inputs for Channel 5
DIFF4
4
Differential Inputs for Channel 4
DIFF3
3
Differential Inputs for Channel 3
DIFF2
2
Differential Inputs for Channel 2
DIFF1
1
Differential Inputs for Channel 1
DIFF0
0
Differential Inputs for Channel 0
ADC_CDR0Channel Data Register
Address
0x40024060
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
15:0
Converted Data
ADC_CDR1Channel Data Register
Address
0x40024064
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
15:0
Converted Data
ADC_CDR2Channel Data Register
Address
0x40024068
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
15:0
Converted Data
ADC_CDR3Channel Data Register
Address
0x4002406C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
15:0
Converted Data
ADC_CDR4Channel Data Register
Address
0x40024070
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
15:0
Converted Data
ADC_CDR5Channel Data Register
Address
0x40024074
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
15:0
Converted Data
ADC_CDR6Channel Data Register
Address
0x40024078
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
15:0
Converted Data
ADC_CDR7Channel Data Register
Address
0x4002407C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
DATA
15:0
Converted Data
ADC_ACRAnalog Control Register
Address
0x400240E0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
SMVT
22
Supply Monitor Voltage Threshold
SMEN
21
Supply Monitor Enable
INTVREFEN
20
ADC Internal Positive Voltage Reference Enable
ZBAT
2
VBAT Resistive Load Selection
ADC_FMRFIFO Mode Register
Address
0x400240E4
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
FIFOCNT
23:16
FIFO Count (read-only)
CHUNK
7:4
Chunk Size
ENLEVEL
1
Enable Level
0 Request to DMA is generated as soon as one data is written in FIFO when FIFO is enabled. CHUNK is not used.
1 Request to DMA is generated as soon as the number of written elements in the FIFO is greater than or equal to CHUNK.
ENFIFO
0
Enable FIFO
0 FIFO is disabled.
1 FIFO is enabled.
ADC_RPRReceive Pointer Register
Address
0x40024100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXPTR
31:0
Receive Pointer Register
ADC_RCRReceive Counter Register
Address
0x40024104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXCTR
15:0
Receive Counter Register
ADC_RNPRReceive Next Pointer Register
Address
0x40024110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNPTR
31:0
Receive Next Pointer
ADC_RNCRReceive Next Counter Register
Address
0x40024114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNCTR
15:0
Receive Next Counter
ADC_PTCRTransfer Control Register
Address
0x40024120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
Field
Bits
What it does
ERRCLR
24
Transfer Bus Error Clear
TXCBDIS
19
Transmitter Circular Buffer Disable
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBDIS
17
Receiver Circular Buffer Disable
RXCBEN
16
Receiver Circular Buffer Enable
TXTDIS
9
Transmitter Transfer Disable
TXTEN
8
Transmitter Transfer Enable
RXTDIS
1
Receiver Transfer Disable
RXTEN
0
Receiver Transfer Enable
ADC_PTSRTransfer Status Register
Address
0x40024124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
ERR
24
Transfer Bus Error
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBEN
16
Receiver Circular Buffer Enable
TXTEN
8
Transmitter Transfer Enable
RXTEN
0
Receiver Transfer Enable
ADC_PWPMRWrite Protection Mode Register
Address
0x40024128
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
WPCREN
2
Write Protection Control Register Enable
WPCTREN
1
Write Protection Counter Registers Enable
WPPTREN
0
Write Protection Pointer Registers Enable
WPKEY
31:8
Write Protection Key
5260355 Writing any other value in this field aborts the write operation. Always reads as 0.
ADC_TRGRTrigger Register
Address
0x40024130
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TRGMOD
2:0
Trigger Mode
0 No hardware trigger, only software trigger can start conversions
1 Rising edge of the selected trigger event, defined in ADC_MR.TRGSEL
2 Falling edge of the selected trigger event
3 Any edge of the selected trigger event
5 ADC internal periodic trigger (see TRGPER)
6 Continuous mode, free run mode
TRGPER
31:8
Trigger Period
ADC_COSRCorrection Select Register
Address
0x40024134
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CSEL
4:0
Channel Correction Select
ADC_CVRCorrection Values Register
Address
0x40024138
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
OFFSETCORR
15:0
Offset Correction
GAINCORR
31:16
Gain Correction
ADC_CECRChannel Error Correction Register
Address
0x4002413C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
ECORR7
7
Error Correction Enable for Channel 7
ECORR6
6
Error Correction Enable for Channel 6
ECORR5
5
Error Correction Enable for Channel 5
ECORR4
4
Error Correction Enable for Channel 4
ECORR3
3
Error Correction Enable for Channel 3
ECORR2
2
Error Correction Enable for Channel 2
ECORR1
1
Error Correction Enable for Channel 1
ECORR0
0
Error Correction Enable for Channel 0
ADC_SRStatus Register
Address
0x40024144
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
VADCSM
0
VDD ADC Supply Monitor Output
ADC_WPMRWrite Protection Mode Register
Address
0x4002414C
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
WPCREN
2
Write Protection Control Register Enable
WPITEN
1
Write Protection Interrupt Enable
WPEN
0
Write Protection Enable
WPKEY
31:8
Write Protection Key
4277315 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
BETA