The 19 registers of SLCDC (Segment LCD Controller), from 0x40030000, with their reset value and every field. The PIC32CX2051MTG128 has 2875 registers in 60 peripherals, one page each.
SLCDC Segment LCD Controller
SLCDC_CRControl Register
Address
0x40030000
Reset
0x00000000
Access
write only
Size
32-bit
6 fields
Field
Bits
What it does
FRZKEY
15:8
Freeze Key (write-only)
78 Writing any other value in this field aborts the write operation of the FRZDF bit or FRZMAP bit. Always reads as 0.
FRZMAP
7
Freeze Remap Configuration
FRZDF
6
Freeze Display Panel Features Configuration
SWRST
3
Software Reset
LCDDIS
1
Disable LCDC
LCDEN
0
Enable the LCDC
SLCDC_MRMode Register
Address
0x40030004
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
LPMODE
24
Low-Power Mode
BIAS
21:20
LCD Display Configuration
0 Static
1 Bias 1/2
2 Bias 1/3
3 Bias 1/4
BUFTIME
19:16
Buffer On-Time
0 Nominal drive time is 0% of SLCK period
1 Nominal drive time is 2 periods of SLCK clock
2 Nominal drive time is 4 periods of SLCK clock
3 Nominal drive time is 8 periods of SLCK clock
4 Nominal drive time is 16 periods of SLCK clock
5 Nominal drive time is 32 periods of SLCK clock
6 Nominal drive time is 64 periods of SLCK clock
7 Nominal drive time is 128 periods of SLCK clock
8 Nominal drive time is 50% of SLCK period
9 Nominal drive time is 100% of SLCK period
SEGSEL
13:8
Selection of the Number of Segments
COMSEL
2:0
Selection of the Number of Commons
0 COM0 is driven by SLCDC, COM1:7 are driven by digital function
1 COM0:1 are driven by SLCDC, COM2:7 are driven by digital function
2 COM0:2 are driven by SLCDC, COM3:7 are driven by digital function
3 COM0:3 are driven by SLCDC, COM4:7 are driven by digital function
4 COM0:4 are driven by SLCDC, COM5:7 are driven by digital function
5 COM0:5 are driven by SLCDC, COM6:7 are driven by digital function
6 COM0:6 are driven by SLCDC, COM7 driven by digital function
7 COM0:7 are driven by SLCDC, no COM pin driven by digital function
SLCDC_FRRFrame Rate Register
Address
0x40030008
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DIV
10:8
Clock Division
0 Clock output from prescaler is divided by 1
1 Clock output from prescaler is divided by 2
2 Clock output from prescaler is divided by 3
3 Clock output from prescaler is divided by 4
4 Clock output from prescaler is divided by 5
5 Clock output from prescaler is divided by 6
6 Clock output from prescaler is divided by 7
7 Clock output from prescaler is divided by 8
PRESC
2:0
Clock Prescaler
0 Slow clock is divided by 8
1 Slow clock is divided by 16
2 Slow clock is divided by 32
3 Slow clock is divided by 64
4 Slow clock is divided by 128
5 Slow clock is divided by 256
6 Slow clock is divided by 512
7 Slow clock is divided by 1024
SLCDC_DRDisplay Register
Address
0x4003000C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
LCDBLKFREQ
15:8
LCD Blinking Frequency Selection
DISPMODE
2:0
Display Mode Register
0 Normal Mode-Latched data are displayed.
1 Force Off Mode-All pixels are invisible. (The SLCDC memory is unchanged.)
2 Force On Mode-All pixels are visible. (The SLCDC memory is unchanged.)
3 Blinking Mode-All pixels are alternately turned off to the predefined state in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
4 Inverted Mode-All pixels are set in the inverted state as defined in SLCDC memory. (The SLCDC memory is unchanged.)
5 Inverted Blinking Mode-All pixels are alternately turned off to the predefined opposite state in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
6 User Buffer Only Load Mode-Blocks the automatic transfer from User Buffer to Display Buffer.
7 Buffer Swap Mode-All pixels are alternatively assigned to the state defined in the User Buffer, then to the state defined in the Display Buffer at LCDBLKFREQ frequency.
SLCDC_SRStatus Register
Address
0x40030010
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
MAPFRZS
7
Remapping Configuration Freeze Status
DFFRZS
6
Display Panel Features Configuration Freeze Status
ENA
0
Enable Status (Automatically Set/Reset)
SLCDC_IERInterrupt Enable Register
Address
0x40030020
Reset
0x00000000
Access
write only
Size
32-bit
2 fields
Field
Bits
What it does
DIS
2
Disable Completion Interrupt Enable
ENDFRAME
0
End of Frame Interrupt Enable
SLCDC_IDRInterrupt Disable Register
Address
0x40030024
Reset
0x00000000
Access
write only
Size
32-bit
2 fields
Field
Bits
What it does
DIS
2
Disable Completion Interrupt Disable
ENDFRAME
0
End of Frame Interrupt Disable
SLCDC_IMRInterrupt Mask Register
Address
0x40030028
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
DIS
2
Disable Completion Interrupt Mask
ENDFRAME
0
End of Frame Interrupt Mask
SLCDC_ISRInterrupt Status Register
Address
0x4003002C
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
DIS
2
Disable Completion Interrupt Status
ENDFRAME
0
End of Frame Interrupt Status
SLCDC_SMR0Segment Map Register 0
Address
0x40030030
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
Field
Bits
What it does
LCD30
30
LCD Segment Mapped on SEGx I/O Pin
LCD29
29
LCD Segment Mapped on SEGx I/O Pin
LCD28
28
LCD Segment Mapped on SEGx I/O Pin
LCD27
27
LCD Segment Mapped on SEGx I/O Pin
LCD26
26
LCD Segment Mapped on SEGx I/O Pin
LCD25
25
LCD Segment Mapped on SEGx I/O Pin
LCD24
24
LCD Segment Mapped on SEGx I/O Pin
LCD23
23
LCD Segment Mapped on SEGx I/O Pin
LCD22
22
LCD Segment Mapped on SEGx I/O Pin
LCD21
21
LCD Segment Mapped on SEGx I/O Pin
LCD20
20
LCD Segment Mapped on SEGx I/O Pin
LCD19
19
LCD Segment Mapped on SEGx I/O Pin
LCD18
18
LCD Segment Mapped on SEGx I/O Pin
LCD17
17
LCD Segment Mapped on SEGx I/O Pin
LCD16
16
LCD Segment Mapped on SEGx I/O Pin
LCD15
15
LCD Segment Mapped on SEGx I/O Pin
LCD14
14
LCD Segment Mapped on SEGx I/O Pin
LCD13
13
LCD Segment Mapped on SEGx I/O Pin
LCD12
12
LCD Segment Mapped on SEGx I/O Pin
LCD11
11
LCD Segment Mapped on SEGx I/O Pin
LCD10
10
LCD Segment Mapped on SEGx I/O Pin
LCD9
9
LCD Segment Mapped on SEGx I/O Pin
LCD8
8
LCD Segment Mapped on SEGx I/O Pin
LCD7
7
LCD Segment Mapped on SEGx I/O Pin
LCD6
6
LCD Segment Mapped on SEGx I/O Pin
LCD5
5
LCD Segment Mapped on SEGx I/O Pin
LCD4
4
LCD Segment Mapped on SEGx I/O Pin
LCD3
3
LCD Segment Mapped on SEGx I/O Pin
LCD2
2
LCD Segment Mapped on SEGx I/O Pin
LCD1
1
LCD Segment Mapped on SEGx I/O Pin
LCD0
0
LCD Segment Mapped on SEGx I/O Pin
LCD31
31
LCD Segment Mapped on SEGx I/O Pin
SLCDC_WPMRWrite Protection Mode Register
Address
0x400300E4
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
WPCREN
2
Write Protection Control Enable
WPITEN
1
Write Protection Interrupt Enable
WPEN
0
Write Protection Enable
WPKEY
31:8
Write Protection Key
5459011 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
BETA