PIC32CX2051MTG128 SUPC registers

The 13 registers of SUPC (Supply Controller), from 0x400531D0, with their reset value and every field. The PIC32CX2051MTG128 has 2875 registers in 60 peripherals, one page each.

SUPC Supply Controller

SUPC_CRControl Register

Address
0x400531D0
Reset
0x00000000
Access
write only
Size
32-bit
5 fields
FieldBitsWhat it does
TDXTALSEL3Timing Domain Slow Clock Selector
  • 0 Slow clock of the timing domain is driven by the embedded 32 kHz (typical) RC oscillator.
  • 1 Slow clock of the timing domain is driven by the 32.768 kHz crystal oscillator.
VROFF2Voltage Regulator Off
  • 0 No effect.
  • 1 If KEY=0xA5, VROFF asserts the VDDCORE domain reset and stops the voltage regulator.
SHDWEOF1Shutdown End Of Frame
SHDW0Shutdown
KEY31:24Password
  • 165 Writing any other value in this field aborts the write operation.

SUPC_SMMRSupply Monitor Mode Register

Address
0x400531D4
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
VDD3V3SMPWRM13VDD3V3 Supply Monitor Power Supply Mode
  • 0 The VDDBU power source selection is controlled by configuring the bit RSTC_MR.PWRSW.
  • 1 The VDDBU power source is VBAT when a VDD3V3 undervoltage is detected by the VDD3V3 supply monitor.
VDD3V3SMRSTEN12VDD3V3 Supply Monitor Reset Enable
VDD3V3SMSMPL10:8VDD3V3 Supply Monitor Sampling Period
  • 0 VDD3V3 supply monitor is disabled
  • 1 Continuous VDD3V3 supply monitoring
  • 2 VDD3V3 supply monitor is enabled for 1 period every 32 MD_SLCK periods Energy optimization in Backup mode with VDD3V3 supplied.
  • 3 VDD3V3 supply monitor is enabled for 1 period every 256 MD_SLCK periods Energy optimization in Backup mode with VDD3V3 supplied.
  • 4 VDD3V3 supply monitor is enabled for 1 period every 2048 MD_SLCK periods Energy optimization in Backup mode with VDD3V3 supplied.
VDD3V3SMTH3:0VDD3V3 Supply Monitor Threshold

SUPC_MRMode Register

Address
0x400531D8
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
OSCBYPASS20Slow Crystal Oscillator Bypass
  • 0 No effect. Clock selection depends on the value of the bit SUPC_CR.TDXTALSEL.
  • 1 The slow crystal oscillator is bypassed if SUPC_CR.TDXTALSEL=1. The bit OSCBYPASS must be set prior to setting the bit TDXTALSEL.
IO_BACKUP_ISO14Backup Domain IO Isolation Control
CORSMDIS13VDDCORE Supply Monitor Disable
CORSMRSTEN12VDDCORE Supply Monitor Reset Enable
VREGDIS7Internal VDDCORE Voltage Regulator Disable
  • 0 Internal VDDCORE voltage regulator is enabled.
  • 1 Internal VDDCORE voltage regulator is disabled (external power supply is used).
CORSMM6VDDCORE Supply Monitor Output Mode
  • 0 VDDCORE supply monitor output value has no effect. Power-on is performed whatever the value of the supply monitor output.
  • 1 VDDCORE supply monitor output value is checked to validate the VDDCORE domain power-on.
LCDMODE5:4LCD Controller Mode of Operation
  • 0 The internal supply source and the external supply source are both deselected (OFF Mode).
  • 2 The external supply source for LCD (VDDLCD) is selected (the embedded LCD voltage regulator is in High-impedance mode).
  • 3 The internal voltage regulator for VDDLCD is selected (Active mode).
LCDOUT3:0LCD Voltage Regulator Output
KEY31:24Password Key
  • 89 Modifies the VREGDIS bit. Other bits are not affected.
  • 165 Writing any other value in this field aborts the write operation.

SUPC_WUMRWakeup Mode Register

Address
0x400531DC
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LPDBC430:28Low-power Debouncer Period of WKUPx
  • 0 Disables the low-power debouncers.
  • 1 WKUPx in active state for at least 2 RTCOUTx clock periods
  • 2 WKUPx in active state for at least 3 RTCOUTx clock periods
  • 3 WKUPx in active state for at least 4 RTCOUTx clock periods
  • 4 WKUPx in active state for at least 5 RTCOUTx clock periods
  • 5 WKUPx in active state for at least 6 RTCOUTx clock periods
  • 6 WKUPx in active state for at least 7 RTCOUTx clock periods
  • 7 WKUPx in active state for at least 8 RTCOUTx clock periods
LPDBC327:25Low-power Debouncer Period of WKUPx
  • 0 Disables the low-power debouncers.
  • 1 WKUPx in active state for at least 2 RTCOUTx clock periods
  • 2 WKUPx in active state for at least 3 RTCOUTx clock periods
  • 3 WKUPx in active state for at least 4 RTCOUTx clock periods
  • 4 WKUPx in active state for at least 5 RTCOUTx clock periods
  • 5 WKUPx in active state for at least 6 RTCOUTx clock periods
  • 6 WKUPx in active state for at least 7 RTCOUTx clock periods
  • 7 WKUPx in active state for at least 8 RTCOUTx clock periods
LPDBC224:22Low-power Debouncer Period of WKUPx
  • 0 Disables the low-power debouncers.
  • 1 WKUPx in active state for at least 2 RTCOUTx clock periods
  • 2 WKUPx in active state for at least 3 RTCOUTx clock periods
  • 3 WKUPx in active state for at least 4 RTCOUTx clock periods
  • 4 WKUPx in active state for at least 5 RTCOUTx clock periods
  • 5 WKUPx in active state for at least 6 RTCOUTx clock periods
  • 6 WKUPx in active state for at least 7 RTCOUTx clock periods
  • 7 WKUPx in active state for at least 8 RTCOUTx clock periods
LPDBC121:19Low-power Debouncer Period of WKUPx
  • 0 Disables the low-power debouncers.
  • 1 WKUPx in active state for at least 2 RTCOUTx clock periods
  • 2 WKUPx in active state for at least 3 RTCOUTx clock periods
  • 3 WKUPx in active state for at least 4 RTCOUTx clock periods
  • 4 WKUPx in active state for at least 5 RTCOUTx clock periods
  • 5 WKUPx in active state for at least 6 RTCOUTx clock periods
  • 6 WKUPx in active state for at least 7 RTCOUTx clock periods
  • 7 WKUPx in active state for at least 8 RTCOUTx clock periods
LPDBC018:16Low-power Debouncer Period of WKUPx
  • 0 Disables the low-power debouncers.
  • 1 WKUPx in active state for at least 2 RTCOUTx clock periods
  • 2 WKUPx in active state for at least 3 RTCOUTx clock periods
  • 3 WKUPx in active state for at least 4 RTCOUTx clock periods
  • 4 WKUPx in active state for at least 5 RTCOUTx clock periods
  • 5 WKUPx in active state for at least 6 RTCOUTx clock periods
  • 6 WKUPx in active state for at least 7 RTCOUTx clock periods
  • 7 WKUPx in active state for at least 8 RTCOUTx clock periods
WKUPDBC14:12Wake-up Inputs Debouncer Period
  • 0 Immediate, no debouncing, detected active at least on one Slow Clock edge.
  • 1 WKUPx shall be in its active state for at least 3 MD_SLCK periods
  • 2 WKUPx shall be in its active state for at least 32 MD_SLCK periods
  • 3 WKUPx shall be in its active state for at least 512 MD_SLCK periods
  • 4 WKUPx shall be in its active state for at least 4,096 MD_SLCK periods
  • 5 WKUPx shall be in its active state for at least 32,768 MD_SLCK periods
FWUPDBC10:8Force Wake-up Inputs Debouncer Period
  • 0 Immediate, no debouncing, detected active at least on one Slow Clock edge.
  • 1 WKUPx shall be in its active state for at least 3 MD_SLCK periods
  • 2 WKUPx shall be in its active state for at least 32 MD_SLCK periods
  • 3 WKUPx shall be in its active state for at least 512 MD_SLCK periods
  • 4 WKUPx shall be in its active state for at least 4,096 MD_SLCK periods
  • 5 WKUPx shall be in its active state for at least 32,768 MD_SLCK periods
LPDBCEN44Tamper Enable for WKUPx Pin
LPDBCEN33Tamper Enable for WKUPx Pin
LPDBCEN22Tamper Enable for WKUPx Pin
LPDBCEN11Tamper Enable for WKUPx Pin
LPDBCEN00Tamper Enable for WKUPx Pin

SUPC_WUIRWakeup Inputs Register

Address
0x400531E0
Reset
0x00000000
Access
read/write
Size
32-bit
30 fields
FieldBitsWhat it does
WKUPT1430Wake-up Input Type 14
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT1329Wake-up Input Type 13
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT1228Wake-up Input Type 12
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT1127Wake-up Input Type 11
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT1026Wake-up Input Type 10
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT925Wake-up Input Type 9
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT824Wake-up Input Type 8
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT723Wake-up Input Type 7
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT622Wake-up Input Type 6
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT521Wake-up Input Type 5
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT420Wake-up Input Type 4
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT319Wake-up Input Type 3
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT218Wake-up Input Type 2
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT117Wake-up Input Type 1
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPT016Wake-up Input Type 0
  • 0 A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
  • 1 A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
WKUPEN1414Wake-up Input Enable 14
WKUPEN1313Wake-up Input Enable 13
WKUPEN1212Wake-up Input Enable 12
WKUPEN1111Wake-up Input Enable 11
WKUPEN1010Wake-up Input Enable 10
WKUPEN99Wake-up Input Enable 9
WKUPEN88Wake-up Input Enable 8
WKUPEN77Wake-up Input Enable 7
WKUPEN66Wake-up Input Enable 6
WKUPEN55Wake-up Input Enable 5
WKUPEN44Wake-up Input Enable 4
WKUPEN33Wake-up Input Enable 3
WKUPEN22Wake-up Input Enable 2
WKUPEN11Wake-up Input Enable 1
WKUPEN00Wake-up Input Enable 0

SUPC_SRStatus Register

Address
0x400531E4
Reset
0x00000000
Access
read only
Size
32-bit
20 fields
FieldBitsWhat it does
RTTS30RTT Wake-up Status (cleared by reading SUPC_WUSR)
FWKUPS29FWUP Wake-up Status (cleared by reading SUPC_WUSR)
BADXTS28Slow Crystal Oscillator Wake-up Status (cleared by reading SUPC_WUSR)
WKUPS27WKUP Wake-up Status (cleared by reading SUPC_WUSR)
SXFME26Slow Crystal Oscillator Frequency Monitor Error (cleared on read)
SXFMS25:24Slow Crystal Oscillator Frequency Monitor Status (cleared on read)
  • 0 No frequency error detected.
  • 1 The frequency has not been correct over 4 consecutive monitoring periods but there are still edges detected on the slow crystal oscillator output.
  • 2 No edge detected in the slow crystal oscillator output for at least 2 consecutive monitoring periods.
LPDBCS420Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)
LPDBCS319Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)
LPDBCS218Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)
LPDBCS117Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)
LPDBCS016Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)
FWUPS12Force Wake-up Pin Status
LCDS8LCD Power Domain Status
VDD3V3SMS6VDD3V3 Supply Monitor Output Status
VDD3V3SMIS5VDD3V3 Supply Monitor Interrupt Status (cleared by reading SUPC_ISR)
VDD3V3SMRSTS4VDD3V3 Supply Monitor Reset Status (cleared by reading SUPC_WUSR)
CORSMRSTS3VDDCORE Supply Monitor Reset Status (cleared by reading SUPC_WUSR)
VDD3V3SMWS2VDD3V3 Supply Monitor Wake-up Status (cleared by reading SUPC_WUSR)
TDOSCSEL0Timing Domain 32 kHz Oscillator Selection Status
  • 0 The timing domain slow clock (TD_SLCK) source is the slow RC oscillator output.
  • 1 The timing domain slow clock source is the 32.768 kHz crystal oscillator output.
RTCS31RTC Wake-up Status (cleared by reading SUPC_WUSR)

SUPC_EMRExtended Mode Register

Address
0x400531EC
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
COREBGEN18VDDCORE Voltage Regulator Bandgap Enable
FULLGPBRC17Full GPBR Clean
FLRSGPBR16Flash Erase GPBR

SUPC_BMRBackup Mode Register

Address
0x400531F0
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
BADXTWKEN10Slow Crystal Oscillator Frequency Error Wake-up Enable
MRTCOUT9RTCOUT0 Outputs Drive Mode
  • 0 RTCOUT0 output is driven according to the configuration of the field RTC_MR.OUT0.
VBATREN8Battery Voltage Event Report Enable
  • 0 Disables the report of event on VBAT voltage.
  • 1 Enables the report of event on VBAT voltage.
VDD3V3SMWKEN6VDD3V3 Supply Monitor Wake-up Enable
  • 0 Wake-up on VDD3V3 supply monitor under voltage detection is disabled.
  • 1 Wake-up on VDD3V3 supply monitor under voltage detection is enabled.
CORPORWKEN5VDDCORE POR Wake-up Enable
  • 0 Wake-up on VDDCORE Power-On Reset Event is disabled.
  • 1 Wake-up on VDDCORE Power-On Reset Event is enabled.
FWUPEN4Force Wake-up Pin Wake-up Enable
  • 0 The fwup signal has no wake-up effect.
  • 1 The fwup signal forces the wake-up of the core power supply.
VBATWKEN2VBAT Supply Monitor Wake-up Enable
  • 0 Wake-up on VBAT supply monitor under voltage detection is disabled.
  • 1 Wake-up on VBAT supply monitor under voltage detection is enabled.
RTCWKEN1Real-time Clock Wake-up Enable
  • 0 The RTC alarm signal has no wake-up effect.
  • 1 The RTC alarm signal forces the wake-up of the core power supply.
RTTWKEN0Real-time Timer Wake-up Enable
  • 0 The RTT alarm signal has no wake-up effect.
  • 1 The RTT alarm signal forces the wake-up of the core power supply.
KEY31:24Password Key
  • 165 Writing any other value in this field aborts the write operation.

SUPC_WUSRWakeup Status Register

Address
0x400531F4
Reset
0x00000000
Access
read only
Size
32-bit
23 fields
FieldBitsWhat it does
WKUPIS1430WKUPx Input Wake-up Status (cleared on read)
WKUPIS1329WKUPx Input Wake-up Status (cleared on read)
WKUPIS1228WKUPx Input Wake-up Status (cleared on read)
WKUPIS1127WKUPx Input Wake-up Status (cleared on read)
WKUPIS1026WKUPx Input Wake-up Status (cleared on read)
WKUPIS925WKUPx Input Wake-up Status (cleared on read)
WKUPIS824WKUPx Input Wake-up Status (cleared on read)
WKUPIS723WKUPx Input Wake-up Status (cleared on read)
WKUPIS622WKUPx Input Wake-up Status (cleared on read)
WKUPIS521WKUPx Input Wake-up Status (cleared on read)
WKUPIS420WKUPx Input Wake-up Status (cleared on read)
WKUPIS319WKUPx Input Wake-up Status (cleared on read)
WKUPIS218WKUPx Input Wake-up Status (cleared on read)
WKUPIS117WKUPx Input Wake-up Status (cleared on read)
WKUPIS016WKUPx Input Wake-up Status (cleared on read)
VDD3V3SMRSTS8VDD3V3 Supply Monitor Reset Status (cleared on read)
RTCS5RTC Wake-up Status (cleared on read)
RTTS4RTT Wake-up Status (cleared on read)
VDD3V3SMWS3VDD3V3 Supply Monitor Wake-up Status (cleared on read)
FWUPS2FWUP Wake-up Status (cleared on read)
BADXTWKS1Slow Crystal Oscillator Frequency Error Wake-up Status (cleared on read)
WKUPS0WKUP Wake-up Status (cleared on read)
WKUPIS1531WKUPx Input Wake-up Status (cleared on read)

SUPC_IEREnable Interrupt Register

Address
0x400531F8
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
VBATSMEV17VBAT Supply Monitor Event Interrupt Enable
VDD3V3SMEV16VDD3V3 Supply Monitor Event Interrupt Enable
LPDBC44WKUPx Pin Tamper Detection Interrupt Enable
LPDBC33WKUPx Pin Tamper Detection Interrupt Enable
LPDBC22WKUPx Pin Tamper Detection Interrupt Enable
LPDBC11WKUPx Pin Tamper Detection Interrupt Enable
LPDBC00WKUPx Pin Tamper Detection Interrupt Enable

SUPC_IDRDisable Interrupt Register

Address
0x400531FC
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
VBATSMEV17VBAT Supply Monitor Event Interrupt Disable
VDD3V3SMEV16VDD3V3 Supply Monitor Event Interrupt Disable
LPDBC44WKUPx Pin Tamper Detection Interrupt Disable
LPDBC33WKUPx Pin Tamper Detection Interrupt Disable
LPDBC22WKUPx Pin Tamper Detection Interrupt Disable
LPDBC11WKUPx Pin Tamper Detection Interrupt Disable
LPDBC00WKUPx Pin Tamper Detection Interrupt Disable

SUPC_IMRMask Interrupt Register

Address
0x40053200
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
VBATSMEV17VBAT Supply Monitor Event Interrupt Mask
VDD3V3SMEV16VDD3V3 Supply Monitor Event Interrupt Mask
LPDBC44WKUPx Pin Tamper Detection Interrupt Mask
LPDBC33WKUPx Pin Tamper Detection Interrupt Mask
LPDBC22WKUPx Pin Tamper Detection Interrupt Mask
LPDBC11WKUPx Pin Tamper Detection Interrupt Mask
LPDBC00WKUPx Pin Tamper Detection Interrupt Mask

SUPC_ISRStatus Interrupt Register

Address
0x40053204
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
VBATSMEV17VBAT Supply Monitor Event Interrupt Status (cleared on read)
VDD3V3SMEV16VDD3V3 Supply Monitor Event Interrupt Status (cleared on read)
LPDBC44WKUPx Pin Tamper Detection Interrupt Status (cleared on read)
LPDBC33WKUPx Pin Tamper Detection Interrupt Status (cleared on read)
LPDBC22WKUPx Pin Tamper Detection Interrupt Status (cleared on read)
LPDBC11WKUPx Pin Tamper Detection Interrupt Status (cleared on read)
LPDBC00WKUPx Pin Tamper Detection Interrupt Status (cleared on read)