The 9 registers of SFR (Special Function Register), from 0x40050410, with their reset value and every field. The PIC32CX2051MTG64 has 2801 registers in 57 peripherals, one page each.
0 If HW_ERASE = 1, and HW erase signal assertion occurs, SRAM0 content is not deleted.
1 If HW_ERASE = 1, and HW erase signal assertion occurs, SRAM0 content is deleted.
HW_ERASE
0
PB2/Peripherals or Hardware Erase Signal Assignment
0 Hardware erase signal disabled. PB2 pin can be used in GPIO or Peripheral IO mode.
1 Hardware erase signal enabled. PB2 pin is assigned to Flash erase function.
SFR_PWM_DEBUGPWM Debug Register
Address
0x400504B4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
CORE1
1
Debug Information Propagation Mode
0 Core x does not send the debug signal to the PWM.
1 Core x sends the debug signal to PWM. Refer to "Debug Mode" in the section "Pulse Width Modulation Controller (PWM)" for details on configuring an action when the debug signal is active.
CORE0
0
Debug Information Propagation Mode
0 Core x does not send the debug signal to the PWM.
1 Core x sends the debug signal to PWM. Refer to "Debug Mode" in the section "Pulse Width Modulation Controller (PWM)" for details on configuring an action when the debug signal is active.
SFR_WAIT_MODEImproved Wait Mode Register
Address
0x400504BC
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CONTROL
0
Improved Wait Mode Control
SFR_WPMRWrite Protection Mode Register
Address
0x400504E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
WPEN
0
Write Protection Enable
WPKEY
31:8
Write Protection Key
5457490 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
BETA