PIC32CX5109BZ31032_SL3 CVD registers

The 25 registers of CVD (Hardware CVD Controller Macro), from 0x44002400, with their reset value and every field. The PIC32CX5109BZ31032_SL3 has 2134 registers in 59 peripherals, one page each.

CVD Hardware CVD Controller Macro

CVDCONCVD Control Register

Address: 0x44002400
Reset: 0x00020000
Access: read/write
Size: 32-bit

13 fields

Field	Bits	What it does
FRZ	30	Freeze Mode1= CVD controller halts in debugger mode0= CVD controller runs in debugger mode
SIDL	29	Stop in Idle Mode bit1= CVD controller halts when device enters Idle mode0= CVD controller continues running in Idle mode
ORDER	28	RX/TX Loop Order1= Scan all requested TX indexes, then increment RX index and continue0= Scan all requested RX indexes, then increment TX index and continue
SDWREN	27	Scan Descriptor Write Enable1= Enables writes to the scan descriptors, and prevents Scan Descriptor EN bits from being decoded and captured intoFSM_CLK domain by the Descriptor Selection Logic. This simplifies synchronization issues. The currently active ScanDescriptor registers should NOT be writte
ABORT	25	Instructs the controller to abort the current scan. The controller will move on to the next enabled ScanDescriptor if there is one, else it will go idle.Cleared by Hardware
SWTRIG	24	Software Trigger control. Starts scan manuallyCleared by Hardware.
THSTR	23	Threshold Store Mode1= Store only results which exceed the programmed threshold for the Scan Descriptor0= Store all results in FIFO
CVDIEN	19	Global Interrupt Enable for full macro. Gates any enabled FIFO or Scan Descriptor interrupts.
FIFOTHIEN	18	FIFO Threshold Interrupt Enable1= Controller will assert an interrupt when the FIFO threshold is met0= Controller will not assert an interrupt when the FIFO threshold is met
FIFOTH	17:8	Threshold for the results FIFO that will cause an interrupt and watermark FIFOWM status bitassertion
CLKSEL	5:4	Clock Select for FSM00= UPB_FSM_CLK01= External clock source 110= External clock source 211= External clock source 3
TRIGSEL	3:0	Selects one of 15 external trigger inputs to start scanning.
ON	31	Enables the State Machine to scan enabled Scan Descriptors upon next trigger.

CVDADCCVD ADC Configuration Register

Address: 0x44002404
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
DIGEN	3	Control differential mode operation of ANN0
DIFFPEN	2	Control differential mode operation of ANN0
SELRES	1:0	Shared ADC Resolution bits

CVDSTATCVD Status Register

Address: 0x44002408
Reset: 0x20000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
FIFOWM	30	The Results FIFO has reached the programmed FIFOTHRESH threshold.
FIFOMT	29	The Results FIFO is empty.
FIFOCNT	25:16	Results FIFO word count: Indicates the number of words in the Results FIFO.
SD4INT	14	Scan Descriptor 4 has caused an interrupt.
SD4DONE	13	Core will set this bit if Scan Descriptor 4 has completed at least once. Core will clear this bit uponreceiving next trigger for Scan Descriptor 4.
SD4BUSY	12	Scan Descriptor 4 is in progress
SD3INT	10	Scan Descriptor 3 has caused an interrupt
SD3DONE	9	Core will set this bit if Scan Descriptor 3 has completed at least once. Core will clear this bit uponreceiving next trigger for Scan Descriptor 3.
SD3BUSY	8	Scan Descriptor 3 is in progress
SD2INT	6	Scan Descriptor 2 has caused an interrupt
SD2DONE	5	Core will set this bit if Scan Descriptor 2 has completed at least once. Core will clear this bit uponreceiving next trigger for Scan Descriptor 2.
SD2BUSY	4	Scan Descriptor 2 is in progress
SD1INT	2	Scan Descriptor 1 has caused an interrupt
SD1DONE	1	Core will set this bit if Scan Descriptor 1 has completed at least once. Core will clear this bit uponreceiving next trigger for Scan Descriptor 1.
SD1BUSY	0	Scan Descriptor 1 is in progress
FIFOFULL	31	The Results FIFO is full.

CVDRESHCVD RESULTS POS FIFO Read Register (CVDRESH)

Address: 0x44002410
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
POS	23:0	The accumulated result of the positive-side measurements.Since the controller supports up to 128x oversampling, each polarity can accumulate up to 23 bits when using a 16-bitADC. The accumulation is not shifted back down to create an average. Therefore, if oversampling was requested, theSW will need

CVDRESLCVD RESULTS NEG FIFO Read Register

Address: 0x44002414
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
NEG	23:0	The accumulated result of the negative-side measurements.Since the controller supports up to 128x oversampling, each polarity can accumulate up to 23 bits when using a 16-bitADC. The accumulation is not shifted back down to create an average. Therefore, if oversampling was requested, theSW will need

CVDRESDCVD RESULTS DESCRIPTOR FIFO Read Register

Address: 0x44002418
Reset: 0x00000000
Access: read only
Size: 32-bit

4 fields

Field	Bits	What it does
SDNUM	25:24	Scan Descriptor Number that generated this result
RXINDEX	23:19	Receive Index for this result. If the Stride of the Scan Descriptor was more than one, the ReceiveIndex indicates the first one of the group.
DELTA	17:0	Delta of the accumulated results of the negative-side and positive-side measurements.
TXINDEX	31:27	Transmit Index for this result. If the Stride of the Scan Descriptor was more than one, the Transmit Index indicates the first one of the group.

CVDRXCVD RECEIVE INDEX N CONFIGURATION Register

Address: 0x44002480
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXAN3	29:24	ANx/CVDR channel to use for RX Index 4n+3
RXAN2	21:16	ANx/CVDR channel to use for RX Index 4n+3
RXAN1	13:8	ANx/CVDR channel to use for RX Index 4n+3
RXAN0	5:0	ANx/CVDR channel to use for RX Index 4n+3

CVDTXCVD TRANSMIT INDEX NCONFIGURATION

Address: 0x440024C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TXAN3	29:24	CVDT channel to use for TX Index
TXAN2	21:16	CVDT channel to use for TX Index
TXAN1	13:8	CVDT channel to use for TX Index
TXAN0	5:0	CVDT channel to use for TX Index

CVDSD0C1CVD SCAN DESCRIPTOR N CONTROL1 REGISTER

Address: 0x44002500
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
SDOVRSAMP	6:0	Scan Descriptor Over Sampling0= One measurement1= Two measurements accumulated...127= 128 measurements accumulated
SDTH	31:8	Scan Descriptor Threshold.

CVDSD0C2CVD SCAN DESCRIPTOR N CONTROL2 REGISTER

Address: 0x44002504
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
SDTXEND	29:24	Scan Descriptor TX Index EndDetermines the last TX index to include in a scan.One the TX index pointer, which is incremented by the SDnTXSTRIDE+1 value, meets or exceeds this value, the TXloop of the scan is complete.
SDTXSTRIDE0	23:22	Scan Descriptor TX Index StrideDetermines the number of TX Indexes included in a single measurement.4'h0= One TX Index4'bF= 16TX Indexes
SDTXBEG	21:16	Scan Descriptor TX Index StartDetermines the first TX index to include in a scan.
SDRXSTRIDE1	15:14	Scan Descriptor RX Index StrideDetermines the number of RX Indexes included in a single measurement4'h0= One RX Index4'hF= 16 TX Indexes
SDRXEND	13:8	Scan Descriptor RX Index EndDetermines the last RX index to include in a scan.One the RX index pointer, which is incremented by the SDnRXSTRIDE+1 value, meets or exceeds this value, the RXloop of the scan is complete.
SDRXSTRIDE0	7:6	Scan Descriptor RX Index StrideDetermines the number of RX Indexes included in a single measurement4'h0= One RX Index4'hF= 16 TX Indexes
SDRXBEG	5:0	Scan Descriptor RX Index StartDetermines the first RX index to include in a scan.
SDTXSTRIDE1	31:30	Scan Descriptor TX Index StrideDetermines the number of TX Indexes included in a single measurement.4'h0= One TX Index4'bF= 16TX Indexes

CVDSD0C3CVD SCAN DESCRIPTOR N CONTROL3 REGISTER

Address: 0x44002508
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
SDBUF	27	Scan Descriptor CVD Buffer Enable1= Use the SOC's CVD Buffer macro to drive the party-line (shared ADC core input) rather than the RX outputs0= SOC's CVD Buffer macro not used to drive party-line (or doesn't exist)
SDINTEN	26	Scan Descriptor Interrupt Enable1= Scan Descriptor creates an interrupt if the accumulator threshold is met0= Scan descriptor does not create an interrupt
SDSELF	25	Scan Descriptor Mutual Mode1= Self Measurement Mode; RX outputs are part of CVD measurement and are driven0= No Self Measurement; RX outputs are not part of CVD measurements
SDMUT	24	Scan Descriptor Mutual Mode1= Mutual Measurement Mode; TX outputs are part of CVD measurement and are driven0=No Mutual Measurement Mode; TX outputs are not part of CVD measurements
CVDEN	19	Capacitive Voltage Division Enable bit
CVDCPL	18:16	Capacitor Voltage Divider (CVD) Setting bits
SDACQTIME	14:8	Scan Descriptor Acquire TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the ACQUIRE stateto allow the ADC voltage to settle
SDCHGTIME	6:0	Scan Descriptor Charge TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the CHARGE statedriving both the internal and external capacitor nodes, as well as the TX output(s)
SDEN	31:30	Scan Descriptor Enable Mode00= Scan Descriptor Disabled01= Execute Scan Descriptor one time only, then clear the enable.10= Execute the Scan Descriptor, but keep enabled. Move on to next enabled descriptors.11= Execute the Scan Descriptor in a loop until a threshold match is detected, then clear the

CVDSD0T2CVD SCAN DESCRIPTOR N TIME2 REGISTER

Address: 0x4400250C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
SDCHNTIME	30:24	Scan Descriptor Channel TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the RXCHAN orTXCHAN state before moving to the next RX/TX pair
SDOVRTIME	22:16	Scan Descriptor Oversample TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the OVERSAMPstate before taking the next oversampling measurement of an RX/TX pair.
SDPOLTIME	14:8	Scan Descriptor Polarity TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the POLARITY statebefore taking the second polarity measurement of an RX/TX pair
SDCONTIME	6:0	Scan Descriptor Charge TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the CONVERT statewaiting for the ADC sample data. It must be ensured that the ADC will assert End-Of-Convert (EOC) before the CONVERT state timer expires.

CVDSD1C1CVD SCAN DESCRIPTOR N CONTROL1 REGISTER

Address: 0x44002510
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
SDOVRSAMP	6:0	Scan Descriptor Over Sampling0= One measurement1= Two measurements accumulated...127= 128 measurements accumulated
SDTH	31:8	Scan Descriptor Threshold.

CVDSD1C2CVD SCAN DESCRIPTOR N CONTROL2 REGISTER

Address: 0x44002514
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
SDTXEND	29:24	Scan Descriptor TX Index EndDetermines the last TX index to include in a scan.One the TX index pointer, which is incremented by the SDnTXSTRIDE+1 value, meets or exceeds this value, the TXloop of the scan is complete.
SDTXSTRIDE0	23:22	Scan Descriptor TX Index StrideDetermines the number of TX Indexes included in a single measurement.4'h0= One TX Index4'bF= 16TX Indexes
SDTXBEG	21:16	Scan Descriptor TX Index StartDetermines the first TX index to include in a scan.
SDRXSTRIDE1	15:14	Scan Descriptor RX Index StrideDetermines the number of RX Indexes included in a single measurement4'h0= One RX Index4'hF= 16 TX Indexes
SDRXEND	13:8	Scan Descriptor RX Index EndDetermines the last RX index to include in a scan.One the RX index pointer, which is incremented by the SDnRXSTRIDE+1 value, meets or exceeds this value, the RXloop of the scan is complete.
SDRXSTRIDE0	7:6	Scan Descriptor RX Index StrideDetermines the number of RX Indexes included in a single measurement4'h0= One RX Index4'hF= 16 TX Indexes
SDRXBEG	5:0	Scan Descriptor RX Index StartDetermines the first RX index to include in a scan.
SDTXSTRIDE1	31:30	Scan Descriptor TX Index StrideDetermines the number of TX Indexes included in a single measurement.4'h0= One TX Index4'bF= 16TX Indexes

CVDSD1C3CVD SCAN DESCRIPTOR N CONTROL3 REGISTER

Address: 0x44002518
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
SDBUF	27	Scan Descriptor CVD Buffer Enable1= Use the SOC's CVD Buffer macro to drive the party-line (shared ADC core input) rather than the RX outputs0= SOC's CVD Buffer macro not used to drive party-line (or doesn't exist)
SDINTEN	26	Scan Descriptor Interrupt Enable1= Scan Descriptor creates an interrupt if the accumulator threshold is met0= Scan descriptor does not create an interrupt
SDSELF	25	Scan Descriptor Mutual Mode1= Self Measurement Mode; RX outputs are part of CVD measurement and are driven0= No Self Measurement; RX outputs are not part of CVD measurements
SDMUT	24	Scan Descriptor Mutual Mode1= Mutual Measurement Mode; TX outputs are part of CVD measurement and are driven0=No Mutual Measurement Mode; TX outputs are not part of CVD measurements
CVDEN	19	Capacitive Voltage Division Enable bit
CVDCPL	18:16	Capacitor Voltage Divider (CVD) Setting bits
SDACQTIME	14:8	Scan Descriptor Acquire TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the ACQUIRE stateto allow the ADC voltage to settle
SDCHGTIME	6:0	Scan Descriptor Charge TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the CHARGE statedriving both the internal and external capacitor nodes, as well as the TX output(s)
SDEN	31:30	Scan Descriptor Enable Mode00= Scan Descriptor Disabled01= Execute Scan Descriptor one time only, then clear the enable.10= Execute the Scan Descriptor, but keep enabled. Move on to next enabled descriptors.11= Execute the Scan Descriptor in a loop until a threshold match is detected, then clear the

CVDSD1T2CVD SCAN DESCRIPTOR N TIME2 REGISTER

Address: 0x4400251C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
SDCHNTIME	30:24	Scan Descriptor Channel TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the RXCHAN orTXCHAN state before moving to the next RX/TX pair
SDOVRTIME	22:16	Scan Descriptor Oversample TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the OVERSAMPstate before taking the next oversampling measurement of an RX/TX pair.
SDPOLTIME	14:8	Scan Descriptor Polarity TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the POLARITY statebefore taking the second polarity measurement of an RX/TX pair
SDCONTIME	6:0	Scan Descriptor Charge TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the CONVERT statewaiting for the ADC sample data. It must be ensured that the ADC will assert End-Of-Convert (EOC) before the CONVERT state timer expires.

CVDSD2C1CVD SCAN DESCRIPTOR N CONTROL1 REGISTER

Address: 0x44002520
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
SDOVRSAMP	6:0	Scan Descriptor Over Sampling0= One measurement1= Two measurements accumulated...127= 128 measurements accumulated
SDTH	31:8	Scan Descriptor Threshold.

CVDSD2C2CVD SCAN DESCRIPTOR N CONTROL2 REGISTER

Address: 0x44002524
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
SDTXEND	29:24	Scan Descriptor TX Index EndDetermines the last TX index to include in a scan.One the TX index pointer, which is incremented by the SDnTXSTRIDE+1 value, meets or exceeds this value, the TXloop of the scan is complete.
SDTXSTRIDE0	23:22	Scan Descriptor TX Index StrideDetermines the number of TX Indexes included in a single measurement.4'h0= One TX Index4'bF= 16TX Indexes
SDTXBEG	21:16	Scan Descriptor TX Index StartDetermines the first TX index to include in a scan.
SDRXSTRIDE1	15:14	Scan Descriptor RX Index StrideDetermines the number of RX Indexes included in a single measurement4'h0= One RX Index4'hF= 16 TX Indexes
SDRXEND	13:8	Scan Descriptor RX Index EndDetermines the last RX index to include in a scan.One the RX index pointer, which is incremented by the SDnRXSTRIDE+1 value, meets or exceeds this value, the RXloop of the scan is complete.
SDRXSTRIDE0	7:6	Scan Descriptor RX Index StrideDetermines the number of RX Indexes included in a single measurement4'h0= One RX Index4'hF= 16 TX Indexes
SDRXBEG	5:0	Scan Descriptor RX Index StartDetermines the first RX index to include in a scan.
SDTXSTRIDE1	31:30	Scan Descriptor TX Index StrideDetermines the number of TX Indexes included in a single measurement.4'h0= One TX Index4'bF= 16TX Indexes

CVDSD2C3CVD SCAN DESCRIPTOR N CONTROL3 REGISTER

Address: 0x44002528
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
SDBUF	27	Scan Descriptor CVD Buffer Enable1= Use the SOC's CVD Buffer macro to drive the party-line (shared ADC core input) rather than the RX outputs0= SOC's CVD Buffer macro not used to drive party-line (or doesn't exist)
SDINTEN	26	Scan Descriptor Interrupt Enable1= Scan Descriptor creates an interrupt if the accumulator threshold is met0= Scan descriptor does not create an interrupt
SDSELF	25	Scan Descriptor Mutual Mode1= Self Measurement Mode; RX outputs are part of CVD measurement and are driven0= No Self Measurement; RX outputs are not part of CVD measurements
SDMUT	24	Scan Descriptor Mutual Mode1= Mutual Measurement Mode; TX outputs are part of CVD measurement and are driven0=No Mutual Measurement Mode; TX outputs are not part of CVD measurements
CVDEN	19	Capacitive Voltage Division Enable bit
CVDCPL	18:16	Capacitor Voltage Divider (CVD) Setting bits
SDACQTIME	14:8	Scan Descriptor Acquire TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the ACQUIRE stateto allow the ADC voltage to settle
SDCHGTIME	6:0	Scan Descriptor Charge TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the CHARGE statedriving both the internal and external capacitor nodes, as well as the TX output(s)
SDEN	31:30	Scan Descriptor Enable Mode00= Scan Descriptor Disabled01= Execute Scan Descriptor one time only, then clear the enable.10= Execute the Scan Descriptor, but keep enabled. Move on to next enabled descriptors.11= Execute the Scan Descriptor in a loop until a threshold match is detected, then clear the

CVDSD2T2CVD SCAN DESCRIPTOR N TIME2 REGISTER

Address: 0x4400252C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
SDCHNTIME	30:24	Scan Descriptor Channel TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the RXCHAN orTXCHAN state before moving to the next RX/TX pair
SDOVRTIME	22:16	Scan Descriptor Oversample TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the OVERSAMPstate before taking the next oversampling measurement of an RX/TX pair.
SDPOLTIME	14:8	Scan Descriptor Polarity TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the POLARITY statebefore taking the second polarity measurement of an RX/TX pair
SDCONTIME	6:0	Scan Descriptor Charge TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the CONVERT statewaiting for the ADC sample data. It must be ensured that the ADC will assert End-Of-Convert (EOC) before the CONVERT state timer expires.

CVDSD3C1CVD SCAN DESCRIPTOR N CONTROL1 REGISTER

Address: 0x44002530
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
SDOVRSAMP	6:0	Scan Descriptor Over Sampling0= One measurement1= Two measurements accumulated...127= 128 measurements accumulated
SDTH	31:8	Scan Descriptor Threshold.

CVDSD3C2CVD SCAN DESCRIPTOR N CONTROL2 REGISTER

Address: 0x44002534
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
SDTXEND	29:24	Scan Descriptor TX Index EndDetermines the last TX index to include in a scan.One the TX index pointer, which is incremented by the SDnTXSTRIDE+1 value, meets or exceeds this value, the TXloop of the scan is complete.
SDTXSTRIDE0	23:22	Scan Descriptor TX Index StrideDetermines the number of TX Indexes included in a single measurement.4'h0= One TX Index4'bF= 16TX Indexes
SDTXBEG	21:16	Scan Descriptor TX Index StartDetermines the first TX index to include in a scan.
SDRXSTRIDE1	15:14	Scan Descriptor RX Index StrideDetermines the number of RX Indexes included in a single measurement4'h0= One RX Index4'hF= 16 TX Indexes
SDRXEND	13:8	Scan Descriptor RX Index EndDetermines the last RX index to include in a scan.One the RX index pointer, which is incremented by the SDnRXSTRIDE+1 value, meets or exceeds this value, the RXloop of the scan is complete.
SDRXSTRIDE0	7:6	Scan Descriptor RX Index StrideDetermines the number of RX Indexes included in a single measurement4'h0= One RX Index4'hF= 16 TX Indexes
SDRXBEG	5:0	Scan Descriptor RX Index StartDetermines the first RX index to include in a scan.
SDTXSTRIDE1	31:30	Scan Descriptor TX Index StrideDetermines the number of TX Indexes included in a single measurement.4'h0= One TX Index4'bF= 16TX Indexes

CVDSD3C3CVD SCAN DESCRIPTOR N CONTROL3 REGISTER

Address: 0x44002538
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
SDBUF	27	Scan Descriptor CVD Buffer Enable1= Use the SOC's CVD Buffer macro to drive the party-line (shared ADC core input) rather than the RX outputs0= SOC's CVD Buffer macro not used to drive party-line (or doesn't exist)
SDINTEN	26	Scan Descriptor Interrupt Enable1= Scan Descriptor creates an interrupt if the accumulator threshold is met0= Scan descriptor does not create an interrupt
SDSELF	25	Scan Descriptor Mutual Mode1= Self Measurement Mode; RX outputs are part of CVD measurement and are driven0= No Self Measurement; RX outputs are not part of CVD measurements
SDMUT	24	Scan Descriptor Mutual Mode1= Mutual Measurement Mode; TX outputs are part of CVD measurement and are driven0=No Mutual Measurement Mode; TX outputs are not part of CVD measurements
CVDEN	19	Capacitive Voltage Division Enable bit
CVDCPL	18:16	Capacitor Voltage Divider (CVD) Setting bits
SDACQTIME	14:8	Scan Descriptor Acquire TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the ACQUIRE stateto allow the ADC voltage to settle
SDCHGTIME	6:0	Scan Descriptor Charge TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the CHARGE statedriving both the internal and external capacitor nodes, as well as the TX output(s)
SDEN	31:30	Scan Descriptor Enable Mode00= Scan Descriptor Disabled01= Execute Scan Descriptor one time only, then clear the enable.10= Execute the Scan Descriptor, but keep enabled. Move on to next enabled descriptors.11= Execute the Scan Descriptor in a loop until a threshold match is detected, then clear the

CVDSD3T2CVD SCAN DESCRIPTOR N TIME2 REGISTER

Address: 0x4400253C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
SDCHNTIME	30:24	Scan Descriptor Channel TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the RXCHAN orTXCHAN state before moving to the next RX/TX pair
SDOVRTIME	22:16	Scan Descriptor Oversample TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the OVERSAMPstate before taking the next oversampling measurement of an RX/TX pair.
SDPOLTIME	14:8	Scan Descriptor Polarity TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the POLARITY statebefore taking the second polarity measurement of an RX/TX pair
SDCONTIME	6:0	Scan Descriptor Charge TimeControls the number of cycles (clock based on CVDCON.CLKSEL[1:0]) the state machine waits in the CONVERT statewaiting for the ADC sample data. It must be ensured that the ADC will assert End-Of-Convert (EOC) before the CONVERT state timer expires.

CVDBGCVD DEBUG REGISTER

Address: 0x44002600
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
SEL_L	15:0	Select signal to MUX debug signals on to port cvd_tst_dbg_data[15:0]
SEL_H	31:16	Select signal to MUX debug signals on to port cvd_tst_dbg_data[31:16]