PIC32CX5109BZ31032_SL3 SILEX Registers – 77 with their bits and fields

CRYPTOCONCrypto control register.

Address: 0x43000000
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
RUNSTDBY	6	Enable clock in idle mode
ENABLE	1	Enable clock to SILEX
SWRST	0	Software Reset

SFR.DMA_FETCH_ADDR_LSB

Address: 0x43010000
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FETCH_ADDR_LSB	31:0

SFR.DMA_FETCH_ADDR_MSB

Address: 0x43010004
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FETCH_ADDR_MSB	31:0

SFR.DMA_FETCH_LEN

Address: 0x43010008
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
FETCH_ZPADDING	30
FETCH_REALIGN	29
FETCH_CSTADDR	28
FETCH_LEN	27:0

SFR.DMA_FETCH_TAG

Address: 0x4301000C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FETCH_TAG	31:0

SFR.DMA_PUSH_ADDR_LSB

Address: 0x43010010
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
PUSH_ADDR_LSB	31:0

SFR.DMA_PUSH_ADDR_MSB

Address: 0x43010014
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
PUSH_ADDR_MSB	31:0

SFR.DMA_PUSH_LEN

Address: 0x43010018
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
PUSH_DISCARD	30
PUSH_REALIGN	29
PUSH_CSTADDR	28
PUSH_LEN	27:0

SFR.DMA_INT_EN

Address: 0x4301001C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
INT_EN	31:0

SFR.DMA_INT_ENSET

Address: 0x43010020
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
INT_ENSET	31:0

SFR.DMA_INT_ENCLR

Address: 0x43010024
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
INT_ENCLR	31:0

SFR.DMA_INT_STATRAW

Address: 0x43010028
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
INT_STATRAW	31:0

SFR.DMA_INT_STAT

Address: 0x4301002C
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
INT_STAT	31:0

SFR.DMA_INT_STATCLR

Address: 0x43010030
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
INT_STATCLR	31:0

SFR.DMA_CONFIG

Address: 0x43010034
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SOFT_RST	4
PUSH_STOP	3
FETCH_STOP	2
PUSH_CTRL_INDIRECT	1
FETCH_CTRL_INDIRECT	0

SFR.DMA_START

Address: 0x43010038
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
START_PUSH	1
START_FETCH	0

SFR.DMA_STATUS

Address: 0x4301003C
Reset: 0x00000000
Access: read only
Size: 32-bit

6 fields

Field	Bits	What it does
SOFT_RST_BUSY	6
PUSH_WAITINGFIFO	5
FETCH_NOT_EMPTY	4
PUSH_BUSY	1
FETCH_BUSY	0
PUSH_NBDATA	31:16

SFR.HWCONF_INCL_IPS_HW_CFG

Address: 0x43010400
Reset: 0x00000000
Access: read only
Size: 32-bit

14 fields

Field	Bits	What it does
BA422_KASUMI_INCLUDED	13	Generic g_IncludeKasumi value. BA422-Kasumi IP included if set
BA423_SNOW3G_INCLUDED	12	Generic g_IncludeSnow3G value. BA423-Snow3G IP included if set
BA420_HP_CHACHAPOLY_INCLUDED	11	Generic g_IncludeHPChachaPoly value. BA420-HP-ChaChaPoly IP included if set
BA431_NDRNG_INCLUDED	10	Generic g_IncludeNDRNG value. BA431-NDRNG IP included if set
BA414EP_PKE_INCLUDED	9	Generic g_IncludePKE value. BA414EP-PKE IP included if set
BA419_SM4_INCLUDED	8	Generic g_IncludeSM4 value. BA419-SM4 IP included if set
BA421_ZUC_INCLUDED	7	Generic g_IncludeZUC value. BA421-ZUC IP included if set
BA418_SHA3_INCLUDED	6	Generic g_IncludeSHA3 value. BA418-SHA3 IP included if set
BA417_CHACHAPOLY_INCLUDED	5	Generic g_IncludeChachaPoly value. BA417-ChaChaPoly IP included if set
BA413_HASH_INCLUDED	4	Generic g_IncludeHASH value. BA413-HASH IP included if set
BA412_DES_INCLUDED	3	Generic g_IncludeDES value. BA412-3DES IP included if set
BA416_HP_AES_XTS_INCLUDED	2	Generic g_IncludeAESXTS value. BA416-HP-AES-XTS IP included if set
BA415_HP_AES_GCM_INCLUDED	1	Generic g_IncludeAESGCM value. BA415-HP-AES-GCM IP included if set
BA411_AES_INCLUDED	0	Generic g_IncludeAES value. BA411E-AES IP included if set

SFR.HWCONF_BA411E_AES_HW_CFG_1

Address: 0x43010404
Reset: 0x00000000
Access: read only
Size: 32-bit

4 fields

Field	Bits	What it does
BA411E_AES_HW_CFG_KEYSIZE	26:24	Generic g_Keysize value. BA411E-AES engine configuration.
BA411E_AES_HW_CFG_MASKING	17	Generic g_UseMasking value. BA411E-AES engine configuration.
BA411E_AES_HW_CFG_CS	16	Generic g_CS value. BA411E-AES engine configuration.
BA411E_AES_HW_CFG_MODE	8:0	Generic g_AesModesPoss value. BA411E-AES engine configuration.

SFR.HWCONF_BA411E_AES_HW_CFG_2Generic g_CtrSize value. BA411E-AES engine configuration.

Address: 0x43010408
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
BA411E_AES_HW_CFG_2	15:0	Generic g_CtrSize value. BA411E-AES engine configuration.

SFR.HWCONF_BA413_HASH_HW_CFG

Address: 0x4301040C
Reset: 0x00000000
Access: read only
Size: 32-bit

4 fields

Field	Bits	What it does
BA413_HASH_HW_CFG_VERIFYDIGEST	18	Generic g_HashVerifyDigest value. BA413-Hash engine configuration.
BA413_HASH_HW_CFG_HMAC	17	Generic g_HMAC_enabled value. BA413-Hash engine configuration.
BA413_HASH_HW_CFG_PASSING	16	Generic g_HashPadding value. BA413-Hash engine configuration.
BA413_HASH_HW_CFG_MASK	6:0	Generic g_HashMaskFunc value. BA413-Hash engine configuration.

SFR.HWCONF_BA418_SHA3_HW_CFGGeneric g_Sha3CtxtEn value. BA418-SHA3 configuration.

Address: 0x43010410
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
BA418_SHA3_HW_CFG	0	Generic g_Sha3CtxtEn value. BA418-SHA3 configuration.

SFR.HWCONF_BA419_SM4_HW_CFGGeneric g_SM4ModesPoss value. BA419-SM4 engine configuration.

Address: 0x43010414
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
BA419_SM4_HW_CFG	6:0	Generic g_SM4ModesPoss value. BA419-SM4 engine configuration.

SFR.HWCONF_BA424_ARIA_HW_CFGGeneric g_aria_modePoss value. BA424-Aria engine configuration.

Address: 0x43010418
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
BA424_ARIA_HW_CFG	8:0	Generic g_aria_modePoss value. BA424-Aria engine configuration.

SFR.RNG_CONTROL_CONTROLControl register

Address: 0x43011000
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
FIFOWRITESTARTUP	20	Enable write of the samples in the FIFO during start-up.
NB128BITBLOCKS	19:16	Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.
AIS31TESTSEL	15	Select input to the AIS31 test module: 0: Before conditioning, 1: After conditioning.
HEALTHTESTSEL	14	Select input to health test module: 0: Before conditioning, 1: After conditioning.
AIS31BYPASS	13	Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state.
HEALTHTESTBYPASS	12	Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state.
FORCEACTIVEROS	11	Force oscillators to run when FIFO is full.
INTENALM	10	Interrupt enable for AIS31 noise alarm.
INTENPRE	9	Interrupt enable for AIS31 preliminary noise alarm.
SOFTRST	8	Software reset: 0: Normal mode, 1: The continuous test, the conditioning function and the FIFO are reset. This bit is not cleared automatically.
INTENFULL	7	Interrupt enable for FIFO full.
INTENPROP	5	Interrupt enable for Adaptive Proportion Test failure (1024-sample window).
INTENREP	4	Interrupt enable for Repetition Count Test failure.
CONDBYPASS	3	0: the conditioning function is used (normal mode), 1: the conditioning function is bypassed (to observe entropy source directly).
TESTEN	2	Select input for conditioning function and continuous tests: 0: Noise source (normal mode), 1: Test data register (test mode).
LFSREN	1	Select between the NDRNG with asynchronous free running oscillators (when '0') and the Pseudo-Random generator with synchronous oscillators for simulation purpose (when '1').
ENABLE	0	Enable the NDRNG.

SFR.RNG_CONTROL_FIFOLEVELFIFO level register.

Address: 0x43011004
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOLEVEL	31:0	Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.

SFR.RNG_CONTROL_FIFOTHRESHOLDFIFO threshold register.

Address: 0x43011008
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOTHRESHOLD	31:0	FIFO level below which the module leaves the idle state to refill the FIFO, expressed in number of 128bit blocks.

SFR.RNG_CONTROL_FIFODEPTHFIFO depth register.

Address: 0x4301100C
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
FIFODEPTH	31:0	Maximum number of 32 bits words that can be stored in the FIFO: 2**g_fifodepth.

SFR.RNG_CONTROL_KEY0Key register (MSB).

Address: 0x43011010
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
KEY0	31:0	Key register (MSB).

SFR.RNG_CONTROL_KEY1Key register.

Address: 0x43011014
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
KEY1	31:0	Key register.

SFR.RNG_CONTROL_KEY2Key register.

Address: 0x43011018
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
KEY2	31:0	Key register.

SFR.RNG_CONTROL_KEY3Key register (LSB).

Address: 0x4301101C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
KEY3	31:0	Key register (LSB).

SFR.RNG_CONTROL_TESTDATATest data register.

Address: 0x43011020
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
TESTDATA	31:0	Test data register.

SFR.RNG_CONTROL_REPEATTHRESHOLDRepetition Test Count Cut-Off value.

Address: 0x43011024
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
REPEATTHRESHOLD	31:0	Repetition Test Count Cut-Off value.

SFR.RNG_CONTROL_PROPTHRESHOLDAdaptive Proportion Test (1024-sample window) Cut-Off value.

Address: 0x43011028
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
PROPTHRESHOLD	31:0	Adaptive Proportion Test (1024-sample window) Cut-Off value.

SFR.RNG_CONTROL_STATUSStatus register.

Address: 0x43011030
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOACCFAIL	11	Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0).
STARTUPFAIL	10	Start-up test failure.
ALMINT	9	AIS31 noise alarm interrupt status.
PREINT	8	AIS31 preliminary noise alarm interrupt status.
FULLINT	7	FIFO full status.
PROPFAIL	5	NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status.
REPFAIL	4	NIST-800-90B repetition Count Test interrupt status.
STATE	3:1	State of the control FSM: 000: Reset, 001: Startup, 010: Idle (Rings On), 011: Idle (Rings Off), 100: Fill FIFO, 101: Error, 110: Unused, 111: Unused.
TESTDATABUSY	0	High when data written to TestData register is being processed. (see section 4.7)

SFR.RNG_CONTROL_INITWAITVALInitial wait counter value.

Address: 0x43011034
Reset: 0x0000FFFF
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
INITWAITVAL	15:0	Number of clock cycles to wait before sampling data from the noise source.

SFR.RNG_CONTROL_DISABLEOSC0Disable oscillator rings #0 to #31.

Address: 0x43011038
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DISABLEOSC0	31:0	Disable oscillator rings #0 to #31.

SFR.RNG_CONTROL_DISABLEOSC1Disable oscillator rings #32 to #63.

Address: 0x4301103C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DISABLEOSC1	31:0	Disable oscillator rings #32 to #63.

SFR.RNG_CONTROL_SWOFFTMRVALSwitch off timer value.

Address: 0x43011040
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SWOFFTMRVAL	15:0	Number of clk cycles to wait before stopping the rings after the FIFO is full.

SFR.RNG_CONTROL_CLKDIVSample clock divider.

Address: 0x43011044
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CLKDIV	7:0	Sample clock divider. The frequency at which the outputs of the rings are sampled is given by: Fs=Fpclk/(ClkDiv+1).

SFR.RNG_CONTROL_AIS31CONF0AIS31 configuration register 0.

Address: 0x43011048
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
STARTUPTHRESHOLD	15:0	Start-up test threshold.
ONLINETHRESHOLD	31:16	Online threshold.

SFR.RNG_CONTROL_AIS31CONF1AIS31 configuration register 1.

Address: 0x4301104C
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ONLINEREPTHRESHOLD	15:0	Online repeat threshold.
HEXPECTEDVALUE	31:16	Expected history value.

SFR.RNG_CONTROL_AIS31CONF2AIS31 configuration register 2.

Address: 0x43011050
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
HMIN	15:0	Minimum allowed history value.
HMAX	31:16	Maximum allowed history value.

SFR.RNG_CONTROL_AIS31STATUSAIS31 status register.

Address: 0x43011054
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PRELIMNOISEALARMREP	17	Last preliminary noise alarm occurred due to consecutive high X**2.
PRELIMNOISEALARMRNG	16	Last preliminary noise alarm occurred due to history value out of range.
NUMPRELIMALARMS	15:0	Number of preliminary noise alarms since counter was last cleared.

SFR.RNG_CONTROL_HWCONFIGHardware configuration register.

Address: 0x43011058
Reset: 0x00000000
Access: read only
Size: 32-bit

3 fields

Field	Bits	What it does
AIS31Full	9	Generic g_AIS31Full value.
AIS31	8	Generic g_AIS31 value.
NUMBOFRINGS	7:0	Generic g_NumRings value.

SFR.PK_POINTERSPointers register.

Address: 0x43012000
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
OPPTRN	27:24	When executing primitive arithmetic operations, this pointer defines the location where the modulus is located in memory (location 0x0 to 0xF).
OPPTRC	19:16	When executing primitive arithmetic operations, this pointer defines the location (0x0 to 0xF) where the result will be stored in memory.
OPPTRB	11:8	When executing primitive arithmetic operations, this pointer defines where operand B is located in memory (location 0x0 to 0xF).
OPPTRA	3:0	When executing primitive arithmetic operations, this pointer defines where operand A is located in memory (location 0x0 to 0xF).

SFR.PK_COMMANDCommand register.

Address: 0x43012004
Reset: 0x0000000F
Access: read/write
Size: 32-bit

12 fields

Field	Bits	What it does
FLAGB	30	See operation description.
FLAGA	29	See operation description.
SWAPBYTES	28	Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.
EDWARDS	26	Enable Edwards curve (see operation description).
RANDPROJ	25	Enable randomization of projective coordinates (counter-measure).
RANDKE	24	Enable randomization of exponent/scalar (counter-measure).
SELCURVE	22:20	Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521 0x4: P192 0x5: Curve25519 0x6: Ed25519 This field has no effect when the optional acceleration hardware is not included.
RANDMOD	19	Enable randomization of modulus (counter-measure).
OPBYTESM1	17:8	This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: - 0x014 -> ECC on curve K-163 - 0x01F -> ECC on curve P-256 - 0x02F -> ECC on curve P-384 - 0x033 -> ECC on curve K-409 -
FIELDF	7	'0': Field is GF(p) '1': Field is GF(2**m)
OPEADDR	6:0	This field defines the operation to be performed. See documentation for more details.
CALCR2	31	This bit indicates if the IP has to calculate R2 mod N for the next operation. This bit must be set to '1' when a new prime number has been programmed. This bit is used for primitive operations and ignored for the other operations. '0': don't recalculate R2 mod N '1': re-calculate R**2 mod N

SFR.PK_CONTROLCommand register.

Address: 0x43012008
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CLEARIRQ	1	Writing a '1' clears the IRQ output.
START	0	Writing a '1' starts the processing.

SFR.PK_STATUSStatus register.

Address: 0x4301200C
Reset: 0x00000000
Access: read only
Size: 32-bit

4 fields

Field	Bits	What it does
FAILPTR	28:24	These bits indicate which data location generated the error flag. They are not available for all error flags.
INTRPTSTATUS	17	This bit reflects the IRQ output value. It is set when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.
PK_BUSY	16	This bit reflects the BUSY output value. It is set when the operation starts and it is cleared when the operation is finished.
ERRORFLAGS	15:4	These bits indicate an error condition. They are updated at the end of the operation. They are cleared when starting a new operation. See documentation for more details.

SFR.PK_TIMERTimer register.

Address: 0x43012014
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TIMER	31:0	Number of core clock cycles.

SFR.PK_HWCONFIGHardware configuration register.

Address: 0x43012018
Reset: 0x00000000
Access: read only
Size: 32-bit

13 fields

Field	Bits	What it does
DISABLECLRMEM	30	State of DisableClrMem input (high when automatic clear of the RAM after reset is disabled).
DISABLESMX	29	State of DisableSMx input (high when SM2/SM9 operations are disabled).
AHBMASTER	25	'0': Memory access through AHB Slave and internally in the PKE. '1': Memory access through AHB Master, outside the PKE.
X25519	24	Support Curve25519/Ed25519 acceleration.
P192	23	Support ECC P192 acceleration.
P521	22	Support ECC P521 acceleration.
P384	21	Support ECC P384 acceleration.
P256	20	Support ECC P256 acceleration.
BINARYFIELD	17	Support binary field.
PRIMEFIELD	16	Support prime field.
NBMULT	15:12	Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers
MAXOPSIZE	11:0	Maximum operand size (number of bytes).
DISABLECM	31	State of DisableCM input (high when counter-measures are disabled).

SFR.PK_OPSIZEOperand size register.

Address: 0x4301201C
Reset: 0x00001000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
OPSIZE	12:0	Operand size (number of bytes): 0x0100: 256 0x0209: 521 0x0800: 2048 0x0C00: 3072 0x1000: 4096 This register is used when the memory is accessed via AHB Master

SFR.PK_MEMOFFSETMemory offset register.

Address: 0x43012020
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
MEMOFFSET	31:0	Memory offset for AHB Master

SFR.PK_MICROCODEOFFSETMicroCode offset register.

Address: 0x43012024
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
MICROCODEOFFSET	31:0	MicroCode offset for AHB Master

SFR.RNG_DATA_CONTROLControl register

Address: 0x43014000
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
FIFOWRITESTARTUP	20	Enable write of the samples in the FIFO during start-up.
NB128BITBLOCKS	19:16	Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.
AIS31TESTSEL	15	Select input to the AIS31 test module: 0: Before conditioning, 1: After conditioning.
HEALTHTESTSEL	14	Select input to health test module: 0: Before conditioning, 1: After conditioning.
AIS31BYPASS	13	Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state.
HEALTHTESTBYPASS	12	Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state.
FORCEACTIVEROS	11	Force oscillators to run when FIFO is full.
INTENALM	10	Interrupt enable for AIS31 noise alarm.
INTENPRE	9	Interrupt enable for AIS31 preliminary noise alarm.
SOFTRST	8	Software reset: 0: Normal mode, 1: The continuous test, the conditioning function and the FIFO are reset. This bit is not cleared automatically.
INTENFULL	7	Interrupt enable for FIFO full.
INTENPROP	5	Interrupt enable for Adaptive Proportion Test failure (1024-sample window).
INTENREP	4	Interrupt enable for Repetition Count Test failure.
CONDBYPASS	3	0: the conditioning function is used (normal mode), 1: the conditioning function is bypassed (to observe entropy source directly).
TESTEN	2	Select input for conditioning function and continuous tests: 0: Noise source (normal mode), 1: Test data register (test mode).
LFSREN	1	Select between the NDRNG with asynchronous free running oscillators (when '0') and the Pseudo-Random generator with synchronous oscillators for simulation purpose (when '1').
ENABLE	0	Enable the NDRNG.

SFR.RNG_DATA_FIFOLEVELFIFO level register.

Address: 0x43014004
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOLEVEL	31:0	Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.

SFR.RNG_DATA_FIFOTHRESHOLDFIFO threshold register.

Address: 0x43014008
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOTHRESHOLD	31:0	FIFO level below which the module leaves the idle state to refill the FIFO, expressed in number of 128bit blocks.

SFR.RNG_DATA_FIFODEPTHFIFO depth register.

Address: 0x4301400C
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
FIFODEPTH	31:0	Maximum number of 32 bits words that can be stored in the FIFO: 2**g_fifodepth.

SFR.RNG_DATA_KEY0Key register (MSB).

Address: 0x43014010
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
KEY0	31:0	Key register (MSB).

SFR.RNG_DATA_KEY1Key register.

Address: 0x43014014
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
KEY1	31:0	Key register.

SFR.RNG_DATA_KEY2Key register.

Address: 0x43014018
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
KEY2	31:0	Key register.

SFR.RNG_DATA_KEY3Key register (LSB).

Address: 0x4301401C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
KEY3	31:0	Key register (LSB).

SFR.RNG_DATA_TESTDATATest data register.

Address: 0x43014020
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
TESTDATA	31:0	Test data register.

SFR.RNG_DATA_REPEATTHRESHOLDRepetition Test Count Cut-Off value.

Address: 0x43014024
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
REPEATTHRESHOLD	31:0	Repetition Test Count Cut-Off value.

SFR.RNG_DATA_PROPTHRESHOLDAdaptive Proportion Test (1024-sample window) Cut-Off value.

Address: 0x43014028
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
PROPTHRESHOLD	31:0	Adaptive Proportion Test (1024-sample window) Cut-Off value.

SFR.RNG_DATA_STATUSStatus register.

Address: 0x43014030
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOACCFAIL	11	Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0).
STARTUPFAIL	10	Start-up test failure.
ALMINT	9	AIS31 noise alarm interrupt status.
PREINT	8	AIS31 preliminary noise alarm interrupt status.
FULLINT	7	FIFO full status.
PROPFAIL	5	NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status.
REPFAIL	4	NIST-800-90B repetition Count Test interrupt status.
STATE	3:1	State of the control FSM: 000: Reset, 001: Startup, 010: Idle (Rings On), 011: Idle (Rings Off), 100: Fill FIFO, 101: Error, 110: Unused, 111: Unused.
TESTDATABUSY	0	High when data written to TestData register is being processed. (see section 4.7)

SFR.RNG_DATA_INITWAITVALInitial wait counter value.

Address: 0x43014034
Reset: 0x0000FFFF
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
INITWAITVAL	15:0	Number of clock cycles to wait before sampling data from the noise source.

SFR.RNG_DATA_DISABLEOSC0Disable oscillator rings #0 to #31.

Address: 0x43014038
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DISABLEOSC0	31:0	Disable oscillator rings #0 to #31.

SFR.RNG_DATA_DISABLEOSC1Disable oscillator rings #32 to #63.

Address: 0x4301403C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DISABLEOSC1	31:0	Disable oscillator rings #32 to #63.

SFR.RNG_DATA_SWOFFTMRVALSwitch off timer value.

Address: 0x43014040
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SWOFFTMRVAL	15:0	Number of clk cycles to wait before stopping the rings after the FIFO is full.

SFR.RNG_DATA_CLKDIVSample clock divider.

Address: 0x43014044
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CLKDIV	7:0	Sample clock divider. The frequency at which the outputs of the rings are sampled is given by: Fs=Fpclk/(ClkDiv+1).

SFR.RNG_DATA_AIS31CONF0AIS31 configuration register 0.

Address: 0x43014048
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
STARTUPTHRESHOLD	15:0	Start-up test threshold.
ONLINETHRESHOLD	31:16	Online threshold.

SFR.RNG_DATA_AIS31CONF1AIS31 configuration register 1.

Address: 0x4301404C
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ONLINEREPTHRESHOLD	15:0	Online repeat threshold.
HEXPECTEDVALUE	31:16	Expected history value.

SFR.RNG_DATA_AIS31CONF2AIS31 configuration register 2.

Address: 0x43014050
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
HMIN	15:0	Minimum allowed history value.
HMAX	31:16	Maximum allowed history value.

SFR.RNG_DATA_AIS31STATUSAIS31 status register.

Address: 0x43014054
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PRELIMNOISEALARMREP	17	Last preliminary noise alarm occurred due to consecutive high X**2.
PRELIMNOISEALARMRNG	16	Last preliminary noise alarm occurred due to history value out of range.
NUMPRELIMALARMS	15:0	Number of preliminary noise alarms since counter was last cleared.

SFR.RNG_DATA_HWCONFIGHardware configuration register.

Address: 0x43014058
Reset: 0x00000000
Access: read only
Size: 32-bit

3 fields

Field	Bits	What it does
AIS31FULL	9	Generic g_AIS31Full value.
AIS31	8	Generic g_AIS31 value.
NUMBOFRINGS	7:0	Generic g_NumRings value.