The 12 registers of RCON, from 0x44000A30, with their reset value and every field. The PIC32CX5109BZ36048 has 2233 registers in 60 peripherals, one page each.
RCON
RCONRESET CONTROL REGISTER
Address
0x44000A30
Reset
0x00000003
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
PORCORE
30
Core Voltage POR Flag bit
0 A Power-up Reset has not occurred due to Core Voltage.
1 A Power-up Reset has occurred due to Core Voltage.
BCFGERR
27
BCFG Error Flag Bit
0 A BCFG Error has not occurred.
1 A BCFG Error has occurred.
BCFGFAIL
26
BCFG Failure Flag Bit
0 A BCFG Failure has not occurred.
1 A BCFG Failure has occurred.
NVMLTA
25
NVM Life Time Alert Flag Bit
0 A NVM LTA Error has not occurred.
1 A NVM LTA Error has occurred.
NVMEOL
24
NVM End of Life Flag Bit
0 A NVM EOL Failure has not occurred.
1 A NVM EOL Failure has occurred.
DPSLP
10
DPSLP Deep Sleep Mode Flag Bit
0 Deep Sleep Mode has not occurred.
1 Deep Sleep Mode has occurred.
CMR
9
Configuration Mismatch Flag bit
0 A Configuration Mismatch Reset Event has not occurred.
1 A Configuration Mismatch Reset Event has occurred.
EXTR
7
External Reset (MCLR) Status bit
0 A Master Clear (pin) Reset has not occurred.
1 A Master Clear (pin) Reset has occurred.
SWR
6
Software Reset Flag bit
0 A Software Commanded Reset has not occurred.
1 A Software Commanded Reset has occurred.
DMTO
5
Deadman Timer Time-Out Flag bit
0 DMT Time-out has not occurred.
1 DMT Time-out has occurred and caused a reset.
WDTO
4
Watchdog Timer Time-Out Flag bit
0 WDT Time-out has not occurred.
1 WDT Time-out has occurred and caused a reset.
SLEEP
3
Wake from Sleep Flag bit
0 Device has not been in Sleep mode.
1 Device has been in Sleep mode.
IDLE
2
Wake from Idle Flag bit
0 Device was not in Idle mode.
1 Device was in Idle mode.
BOR
1
Brown-out Reset Flag bit
0 A Brown-out Reset has not occurred.
1 A Brown-out Reset has occurred.
POR
0
Power-On Reset Flag bit
0 A Power-up Reset has not occurred.
1 A Power-up Reset has occurred.
PORIO
31
IO Voltage POR Flag bit
0 A Power-up Reset has not occurred due to IO Voltage.
1 A Power-up Reset has occurred due to IO Voltage.
RCONCLR
Address
0x44000A34
Reset
0x00000000
Access
read/write
Size
32-bit
RCONSET
Address
0x44000A38
Reset
0x00000000
Access
read/write
Size
32-bit
RCONINV
Address
0x44000A3C
Reset
0x00000000
Access
read/write
Size
32-bit
RSWRSTSOFTWARE RESET REGISTER
Address
0x44000A40
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
SWRST
0
Software Reset Trigger
0 Do not enable software reset event
1 Enable software reset event
RSWRSTCLR
Address
0x44000A44
Reset
0x00000000
Access
read/write
Size
32-bit
RSWRSTSET
Address
0x44000A48
Reset
0x00000000
Access
read/write
Size
32-bit
RSWRSTINV
Address
0x44000A4C
Reset
0x00000000
Access
read/write
Size
32-bit
RNMICONNMI CONTROL REGISTER
Address
0x44000A50
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DMTO
25
Deadman Timer Time-Out Flag bit
0 DMT Time-out has not occurred.
1 DMT Time-out has occurred and caused a NMI.
WDTR
24
Watchdog Timer Time-Out in Run Flag bit
0 WDT Time-out has not occurred.
1 WDT Time-out has occurred and caused a NMI.
SWNMI
23
Software NMI Trigger
0 Writing a 0 to this bit will have no effect.
1 Writing a 1 to this bit will cause an NMI to be generated
GNMI
19
External / Generic NMI Event
0 A general NMI event has not been detected.
1 A general NMI event has been detected and caused an NMI
LVD
18
Programmable Low Voltage Detect Event
0 PLVD has not detected a low voltage condition
1 PLVD has detected a low voltage condition and caused an NMI
CF
17
Clock Fail Detect bit
0 FSCM has not detected clock failure
1 FSCM has detected clock failure and caused an NMI
WDTS
16
Watch-Dog Timer Time-Out in Sleep Flag bit
0 WDT Time-out has not occurred during sleep_mode.
1 WDT Time-out has occurred during sleep_mode and caused a wake-up from sleep.
NMICNT
15:0
NMI Reset counter value
0 No delay between NMI assertion and device reset event
1 1 sys_clk cycle that Software has to clear the NMI event before a device reset is performed.
2 2 sys_clk cycles that Software has to clear the NMI event before a device reset is performed.
65535 65535 sys_clk cycles that Software has to clear the NMI event before a device reset is performed.
BETA