PIC32CX5109BZ36048_SL3 CRU registers The 78 registers of CRU, from 0x44000A00, with their reset value and every field. The PIC32CX5109BZ36048_SL3 has 2233 registers in 60 peripherals, one page each.
CRU OSCCONCRU OSCILLATOR CONTROL REGISTER
Address 0x44000A00
Reset 0x00200005
Access read/write
Size 32-bit 10 fields
Field Bits What it does FRCDIV 26:24 Fast RC Clock Divider bits0 FRC Divide by 11 FRC Divide by 22 FRC Divide by 43 FRC Divide by 84 FRC Divide by 165 FRC Divide by 326 FRC Divide by 647 FRC Divide by 256 DRMEN 23 Enable Dream Mode bit0 DMA transfer has no effect1 When the cpu_si_sleep input is asserted and SLPEN = 1, DMA transfer complete causes SLEEP Mode to be entered WAKE2SPD 21 2-Speed startup enabled in Sleep mode bit0 When the device EXITS Sleep Mode, the sys_clk will be from the selected clock.1 When the device EXITS Sleep Mode, the sys_clk will be from FRC until the selected clock is ready COSC 15:12 Current Oscillator Selection bits (Read-only)0 Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV (Supports FRC/16 and FRC/1)1 System PLL (SPLL1 Module) (input clock and divider set by SPLLCON)2 Primary Oscillator- POSC3 Secondary Oscillator (SOSC)4 Low Power RC Oscillator (LPRC) NOSC 11:8 New Oscillator Selection bits0 Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV ( Supports FRC/16 and FRC/1)1 System PLL (SPLL1 Module) (input clock and divider set by SPLLCON)2 Primary Oscillator3 Secondary Oscillator (SOSC)4 Low Power RC Oscillator (LPRC) CLKLOCK 7 Clock Lock Enabled bit0 Clock and PLL selection registers are not locked, configurations may be modified1 All clock and PLL configuration registers are locked. These include OSCCON, OSCTRIM, SPLLCON, UPLLCON, PBxDIV SLPEN 4 Enable SLEEP Mode bit0 When a WAIT instruction is executed device will enter IDLE Mode1 When a WAIT Instruction is executed device will enter SLEEP Mode CF 3 Clock Fail Detect bit (Read / writable / Clearable by application)0 FSCM has not detected clock failure1 FSCM has detected clock failure SOSCEN 1 32 kHz Secondary (LP) Oscillator Enable bit0 Disable Secondary Oscillator1 Enable Secondary Oscillator OSWEN 0 Oscillator Switch Enable bit0 Oscillator switch is complete1 Request oscillator switch to selection specified by NOSC[3:0] bits
OSCCONCLR
Address 0x44000A04
Reset 0x00000000
Access read/write
Size 32-bit OSCCONSET
Address 0x44000A08
Reset 0x00000000
Access read/write
Size 32-bit OSCCONINV
Address 0x44000A0C
Reset 0x00000000
Access read/write
Size 32-bit OSCTUNCRU OSCILLATOR TRIMMING REGISTER
Address 0x44000A10
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TUN 5:0 Internal Fast RC (FRC) Oscillator Tuning bits0 Center Frequency, oscillator is running at calibrated frequency31 Maximum Frequency32 Minimum Frequency
OSCTUNCLR
Address 0x44000A14
Reset 0x00000000
Access read/write
Size 32-bit OSCTUNSET
Address 0x44000A18
Reset 0x00000000
Access read/write
Size 32-bit OSCTUNINV
Address 0x44000A1C
Reset 0x00000000
Access read/write
Size 32-bit SPLLCONSPLL CONTROL REGISTER
Address 0x44000A20
Reset 0xC0010028
Access read/write
Size 32-bit 6 fields
Field Bits What it does SPLLPOSTDIV2 19:16 SPLL Clock 2 Divide Value, 1 to 150 Disable1 Second post divide by 12 Second post divide by 23 Second post divide by 34 Second post divide by 45 Second post divide by 56 Second post divide by 67 Second post divide by 78 Second post divide by 89 Second post divide by 910 Second post divide by 1011 Second post divide by 1112 Second post divide by 1213 Second post divide by 1314 Second post divide by 1415 Second post divide by 15 SPLLPOSTDIV1 15:8 SPLL Clock 1 Divide Value, 1 to 255 SPLLRST 5 System PLL Reset0 De-assert the reset to the SPLL1 Assert the reset to the SPLL SPLLFLOCK 4 System PLL Force Lock0 Do not force the SPLL lock signal to be asserted1 Force the SPLL lock signal to be asserted SPLLPWDN 3 PLL Power Down Register bit0 PLL is active1 PLL is powered down SPLL_BYP 31:30 SPLL Clock 2 Source0 SPLL3 (RFPLL) Clock is the clock source for ADC CP Clock Generation.2 POSC is used as clock source for ADC CP Clock Generation.3 FRC is used as clock source for ADC CP Clock Generation.
SPLLCONCLR
Address 0x44000A24
Reset 0x00000000
Access read/write
Size 32-bit SPLLCONSET
Address 0x44000A28
Reset 0x00000000
Access read/write
Size 32-bit SPLLCONINV
Address 0x44000A2C
Reset 0x00000000
Access read/write
Size 32-bit REFO1CONREFERENCE OSCILLATOR 1 CONTROL REGISTER
Address 0x44000A70
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does RODIV 30:16 Reference Clock Divider bits0 REFO1 clock is same frequency as Base clock (no divider)1 REFO1 clock is Base clock frequency divided by 2 (1*2)2 REFO1 clock is Base clock frequency divided by 4 (2*2)32767 REFO1 clock is Base clock frequency divided by 65,534 (32,767 *2) ON 15 Output Enable bit0 Reference Oscillator Module disabled1 Reference Oscillator Module enabled FRZ 14 Freeze in Debug mode bit0 When emulator is in Debug mode, module continues operation1 When emulator is in Debug mode, module freezes operation SIDL 13 Peripheral Stop in Idle Mode bit0 Continue module operation in Idle mode1 Discontinue module operation when device enters Idle mode OE 12 Reference Clock Output Enable bit0 Reference clock is not driven out on REFO1 pin.1 Reference clock is driven out on REFO1 pin RSLP 11 Reference Oscillator Run in Sleep bit0 Reference Oscillator output is disabled in Sleep1 Reference Oscillator output continues to run in Sleep DIVSWEN 9 Clock RODIV/ROTRIM switch enabled.0 Clock Divider Switch has completed.1 Clock Divider Switching currently in progress. ACTIVE 8 Reference Clock Request Status bit0 Reference clock request is not active (User can update this REFOCON register)1 Reference clock request is active (User should not update this REFOCON register) ROSEL 3:0 Reference Clock Source Select bits0 FRC1 System PLL1 (Clock-1)2 POSC3 SOSC4 LPRC5 System PLL3 (Clock-3)6 Peripheral clock 1 (reference clock reflects any peripheral clock switching)7 System clock (reference clock reflects any device clock switching)8 REFI Pin
REFO1CONCLR
Address 0x44000A74
Reset 0x00000000
Access read/write
Size 32-bit REFO1CONSET
Address 0x44000A78
Reset 0x00000000
Access read/write
Size 32-bit REFO1CONINV
Address 0x44000A7C
Reset 0x00000000
Access read/write
Size 32-bit REFO1TRIMREFERENCE OSCILLATOR 1 TRIM REGISTER
Address 0x44000A80
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ROTRIM 31:23 Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock0 0/512 (0.0) divisor added to RODIV value1 1/512 (0.001953125) divisor added to RODIV value2 2/512 (0.00390625) divisor added to RODIV value256 256/512 (0.5000) divisor added to RODIV value511 511/512 (0.998046875) divisor added to RODIV value
REFO1TRIMCLR
Address 0x44000A84
Reset 0x00000000
Access read/write
Size 32-bit REFO1TRIMSET
Address 0x44000A88
Reset 0x00000000
Access read/write
Size 32-bit REFO1TRIMINV
Address 0x44000A8C
Reset 0x00000000
Access read/write
Size 32-bit REFO2CONREFERENCE OSCILLATOR 2 CONTROL REGISTER
Address 0x44000A90
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does RODIV 30:16 Reference Clock Divider bits0 REFO2 clock is same frequency as Base clock (no divider)1 REFO2 clock is Base clock frequency divided by 2 (1*2)2 REFO2 clock is Base clock frequency divided by 4 (2*2)32767 REFO2 clock is Base clock frequency divided by 65,534 (32,767 *2) ON 15 Output Enable bit0 Reference Oscillator Module disabled1 Reference Oscillator Module enabled FRZ 14 Freeze in Debug mode bit0 When emulator is in Debug mode, module continues operation1 When emulator is in Debug mode, module freezes operation SIDL 13 Peripheral Stop in Idle Mode bit0 Continue module operation in Idle mode1 Discontinue module operation when device enters Idle mode OE 12 Reference Clock Output Enable bit0 Reference clock is not driven out on REFO2 pin.1 Reference clock is driven out on REFO2 pin RSLP 11 Reference Oscillator Run in Sleep bit0 Reference Oscillator output is disabled in Sleep1 Reference Oscillator output continues to run in Sleep DIVSWEN 9 Clock RODIV/ROTRIM switch enabled.0 Clock Divider Switch has completed.1 Clock Divider Switching currently in progress. ACTIVE 8 Reference Clock Request Status bit0 Reference clock request is not active (User can update this REFOCON register)1 Reference clock request is active (User should not update this REFOCON register) ROSEL 3:0 Reference Clock Source Select bits0 FRC1 System PLL1 (Clock-1)2 POSC3 SOSC4 LPRC5 System PLL3 (Clock-3)6 Peripheral clock 1 (reference clock reflects any peripheral clock switching)7 System clock (reference clock reflects any device clock switching)8 REFI Pin
REFO2CONCLR
Address 0x44000A94
Reset 0x00000000
Access read/write
Size 32-bit REFO2CONSET
Address 0x44000A98
Reset 0x00000000
Access read/write
Size 32-bit REFO2CONINV
Address 0x44000A9C
Reset 0x00000000
Access read/write
Size 32-bit REFO2TRIMREFERENCE OSCILLATOR 2 TRIM REGISTER
Address 0x44000AA0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ROTRIM 31:23 Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock0 0/512 (0.0) divisor added to RODIV value1 1/512 (0.001953125) divisor added to RODIV value2 2/512 (0.00390625) divisor added to RODIV value256 256/512 (0.5000) divisor added to RODIV value511 511/512 (0.998046875) divisor added to RODIV value
REFO2TRIMCLR
Address 0x44000AA4
Reset 0x00000000
Access read/write
Size 32-bit REFO2TRIMSET
Address 0x44000AA8
Reset 0x00000000
Access read/write
Size 32-bit REFO2TRIMINV
Address 0x44000AAC
Reset 0x00000000
Access read/write
Size 32-bit REFO3CONREFERENCE OSCILLATOR 3 CONTROL REGISTER
Address 0x44000AB0
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does RODIV 30:16 Reference Clock Divider bits0 REFO3 clock is same frequency as Base clock (no divider)1 REFO3 clock is Base clock frequency divided by 2 (1*2)2 REFO3 clock is Base clock frequency divided by 4 (2*2)32767 REFO3 clock is Base clock frequency divided by 65,534 (32,767 *2) ON 15 Output Enable bit0 Reference Oscillator Module disabled1 Reference Oscillator Module enabled FRZ 14 Freeze in Debug mode bit0 When emulator is in Debug mode, module continues operation1 When emulator is in Debug mode, module freezes operation SIDL 13 Peripheral Stop in Idle Mode bit0 Continue module operation in Idle mode1 Discontinue module operation when device enters Idle mode OE 12 Reference Clock Output Enable bit0 Reference clock is not driven out on REFO3 pin.1 Reference clock is driven out on REFO3 pin RSLP 11 Reference Oscillator Run in Sleep bit0 Reference Oscillator output is disabled in Sleep1 Reference Oscillator output continues to run in Sleep DIVSWEN 9 Clock RODIV/ROTRIM switch enabled.0 Clock Divider Switch has completed.1 Clock Divider Switching currently in progress. ACTIVE 8 Reference Clock Request Status bit0 Reference clock request is not active (User can update this REFOCON register)1 Reference clock request is active (User should not update this REFOCON register) ROSEL 3:0 Reference Clock Source Select bits0 FRC1 System PLL1 (Clock-1)2 POSC3 SOSC4 LPRC5 System PLL3 (Clock-3)6 Peripheral clock 1 (reference clock reflects any peripheral clock switching)7 System clock (reference clock reflects any device clock switching)8 REFI Pin
REFO3CONCLR
Address 0x44000AB4
Reset 0x00000000
Access read/write
Size 32-bit REFO3CONSET
Address 0x44000AB8
Reset 0x00000000
Access read/write
Size 32-bit REFO3CONINV
Address 0x44000ABC
Reset 0x00000000
Access read/write
Size 32-bit REFO3TRIMREFERENCE OSCILLATOR 3 TRIM REGISTER
Address 0x44000AC0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ROTRIM 31:23 Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock0 0/512 (0.0) divisor added to RODIV value1 1/512 (0.001953125) divisor added to RODIV value2 2/512 (0.00390625) divisor added to RODIV value256 256/512 (0.5000) divisor added to RODIV value511 511/512 (0.998046875) divisor added to RODIV value
REFO3TRIMCLR
Address 0x44000AC4
Reset 0x00000000
Access read/write
Size 32-bit REFO3TRIMSET
Address 0x44000AC8
Reset 0x00000000
Access read/write
Size 32-bit REFO3TRIMINV
Address 0x44000ACC
Reset 0x00000000
Access read/write
Size 32-bit REFO4CONREFERENCE OSCILLATOR 4 CONTROL REGISTER
Address 0x44000AD0
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does RODIV 30:16 Reference Clock Divider bits0 REFO4 clock is same frequency as Base clock (no divider)1 REFO4 clock is Base clock frequency divided by 2 (1*2)2 REFO4 clock is Base clock frequency divided by 4 (2*2)32767 REFO4 clock is Base clock frequency divided by 65,534 (32,767 *2) ON 15 Output Enable bit0 Reference Oscillator Module disabled1 Reference Oscillator Module enabled FRZ 14 Freeze in Debug mode bit0 When emulator is in Debug mode, module continues operation1 When emulator is in Debug mode, module freezes operation SIDL 13 Peripheral Stop in Idle Mode bit0 Continue module operation in Idle mode1 Discontinue module operation when device enters Idle mode OE 12 Reference Clock Output Enable bit0 Reference clock is not driven out on REFO4 pin.1 Reference clock is driven out on REFO4 pin RSLP 11 Reference Oscillator Run in Sleep bit0 Reference Oscillator output is disabled in Sleep1 Reference Oscillator output continues to run in Sleep DIVSWEN 9 Clock RODIV/ROTRIM switch enabled.0 Clock Divider Switch has completed.1 Clock Divider Switching currently in progress. ACTIVE 8 Reference Clock Request Status bit0 Reference clock request is not active (User can update this REFOCON register)1 Reference clock request is active (User should not update this REFOCON register) ROSEL 3:0 Reference Clock Source Select bits0 FRC1 System PLL1 (Clock-1)2 POSC3 SOSC4 LPRC5 System PLL3 (Clock-3)6 Peripheral clock 1 (reference clock reflects any peripheral clock switching)7 System clock (reference clock reflects any device clock switching)8 REFI Pin
REFO4CONCLR
Address 0x44000AD4
Reset 0x00000000
Access read/write
Size 32-bit REFO4CONSET
Address 0x44000AD8
Reset 0x00000000
Access read/write
Size 32-bit REFO4CONINV
Address 0x44000ADC
Reset 0x00000000
Access read/write
Size 32-bit REFO4TRIMREFERENCE OSCILLATOR 4 TRIM REGISTER
Address 0x44000AE0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ROTRIM 31:23 Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock0 0/512 (0.0) divisor added to RODIV value1 1/512 (0.001953125) divisor added to RODIV value2 2/512 (0.00390625) divisor added to RODIV value256 256/512 (0.5000) divisor added to RODIV value511 511/512 (0.998046875) divisor added to RODIV value
REFO4TRIMCLR
Address 0x44000AE4
Reset 0x00000000
Access read/write
Size 32-bit REFO4TRIMSET
Address 0x44000AE8
Reset 0x00000000
Access read/write
Size 32-bit REFO4TRIMINV
Address 0x44000AEC
Reset 0x00000000
Access read/write
Size 32-bit REFO5CONREFERENCE OSCILLATOR 5 CONTROL REGISTER
Address 0x44000AF0
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does RODIV 30:16 Reference Clock Divider bits0 REFO5 clock is same frequency as Base clock (no divider)1 REFO5 clock is Base clock frequency divided by 2 (1*2)2 REFO5 clock is Base clock frequency divided by 4 (2*2)32767 REFO5 clock is Base clock frequency divided by 65,534 (32,767 *2) ON 15 Output Enable bit0 Reference Oscillator Module disabled1 Reference Oscillator Module enabled FRZ 14 Freeze in Debug mode bit0 When emulator is in Debug mode, module continues operation1 When emulator is in Debug mode, module freezes operation SIDL 13 Peripheral Stop in Idle Mode bit0 Continue module operation in Idle mode1 Discontinue module operation when device enters Idle mode OE 12 Reference Clock Output Enable bit0 Reference clock is not driven out on REFO5 pin.1 Reference clock is driven out on REFO5 pin RSLP 11 Reference Oscillator Run in Sleep bit0 Reference Oscillator output is disabled in Sleep1 Reference Oscillator output continues to run in Sleep DIVSWEN 9 Clock RODIV/ROTRIM switch enabled.0 Clock Divider Switch has completed.1 Clock Divider Switching currently in progress. ACTIVE 8 Reference Clock Request Status bit0 Reference clock request is not active (User can update this REFOCON register)1 Reference clock request is active (User should not update this REFOCON register) ROSEL 3:0 Reference Clock Source Select bits0 FRC1 System PLL1 (Clock-1)2 POSC3 SOSC4 LPRC5 System PLL3 (Clock-3)6 Peripheral clock 1 (reference clock reflects any peripheral clock switching)7 System clock (reference clock reflects any device clock switching)8 REFI Pin
REFO5CONCLR
Address 0x44000AF4
Reset 0x00000000
Access read/write
Size 32-bit REFO5CONSET
Address 0x44000AF8
Reset 0x00000000
Access read/write
Size 32-bit REFO5CONINV
Address 0x44000AFC
Reset 0x00000000
Access read/write
Size 32-bit REFO5TRIMREFERENCE OSCILLATOR 5 TRIM REGISTER
Address 0x44000B00
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ROTRIM 31:23 Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock0 0/512 (0.0) divisor added to RODIV value1 1/512 (0.001953125) divisor added to RODIV value2 2/512 (0.00390625) divisor added to RODIV value256 256/512 (0.5000) divisor added to RODIV value511 511/512 (0.998046875) divisor added to RODIV value
REFO5TRIMCLR
Address 0x44000B04
Reset 0x00000000
Access read/write
Size 32-bit REFO5TRIMSET
Address 0x44000B08
Reset 0x00000000
Access read/write
Size 32-bit REFO5TRIMINV
Address 0x44000B0C
Reset 0x00000000
Access read/write
Size 32-bit REFO6CONREFERENCE OSCILLATOR 6 CONTROL REGISTER
Address 0x44000B10
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does RODIV 30:16 Reference Clock Divider bits0 REFO6 clock is same frequency as Base clock (no divider)1 REFO6 clock is Base clock frequency divided by 2 (1*2)2 REFO6 clock is Base clock frequency divided by 4 (2*2)32767 REFO6 clock is Base clock frequency divided by 65,534 (32,767 *2) ON 15 Output Enable bit0 Reference Oscillator Module disabled1 Reference Oscillator Module enabled FRZ 14 Freeze in Debug mode bit0 When emulator is in Debug mode, module continues operation1 When emulator is in Debug mode, module freezes operation SIDL 13 Peripheral Stop in Idle Mode bit0 Continue module operation in Idle mode1 Discontinue module operation when device enters Idle mode OE 12 Reference Clock Output Enable bit0 Reference clock is not driven out on REFO6 pin.1 Reference clock is driven out on REFO6 pin RSLP 11 Reference Oscillator Run in Sleep bit0 Reference Oscillator output is disabled in Sleep1 Reference Oscillator output continues to run in Sleep DIVSWEN 9 Clock RODIV/ROTRIM switch enabled.0 Clock Divider Switch has completed.1 Clock Divider Switching currently in progress. ACTIVE 8 Reference Clock Request Status bit0 Reference clock request is not active (User can update this REFOCON register)1 Reference clock request is active (User should not update this REFOCON register) ROSEL 3:0 Reference Clock Source Select bits0 FRC1 System PLL1 (Clock-1)2 POSC3 SOSC4 LPRC5 System PLL3 (Clock-3)6 Peripheral clock 1 (reference clock reflects any peripheral clock switching)7 System clock (reference clock reflects any device clock switching)8 REFI Pin
REFO6CONCLR
Address 0x44000B14
Reset 0x00000000
Access read/write
Size 32-bit REFO6CONSET
Address 0x44000B18
Reset 0x00000000
Access read/write
Size 32-bit REFO6CONINV
Address 0x44000B1C
Reset 0x00000000
Access read/write
Size 32-bit REFO6TRIMREFERENCE OSCILLATOR 6 TRIM REGISTER
Address 0x44000B20
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ROTRIM 31:23 Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock0 0/512 (0.0) divisor added to RODIV value1 1/512 (0.001953125) divisor added to RODIV value2 2/512 (0.00390625) divisor added to RODIV value256 256/512 (0.5000) divisor added to RODIV value511 511/512 (0.998046875) divisor added to RODIV value
REFO6TRIMCLR
Address 0x44000B24
Reset 0x00000000
Access read/write
Size 32-bit REFO6TRIMSET
Address 0x44000B28
Reset 0x00000000
Access read/write
Size 32-bit REFO6TRIMINV
Address 0x44000B2C
Reset 0x00000000
Access read/write
Size 32-bit PB1DIVPB1 CLOCK DIVISOR CONTROL REGISTER
Address 0x44000B30
Reset 0x00008800
Access read/write
Size 32-bit 3 fields
Field Bits What it does PBDIVON 15 Output Enable bit0 PB1 Output clock is disabled1 PB1 Output clock is enabled PBDIVRDY 11 PB1 Peripheral Clock Divisor Ready0 Indicates the PB clock divisor logic is currently switching values and the PB1DIV cannot be written.1 Indicates the PB clock divisor logic is not switching divisors and the PB1DIV may be written. PBDIV 6:0 PB1 Peripheral Clock Divisor Control value0 Divide by 1 PB1 Clock same frequency as sys_clk1 Divide by 2 PB1 Clock is 1/2 of sys_clk2 Divide by 3 PB1 Clock is 1/3 of sys_clk15 Divide by 16 PB1 Clock is 1/16 of sys_clk16 Divide by 17 PB1 Clock is 1/17 of sys_clk126 Divide by 127 PB1 Clock is 1/127 of sys_clk127 Divide by 128 PB1 Clock is 1/128 of sys_clk
PB1DIVCLR
Address 0x44000B34
Reset 0x00000000
Access read/write
Size 32-bit PB1DIVSET
Address 0x44000B38
Reset 0x00000000
Access read/write
Size 32-bit PB1DIVINV
Address 0x44000B3C
Reset 0x00000000
Access read/write
Size 32-bit PB2DIVPB2 CLOCK DIVISOR CONTROL REGISTER
Address 0x44000B40
Reset 0x00008800
Access read/write
Size 32-bit 3 fields
Field Bits What it does PBDIVON 15 Output Enable bit0 PB2 Output clock is disabled1 PB2 Output clock is enabled PBDIVRDY 11 PB2 Peripheral Clock Divisor Ready0 Indicates the PB clock divisor logic is currently switching values and the PB2DIV cannot be written.1 Indicates the PB clock divisor logic is not switching divisors and the PB2DIV may be written. PBDIV 6:0 PB2 Peripheral Clock Divisor Control value0 Divide by 1 PB2 Clock same frequency as sys_clk1 Divide by 2 PB2 Clock is 1/2 of sys_clk2 Divide by 3 PB2 Clock is 1/3 of sys_clk15 Divide by 16 PB2 Clock is 1/16 of sys_clk16 Divide by 17 PB2 Clock is 1/17 of sys_clk126 Divide by 127 PB2 Clock is 1/127 of sys_clk127 Divide by 128 PB2 Clock is 1/128 of sys_clk
PB2DIVCLR
Address 0x44000B44
Reset 0x00000000
Access read/write
Size 32-bit PB2DIVSET
Address 0x44000B48
Reset 0x00000000
Access read/write
Size 32-bit PB2DIVINV
Address 0x44000B4C
Reset 0x00000000
Access read/write
Size 32-bit PB3DIVPB3 CLOCK DIVISOR CONTROL REGISTER
Address 0x44000B50
Reset 0x00008809
Access read/write
Size 32-bit 3 fields
Field Bits What it does PBDIVON 15 Output Enable bit0 PB3 Output clock is disabled1 PB3 Output clock is enabled PBDIVRDY 11 PB3 Peripheral Clock Divisor Ready0 Indicates the PB clock divisor logic is currently switching values and the PB3DIV cannot be written.1 Indicates the PB clock divisor logic is not switching divisors and the PB3DIV may be written. PBDIV 6:0 PB3 Peripheral Clock Divisor Control value0 Divide by 1 PB3 Clock same frequency as sys_clk1 Divide by 2 PB3 Clock is 1/2 of sys_clk2 Divide by 3 PB3 Clock is 1/3 of sys_clk15 Divide by 16 PB3 Clock is 1/16 of sys_clk16 Divide by 17 PB3 Clock is 1/17 of sys_clk126 Divide by 127 PB3 Clock is 1/127 of sys_clk127 Divide by 128 PB3 Clock is 1/128 of sys_clk
PB3DIVCLR
Address 0x44000B54
Reset 0x00000000
Access read/write
Size 32-bit PB3DIVSET
Address 0x44000B58
Reset 0x00000000
Access read/write
Size 32-bit PB3DIVINV
Address 0x44000B5C
Reset 0x00000000
Access read/write
Size 32-bit SLEWCONSLEW RATE CONTROL FOR CLOCK SWITCHING REGISTER
Address 0x44000B60
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does SLWDLY 27:24 Number of clocks generated at each slew step for a clock switch0 1 clock will be generated at each slew step1 2 clocks will be generated at each slew step2 3 clocks will be generated at each slew step3 4 clocks will be generated at each slew step4 5 clocks will be generated at each slew step5 6 clocks will be generated at each slew step6 7 clocks will be generated at each slew step7 8 clocks will be generated at each slew step8 9 clocks will be generated at each slew step9 10 clocks will be generated at each slew step10 11 clocks will be generated at each slew step11 12 clocks will be generated at each slew step12 13 clocks will be generated at each slew step13 14 clocks will be generated at each slew step14 15 clocks will be generated at each slew step15 16 clocks will be generated at each slew step SYSDIV 19:16 PBx Peripheral Clock Divisor Control value0 Divide by 1- sys_clk_out same frequency as sys_clk source - Default1 Divide by 2- sys_clk_out is 1/2 of sys_clk source2 Divide by 3- sys_clk_out is 1/3 of sys_clk source3 Divide by 4- sys_clk_out is 1/4 of sys_clk source4 Divide by 5- sys_clk_out is 1/5 of sys_clk source5 Divide by 6- sys_clk_out is 1/6 of sys_clk source6 Divide by 7- sys_clk_out is 1/7 of sys_clk source7 Divide by 8- sys_clk_out is 1/8 of sys_clk source8 Divide by 9- sys_clk_out is 1/9 of sys_clk source9 Divide by 10- sys_clk_out is 1/10 of sys_clk source10 Divide by 11- sys_clk_out is 1/11 of sys_clk source11 Divide by 12- sys_clk_out is 1/12 of sys_clk source12 Divide by 13- sys_clk_out is 1/13 of sys_clk source13 Divide by 14- sys_clk_out is 1/14 of sys_clk source14 Divide by 15- sys_clk_out is 1/15 of sys_clk source15 Divide by 16- sys_clk_out is 1/16 of sys_clk source SLWDIV 10:8 Divisor steps used when doing slewed clock switches0 No Divisor used1 Divide by 2, then no divisor2 Divide by 4, then by 2, then no divisor3 Divide by 8, then by 4, then by 2, then no divisor4 Divide by 16, then by 8, then by 4, then by 2, then no divisor5 Divide by 32, then by 16, then by 8, then by 4, then by 2, then no divisor6 Divide by 64, then by 32, then by 16, then by 8, then by 4, then by 2, then no divisor7 Divide by 128, then by 64, then by 32, then by 16, then by 8, then by 4, then by 2, then no divisor UPEN 2 Clock slew enable for switching up to faster clocks0 Clock Slewing disabled1 Clock Slewing enabled on a clock switch OR exit from SLEEP DNEN 1 Clock slew enable for switching down to slower clocks0 Clock Slewing disabled1 Clock Slewing enabled on a clock switch BUSY 0 Clock Switch Slewing Active Status Bit - Read-Only0 Clock Switch has reached its final value1 Clock frequency is being actively Slewed
SLEWCONCLR
Address 0x44000B64
Reset 0x00000000
Access read/write
Size 32-bit SLEWCONSET
Address 0x44000B68
Reset 0x00000000
Access read/write
Size 32-bit SLEWCONINV
Address 0x44000B6C
Reset 0x00000000
Access read/write
Size 32-bit CLKSTATCLOCK STATUS REGISTER
Address 0x44000B70
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does SPLL3RDY 5 System PLL3 Ready Status value0 SPLL3 Output is not stable and not ready1 SPLL3 Output is stable and ready LPRCRDY 4 LPRC Ready Status value0 LPRC is not stable and not ready1 LPRC is stable and ready SOSCRDY 3 SOSC Ready Status value0 SOSC is not stable and not ready1 SOSC is stable and ready POSCRDY 2 Primary Oscillator Ready Status value0 POSC is not stable and not ready1 POSC is stable and ready SPLL1RDY 1 System PLL1 Ready Status value0 SPLL1 Primary Output is not stable and not ready1 SPLL1 Primary Output is stable and ready FRCRDY 0 FRC Ready Status value0 FRC is not stable and not ready1 FRC is stable and ready
CLKDIAGUSER CLK DIAGNOSTICS CONTROL REGISTER
Address 0x44000B90
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does SPLL3STOP 5 SPLL3 Clock Stop Control value0 SPLL3 clock source runs as normal1 SPLL3 clock source is stopped SPLL1STOP 4 SPLL1 Clock Stop Control value0 SPLL1 clock source runs as normal1 SPLL1 clock source is stopped LPRCSTOP 3 LPRC Clock Stop Control value0 LPRC clock source runs as normal1 LPRC clock source is stopped FRCSTOP 2 FRC Clock Stop Control value0 FRC clock source runs as normal1 FRC clock source is stopped SOSCSTOP 1 SOSC Clock Stop Control value0 SOSC clock source runs as normal1 SOSC clock source is stopped POSCSTOP 0 POSC Clock Stop Control value0 POSC clock source runs as normal1 POSC clock source is stopped NMICNT 31:16 NMI Counter value
BETA