The 43 registers of PMC (Power Management Controller), from 0x46800000, with their reset value and every field. The PIC32CX5112MTC128 has 2891 registers in 62 peripherals, one page each.
PMC Power Management Controller
PMC_SCERSystem Clock Enable Register
Address
0x46800000
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
Field
Bits
What it does
CPKEY
23:20
Coprocessor Clocks Enable Key
10 This field must be written to 0xA to validate CPBMCK and CPCK.
CPBMCK
17
Coprocessor Bus Master Clocks Enable
CPCK
16
Coprocessor (Second Processor) Clocks Enable
PCK3
11
Programmable Clock 3 Output Enable
PCK2
10
Programmable Clock 2 Output Enable
PCK1
9
Programmable Clock 1 Output Enable
PCK0
8
Programmable Clock 0 Output Enable
PMC_SCDRSystem Clock Disable Register
Address
0x46800004
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
Field
Bits
What it does
CPKEY
23:20
Coprocessor Clocks Enable Key
10 This field must be written to 0xA to validate CPBMCK and CPCK.
CPBMCK
17
Coprocessor Bus Master Clocks Disable
CPCK
16
Coprocessor (Second Processor) Clocks Disable
PCK3
11
Programmable Clock 3 Output Disable
PCK2
10
Programmable Clock 2 Output Disable
PCK1
9
Programmable Clock 1 Output Disable
PCK0
8
Programmable Clock 0 Output Disable
PMC_SCSRSystem Clock Status Register
Address
0x46800008
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
CPBMCK
17
Coprocessor Bus Master Clocks Status
CPCK
16
Coprocessor (Second Processor) Clocks Status
PCK3
11
Programmable Clock 3 Output Status
PCK2
10
Programmable Clock 2 Output Status
PCK1
9
Programmable Clock 1 Output Status
PCK0
8
Programmable Clock 0 Output Status
CPU_CLK1S
1
CPU_CLK Status for Core 1
CPU_CLK0S
0
CPU_CLK Status for Core 0
PMC_PLL_CTRL0PLL Control Register 0
Address
0x4680000C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
ENPLLO1
30
Enable PLL Clock Output 1 (PLLA only)
ENPLLO0
29
Enable PLL Clock Output 0
ENPLL
28
Enable PLL
PLLMS
27
PLL Multiplexer Select
DIVPMC1
19:12
Divider for PMC output 1 (PLLA only)
DIVPMC0
7:0
Divider for PMC output 0
ENLOCK
31
Enable PLL Lock
PMC_PLL_CTRL1PLL Control Register 1
Address
0x46800010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
MUL
15:0
Multiplier Factor Value for PLLA, B and C
PMC_PLL_CTRL2PLL Control Register 2
Address
0x46800014
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
FRACR
21:0
Fractional Loop Divider Setting
PMC_PLL_SSRPLL Spread Spectrum Register
Address
0x46800018
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
ENSPREAD
28
Spread Spectrum Enable
NSTEP
23:16
Spread Spectrum Number of Step
STEP
15:0
Spread Spectrum Step Size
PMC_PLL_ACRPLL Analog Control Register
Address
0x4680001C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
LOCK_THR
23:16
PLL Lock Threshold Value Selection
CONTROL
11:0
PLL Control Value Selection
LOOP_FILTER
31:24
PLL Loop Filter Selection
PMC_PLL_UPDTPLL Update Register
Address
0x46800020
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
STUPTIM
23:16
Start-up Time
UPDATE
8
PLL Setting Update (write-only)
ID
3:0
PLL ID
CKGR_MORMain Oscillator Register
Address
0x46800024
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
BMCKRST
27
Bad MCK0 Clock Reset Enable
XT32KFME
26
32.768 kHz Crystal Oscillator Frequency Monitoring Enable
CFDEN
25
Clock Failure Detector Enable
MOSCSEL
24
Main Clock Oscillator Selection
0 The main RC oscillator is selected.
1 The main crystal oscillator is selected.
KEY
23:16
Write Access Password
55 Writing any other value in this field aborts the write operation. Always reads as 0.
MOSCXTST
15:8
Main Crystal Oscillator Start-up Time
MOSCRCEN
3
Main RC Oscillator Enable
WAITMODE
2
Wait Mode Command (write-only)
MOSCXTBY
1
12 to 48 MHz Crystal Oscillator Bypass
MOSCXTEN
0
Main Crystal Oscillator Enable
CKGR_MCFRMain Clock Frequency Register
Address
0x46800028
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CCSS
24
Counter Clock Source Selection
RCMEAS
20
RC Oscillator Frequency Measure (write-only)
MAINFRDY
16
Main Clock Frequency Measure Ready
MAINF
15:0
Main Clock Frequency
PMC_CPU_CKRCPU Clock Register
Address
0x4680002C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
RATIO_MCK0DIV2
26
MCK0 Clock Frequency Division for MCK0DIV2 Clock
RATIO_MCK1DIV
25
MCK1 Clock Frequency Division for MCK1DIV Clock
RATIO_MCK0DIV
24
MCK0 Clock Frequency Division for MCK0DIV Clock
CPPRES
23:20
Coprocessor MCK1 Prescaler
0 Selected clock
1 Selected clock divided by 2
2 Selected clock divided by 3
3 Selected clock divided by 4
4 Selected clock divided by 5
5 Selected clock divided by 6
6 Selected clock divided by 7
7 Selected clock divided by 8
8 Selected clock divided by 9
9 Selected clock divided by 10
10 Selected clock divided by 11
11 Selected clock divided by 12
12 Selected clock divided by 13
13 Selected clock divided by 14
14 Selected clock divided by 15
15 Selected clock divided by 16
CPCSS
18:16
Coprocessor MCK1 Source Selection
0 MD_SLCK is selected
1 MAINCK is selected
2 MCK0 is selected
3 PLLACK1 is selected
4 PLLBCK is selected
5 PLLCCK is selected
PRES
6:4
Processor (CPU_CLK0) and Master Clock (MCK0) Prescaler
0 Selected clock
1 Selected clock divided by 2
2 Selected clock divided by 4
3 Selected clock divided by 8
4 Selected clock divided by 16
5 Selected clock divided by 32
6 Selected clock divided by 64
7 Selected clock divided by 3
CSS
1:0
Processor (CPU_CLK0) and Master Clock (MCK0) Source Selection