PIC32CZ1038CA70064 PWM1 Registers – 108 with their bits and fields

PWM_CLKPWM Clock Register

Address: 0x4005C000
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
PREB	27:24	CLKB Source Clock Selection `0` Peripheral clock `1` Peripheral clock/2 `2` Peripheral clock/4 `3` Peripheral clock/8 `4` Peripheral clock/16 `5` Peripheral clock/32 `6` Peripheral clock/64 `7` Peripheral clock/128 `8` Peripheral clock/256 `9` Peripheral clock/512 `10` Peripheral clock/1024
DIVB	23:16	CLKB Divide Factor `0` CLKB clock is turned off `1` CLKB clock is clock selected by PREB
PREA	11:8	CLKA Source Clock Selection `0` Peripheral clock `1` Peripheral clock/2 `2` Peripheral clock/4 `3` Peripheral clock/8 `4` Peripheral clock/16 `5` Peripheral clock/32 `6` Peripheral clock/64 `7` Peripheral clock/128 `8` Peripheral clock/256 `9` Peripheral clock/512 `10` Peripheral clock/1024
DIVA	7:0	CLKA Divide Factor `0` CLKA clock is turned off `1` CLKA clock is clock selected by PREA

PWM_ENAPWM Enable Register

Address: 0x4005C004
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CHID3	3	Channel ID
CHID2	2	Channel ID
CHID1	1	Channel ID
CHID0	0	Channel ID

PWM_DISPWM Disable Register

Address: 0x4005C008
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CHID3	3	Channel ID
CHID2	2	Channel ID
CHID1	1	Channel ID
CHID0	0	Channel ID

PWM_SRPWM Status Register

Address: 0x4005C00C
Reset: 0x00000000
Access: read only
Size: 32-bit

4 fields

Field	Bits	What it does
CHID3	3	Channel ID
CHID2	2	Channel ID
CHID1	1	Channel ID
CHID0	0	Channel ID

PWM_IER1PWM Interrupt Enable Register 1

Address: 0x4005C010
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
FCHID3	19	Fault Protection Trigger on Channel 3 Interrupt Enable
FCHID2	18	Fault Protection Trigger on Channel 2 Interrupt Enable
FCHID1	17	Fault Protection Trigger on Channel 1 Interrupt Enable
FCHID0	16	Fault Protection Trigger on Channel 0 Interrupt Enable
CHID3	3	Counter Event on Channel 3 Interrupt Enable
CHID2	2	Counter Event on Channel 2 Interrupt Enable
CHID1	1	Counter Event on Channel 1 Interrupt Enable
CHID0	0	Counter Event on Channel 0 Interrupt Enable

PWM_IDR1PWM Interrupt Disable Register 1

Address: 0x4005C014
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
FCHID3	19	Fault Protection Trigger on Channel 3 Interrupt Disable
FCHID2	18	Fault Protection Trigger on Channel 2 Interrupt Disable
FCHID1	17	Fault Protection Trigger on Channel 1 Interrupt Disable
FCHID0	16	Fault Protection Trigger on Channel 0 Interrupt Disable
CHID3	3	Counter Event on Channel 3 Interrupt Disable
CHID2	2	Counter Event on Channel 2 Interrupt Disable
CHID1	1	Counter Event on Channel 1 Interrupt Disable
CHID0	0	Counter Event on Channel 0 Interrupt Disable

PWM_IMR1PWM Interrupt Mask Register 1

Address: 0x4005C018
Reset: 0x00000000
Access: read only
Size: 32-bit

8 fields

Field	Bits	What it does
FCHID3	19	Fault Protection Trigger on Channel 3 Interrupt Mask
FCHID2	18	Fault Protection Trigger on Channel 2 Interrupt Mask
FCHID1	17	Fault Protection Trigger on Channel 1 Interrupt Mask
FCHID0	16	Fault Protection Trigger on Channel 0 Interrupt Mask
CHID3	3	Counter Event on Channel 3 Interrupt Mask
CHID2	2	Counter Event on Channel 2 Interrupt Mask
CHID1	1	Counter Event on Channel 1 Interrupt Mask
CHID0	0	Counter Event on Channel 0 Interrupt Mask

PWM_ISR1PWM Interrupt Status Register 1

Address: 0x4005C01C
Reset: 0x00000000
Access: read only
Size: 32-bit

8 fields

Field	Bits	What it does
FCHID3	19	Fault Protection Trigger on Channel 3
FCHID2	18	Fault Protection Trigger on Channel 2
FCHID1	17	Fault Protection Trigger on Channel 1
FCHID0	16	Fault Protection Trigger on Channel 0
CHID3	3	Counter Event on Channel 3
CHID2	2	Counter Event on Channel 2
CHID1	1	Counter Event on Channel 1
CHID0	0	Counter Event on Channel 0

PWM_SCMPWM Sync Channels Mode Register

Address: 0x4005C020
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
PTRCS	23:21	DMA Controller Transfer Request Comparison Selection
PTRM	20	DMA Controller Transfer Request Mode
UPDM	17:16	Synchronous Channels Update Mode `0` Manual write of double buffer registers and manual update of synchronous channels `1` Manual write of double buffer registers and automatic update of synchronous channels `2` Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels
SYNC3	3	Synchronous Channel 3
SYNC2	2	Synchronous Channel 2
SYNC1	1	Synchronous Channel 1
SYNC0	0	Synchronous Channel 0

PWM_DMARPWM DMA Register

Address: 0x4005C024
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
DMADUTY	23:0	Duty-Cycle Holding Register for DMA Access

PWM_SCUCPWM Sync Channels Update Control Register

Address: 0x4005C028
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
UPDULOCK	0	Synchronous Channels Update Unlock

PWM_SCUPPWM Sync Channels Update Period Register

Address: 0x4005C02C
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
UPRCNT	7:4	Update Period Counter
UPR	3:0	Update Period

PWM_SCUPUPDPWM Sync Channels Update Period Update Register

Address: 0x4005C030
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
UPRUPD	3:0	Update Period Update

PWM_IER2PWM Interrupt Enable Register 2

Address: 0x4005C034
Reset: 0x00000000
Access: write only
Size: 32-bit

18 fields

Field	Bits	What it does
CMPU7	23	Comparison 7 Update Interrupt Enable
CMPU6	22	Comparison 6 Update Interrupt Enable
CMPU5	21	Comparison 5 Update Interrupt Enable
CMPU4	20	Comparison 4 Update Interrupt Enable
CMPU3	19	Comparison 3 Update Interrupt Enable
CMPU2	18	Comparison 2 Update Interrupt Enable
CMPU1	17	Comparison 1 Update Interrupt Enable
CMPU0	16	Comparison 0 Update Interrupt Enable
CMPM7	15	Comparison 7 Match Interrupt Enable
CMPM6	14	Comparison 6 Match Interrupt Enable
CMPM5	13	Comparison 5 Match Interrupt Enable
CMPM4	12	Comparison 4 Match Interrupt Enable
CMPM3	11	Comparison 3 Match Interrupt Enable
CMPM2	10	Comparison 2 Match Interrupt Enable
CMPM1	9	Comparison 1 Match Interrupt Enable
CMPM0	8	Comparison 0 Match Interrupt Enable
UNRE	3	Synchronous Channels Update Underrun Error Interrupt Enable
WRDY	0	Write Ready for Synchronous Channels Update Interrupt Enable

PWM_IDR2PWM Interrupt Disable Register 2

Address: 0x4005C038
Reset: 0x00000000
Access: write only
Size: 32-bit

18 fields

Field	Bits	What it does
CMPU7	23	Comparison 7 Update Interrupt Disable
CMPU6	22	Comparison 6 Update Interrupt Disable
CMPU5	21	Comparison 5 Update Interrupt Disable
CMPU4	20	Comparison 4 Update Interrupt Disable
CMPU3	19	Comparison 3 Update Interrupt Disable
CMPU2	18	Comparison 2 Update Interrupt Disable
CMPU1	17	Comparison 1 Update Interrupt Disable
CMPU0	16	Comparison 0 Update Interrupt Disable
CMPM7	15	Comparison 7 Match Interrupt Disable
CMPM6	14	Comparison 6 Match Interrupt Disable
CMPM5	13	Comparison 5 Match Interrupt Disable
CMPM4	12	Comparison 4 Match Interrupt Disable
CMPM3	11	Comparison 3 Match Interrupt Disable
CMPM2	10	Comparison 2 Match Interrupt Disable
CMPM1	9	Comparison 1 Match Interrupt Disable
CMPM0	8	Comparison 0 Match Interrupt Disable
UNRE	3	Synchronous Channels Update Underrun Error Interrupt Disable
WRDY	0	Write Ready for Synchronous Channels Update Interrupt Disable

PWM_IMR2PWM Interrupt Mask Register 2

Address: 0x4005C03C
Reset: 0x00000000
Access: read only
Size: 32-bit

18 fields

Field	Bits	What it does
CMPU7	23	Comparison 7 Update Interrupt Mask
CMPU6	22	Comparison 6 Update Interrupt Mask
CMPU5	21	Comparison 5 Update Interrupt Mask
CMPU4	20	Comparison 4 Update Interrupt Mask
CMPU3	19	Comparison 3 Update Interrupt Mask
CMPU2	18	Comparison 2 Update Interrupt Mask
CMPU1	17	Comparison 1 Update Interrupt Mask
CMPU0	16	Comparison 0 Update Interrupt Mask
CMPM7	15	Comparison 7 Match Interrupt Mask
CMPM6	14	Comparison 6 Match Interrupt Mask
CMPM5	13	Comparison 5 Match Interrupt Mask
CMPM4	12	Comparison 4 Match Interrupt Mask
CMPM3	11	Comparison 3 Match Interrupt Mask
CMPM2	10	Comparison 2 Match Interrupt Mask
CMPM1	9	Comparison 1 Match Interrupt Mask
CMPM0	8	Comparison 0 Match Interrupt Mask
UNRE	3	Synchronous Channels Update Underrun Error Interrupt Mask
WRDY	0	Write Ready for Synchronous Channels Update Interrupt Mask

PWM_ISR2PWM Interrupt Status Register 2

Address: 0x4005C040
Reset: 0x00000000
Access: read only
Size: 32-bit

18 fields

Field	Bits	What it does
CMPU7	23	Comparison 7 Update
CMPU6	22	Comparison 6 Update
CMPU5	21	Comparison 5 Update
CMPU4	20	Comparison 4 Update
CMPU3	19	Comparison 3 Update
CMPU2	18	Comparison 2 Update
CMPU1	17	Comparison 1 Update
CMPU0	16	Comparison 0 Update
CMPM7	15	Comparison 7 Match
CMPM6	14	Comparison 6 Match
CMPM5	13	Comparison 5 Match
CMPM4	12	Comparison 4 Match
CMPM3	11	Comparison 3 Match
CMPM2	10	Comparison 2 Match
CMPM1	9	Comparison 1 Match
CMPM0	8	Comparison 0 Match
UNRE	3	Synchronous Channels Update Underrun Error
WRDY	0	Write Ready for Synchronous Channels Update

PWM_OOVPWM Output Override Value Register

Address: 0x4005C044
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
OOVL3	19	Output Override Value for PWML output of the channel 3
OOVL2	18	Output Override Value for PWML output of the channel 2
OOVL1	17	Output Override Value for PWML output of the channel 1
OOVL0	16	Output Override Value for PWML output of the channel 0
OOVH3	3	Output Override Value for PWMH output of the channel 3
OOVH2	2	Output Override Value for PWMH output of the channel 2
OOVH1	1	Output Override Value for PWMH output of the channel 1
OOVH0	0	Output Override Value for PWMH output of the channel 0

PWM_OSPWM Output Selection Register

Address: 0x4005C048
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
OSL3	19	Output Selection for PWML output of the channel 3
OSL2	18	Output Selection for PWML output of the channel 2
OSL1	17	Output Selection for PWML output of the channel 1
OSL0	16	Output Selection for PWML output of the channel 0
OSH3	3	Output Selection for PWMH output of the channel 3
OSH2	2	Output Selection for PWMH output of the channel 2
OSH1	1	Output Selection for PWMH output of the channel 1
OSH0	0	Output Selection for PWMH output of the channel 0

PWM_OSSPWM Output Selection Set Register

Address: 0x4005C04C
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
OSSL3	19	Output Selection Set for PWML output of the channel 3
OSSL2	18	Output Selection Set for PWML output of the channel 2
OSSL1	17	Output Selection Set for PWML output of the channel 1
OSSL0	16	Output Selection Set for PWML output of the channel 0
OSSH3	3	Output Selection Set for PWMH output of the channel 3
OSSH2	2	Output Selection Set for PWMH output of the channel 2
OSSH1	1	Output Selection Set for PWMH output of the channel 1
OSSH0	0	Output Selection Set for PWMH output of the channel 0

PWM_OSCPWM Output Selection Clear Register

Address: 0x4005C050
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
OSCL3	19	Output Selection Clear for PWML output of the channel 3
OSCL2	18	Output Selection Clear for PWML output of the channel 2
OSCL1	17	Output Selection Clear for PWML output of the channel 1
OSCL0	16	Output Selection Clear for PWML output of the channel 0
OSCH3	3	Output Selection Clear for PWMH output of the channel 3
OSCH2	2	Output Selection Clear for PWMH output of the channel 2
OSCH1	1	Output Selection Clear for PWMH output of the channel 1
OSCH0	0	Output Selection Clear for PWMH output of the channel 0

PWM_OSSUPDPWM Output Selection Set Update Register

Address: 0x4005C054
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
OSSUPL3	19	Output Selection Set for PWML output of the channel 3
OSSUPL2	18	Output Selection Set for PWML output of the channel 2
OSSUPL1	17	Output Selection Set for PWML output of the channel 1
OSSUPL0	16	Output Selection Set for PWML output of the channel 0
OSSUPH3	3	Output Selection Set for PWMH output of the channel 3
OSSUPH2	2	Output Selection Set for PWMH output of the channel 2
OSSUPH1	1	Output Selection Set for PWMH output of the channel 1
OSSUPH0	0	Output Selection Set for PWMH output of the channel 0

PWM_OSCUPDPWM Output Selection Clear Update Register

Address: 0x4005C058
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
OSCUPL3	19	Output Selection Clear for PWML output of the channel 3
OSCUPL2	18	Output Selection Clear for PWML output of the channel 2
OSCUPL1	17	Output Selection Clear for PWML output of the channel 1
OSCUPL0	16	Output Selection Clear for PWML output of the channel 0
OSCUPH3	3	Output Selection Clear for PWMH output of the channel 3
OSCUPH2	2	Output Selection Clear for PWMH output of the channel 2
OSCUPH1	1	Output Selection Clear for PWMH output of the channel 1
OSCUPH0	0	Output Selection Clear for PWMH output of the channel 0

PWM_FMRPWM Fault Mode Register

Address: 0x4005C05C
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FFIL	23:16	Fault Filtering
FMOD	15:8	Fault Activation Mode
FPOL	7:0	Fault Polarity

PWM_FSRPWM Fault Status Register

Address: 0x4005C060
Reset: 0x00000000
Access: read only
Size: 32-bit

2 fields

Field	Bits	What it does
FS	15:8	Fault Status
FIV	7:0	Fault Input Value

PWM_FCRPWM Fault Clear Register

Address: 0x4005C064
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
FCLR	7:0	Fault Clear

PWM_FPV1PWM Fault Protection Value Register 1

Address: 0x4005C068
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
FPVL3	19	Fault Protection Value for PWML output on channel 3
FPVL2	18	Fault Protection Value for PWML output on channel 2
FPVL1	17	Fault Protection Value for PWML output on channel 1
FPVL0	16	Fault Protection Value for PWML output on channel 0
FPVH3	3	Fault Protection Value for PWMH output on channel 3
FPVH2	2	Fault Protection Value for PWMH output on channel 2
FPVH1	1	Fault Protection Value for PWMH output on channel 1
FPVH0	0	Fault Protection Value for PWMH output on channel 0

PWM_FPEPWM Fault Protection Enable Register

Address: 0x4005C06C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
FPE2	23:16	Fault Protection Enable for channel 2
FPE1	15:8	Fault Protection Enable for channel 1
FPE0	7:0	Fault Protection Enable for channel 0
FPE3	31:24	Fault Protection Enable for channel 3

PWM_ELMR0PWM Event Line 0 Mode Register 0

Address: 0x4005C07C
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
CSEL7	7	Comparison 7 Selection
CSEL6	6	Comparison 6 Selection
CSEL5	5	Comparison 5 Selection
CSEL4	4	Comparison 4 Selection
CSEL3	3	Comparison 3 Selection
CSEL2	2	Comparison 2 Selection
CSEL1	1	Comparison 1 Selection
CSEL0	0	Comparison 0 Selection

PWM_ELMR1PWM Event Line 0 Mode Register 0

Address: 0x4005C080
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
CSEL7	7	Comparison 7 Selection
CSEL6	6	Comparison 6 Selection
CSEL5	5	Comparison 5 Selection
CSEL4	4	Comparison 4 Selection
CSEL3	3	Comparison 3 Selection
CSEL2	2	Comparison 2 Selection
CSEL1	1	Comparison 1 Selection
CSEL0	0	Comparison 0 Selection

PWM_SSPRPWM Spread Spectrum Register

Address: 0x4005C0A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
SPRDM	24	Spread Spectrum Counter Mode
SPRD	23:0	Spread Spectrum Limit Value

PWM_SSPUPPWM Spread Spectrum Update Register

Address: 0x4005C0A4
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
SPRDUP	23:0	Spread Spectrum Limit Value Update

PWM_SMMRPWM Stepper Motor Mode Register

Address: 0x4005C0B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
DOWN1	17	DOWN Count
DOWN0	16	DOWN Count
GCEN1	1	Gray Count ENable
GCEN0	0	Gray Count ENable

PWM_FPV2PWM Fault Protection Value 2 Register

Address: 0x4005C0C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
FPZL3	19	Fault Protection to Hi-Z for PWML output on channel 3
FPZL2	18	Fault Protection to Hi-Z for PWML output on channel 2
FPZL1	17	Fault Protection to Hi-Z for PWML output on channel 1
FPZL0	16	Fault Protection to Hi-Z for PWML output on channel 0
FPZH3	3	Fault Protection to Hi-Z for PWMH output on channel 3
FPZH2	2	Fault Protection to Hi-Z for PWMH output on channel 2
FPZH1	1	Fault Protection to Hi-Z for PWMH output on channel 1
FPZH0	0	Fault Protection to Hi-Z for PWMH output on channel 0

PWM_WPCRPWM Write Protection Control Register

Address: 0x4005C0E4
Reset: 0x00000000
Access: write only
Size: 32-bit

8 fields

Field	Bits	What it does
WPRG5	7	Write Protection Register Group 5
WPRG4	6	Write Protection Register Group 4
WPRG3	5	Write Protection Register Group 3
WPRG2	4	Write Protection Register Group 2
WPRG1	3	Write Protection Register Group 1
WPRG0	2	Write Protection Register Group 0
WPCMD	1:0	Write Protection Command `0` Disables the software write protection of the register groups of which the bit WPRGx is at '1'. `1` Enables the software write protection of the register groups of which the bit WPRGx is at '1'. `2` Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO i
WPKEY	31:8	Write Protection Key `5265229` Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0

PWM_WPSRPWM Write Protection Status Register

Address: 0x4005C0E8
Reset: 0x00000000
Access: read only
Size: 32-bit

14 fields

Field	Bits	What it does
WPHWS5	13	Write Protect HW Status
WPHWS4	12	Write Protect HW Status
WPHWS3	11	Write Protect HW Status
WPHWS2	10	Write Protect HW Status
WPHWS1	9	Write Protect HW Status
WPHWS0	8	Write Protect HW Status
WPVS	7	Write Protect Violation Status
WPSWS5	5	Write Protect SW Status
WPSWS4	4	Write Protect SW Status
WPSWS3	3	Write Protect SW Status
WPSWS2	2	Write Protect SW Status
WPSWS1	1	Write Protect SW Status
WPSWS0	0	Write Protect SW Status
WPVSRC	31:16	Write Protect Violation Source

PWM_CMPV0PWM Comparison 0 Value Register

Address: 0x4005C130
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CVM	24	Comparison x Value Mode `0` Compare when counter is incrementing `1` Compare when counter is decrementing
CV	23:0	Comparison x Value

PWM_CMPVUPD0PWM Comparison 0 Value Update Register

Address: 0x4005C134
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CVMUPD	24	Comparison x Value Mode Update
CVUPD	23:0	Comparison x Value Update

PWM_CMPM0PWM Comparison 0 Mode Register

Address: 0x4005C138
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CUPRCNT	23:20	Comparison x Update Period Counter
CUPR	19:16	Comparison x Update Period
CPRCNT	15:12	Comparison x Period Counter
CPR	11:8	Comparison x Period
CTR	7:4	Comparison x Trigger
CEN	0	Comparison x Enable

PWM_CMPMUPD0PWM Comparison 0 Mode Update Register

Address: 0x4005C13C
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CUPRUPD	19:16	Comparison x Update Period Update
CPRUPD	11:8	Comparison x Period Update
CTRUPD	7:4	Comparison x Trigger Update
CENUPD	0	Comparison x Enable Update

PWM_CMPV1PWM Comparison 0 Value Register

Address: 0x4005C140
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CVM	24	Comparison x Value Mode `0` Compare when counter is incrementing `1` Compare when counter is decrementing
CV	23:0	Comparison x Value

PWM_CMPVUPD1PWM Comparison 0 Value Update Register

Address: 0x4005C144
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CVMUPD	24	Comparison x Value Mode Update
CVUPD	23:0	Comparison x Value Update

PWM_CMPM1PWM Comparison 0 Mode Register

Address: 0x4005C148
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CUPRCNT	23:20	Comparison x Update Period Counter
CUPR	19:16	Comparison x Update Period
CPRCNT	15:12	Comparison x Period Counter
CPR	11:8	Comparison x Period
CTR	7:4	Comparison x Trigger
CEN	0	Comparison x Enable

PWM_CMPMUPD1PWM Comparison 0 Mode Update Register

Address: 0x4005C14C
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CUPRUPD	19:16	Comparison x Update Period Update
CPRUPD	11:8	Comparison x Period Update
CTRUPD	7:4	Comparison x Trigger Update
CENUPD	0	Comparison x Enable Update

PWM_CMPV2PWM Comparison 0 Value Register

Address: 0x4005C150
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CVM	24	Comparison x Value Mode `0` Compare when counter is incrementing `1` Compare when counter is decrementing
CV	23:0	Comparison x Value

PWM_CMPVUPD2PWM Comparison 0 Value Update Register

Address: 0x4005C154
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CVMUPD	24	Comparison x Value Mode Update
CVUPD	23:0	Comparison x Value Update

PWM_CMPM2PWM Comparison 0 Mode Register

Address: 0x4005C158
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CUPRCNT	23:20	Comparison x Update Period Counter
CUPR	19:16	Comparison x Update Period
CPRCNT	15:12	Comparison x Period Counter
CPR	11:8	Comparison x Period
CTR	7:4	Comparison x Trigger
CEN	0	Comparison x Enable

PWM_CMPMUPD2PWM Comparison 0 Mode Update Register

Address: 0x4005C15C
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CUPRUPD	19:16	Comparison x Update Period Update
CPRUPD	11:8	Comparison x Period Update
CTRUPD	7:4	Comparison x Trigger Update
CENUPD	0	Comparison x Enable Update

PWM_CMPV3PWM Comparison 0 Value Register

Address: 0x4005C160
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CVM	24	Comparison x Value Mode `0` Compare when counter is incrementing `1` Compare when counter is decrementing
CV	23:0	Comparison x Value

PWM_CMPVUPD3PWM Comparison 0 Value Update Register

Address: 0x4005C164
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CVMUPD	24	Comparison x Value Mode Update
CVUPD	23:0	Comparison x Value Update

PWM_CMPM3PWM Comparison 0 Mode Register

Address: 0x4005C168
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CUPRCNT	23:20	Comparison x Update Period Counter
CUPR	19:16	Comparison x Update Period
CPRCNT	15:12	Comparison x Period Counter
CPR	11:8	Comparison x Period
CTR	7:4	Comparison x Trigger
CEN	0	Comparison x Enable

PWM_CMPMUPD3PWM Comparison 0 Mode Update Register

Address: 0x4005C16C
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CUPRUPD	19:16	Comparison x Update Period Update
CPRUPD	11:8	Comparison x Period Update
CTRUPD	7:4	Comparison x Trigger Update
CENUPD	0	Comparison x Enable Update

PWM_CMPV4PWM Comparison 0 Value Register

Address: 0x4005C170
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CVM	24	Comparison x Value Mode `0` Compare when counter is incrementing `1` Compare when counter is decrementing
CV	23:0	Comparison x Value

PWM_CMPVUPD4PWM Comparison 0 Value Update Register

Address: 0x4005C174
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CVMUPD	24	Comparison x Value Mode Update
CVUPD	23:0	Comparison x Value Update

PWM_CMPM4PWM Comparison 0 Mode Register

Address: 0x4005C178
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CUPRCNT	23:20	Comparison x Update Period Counter
CUPR	19:16	Comparison x Update Period
CPRCNT	15:12	Comparison x Period Counter
CPR	11:8	Comparison x Period
CTR	7:4	Comparison x Trigger
CEN	0	Comparison x Enable

PWM_CMPMUPD4PWM Comparison 0 Mode Update Register

Address: 0x4005C17C
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CUPRUPD	19:16	Comparison x Update Period Update
CPRUPD	11:8	Comparison x Period Update
CTRUPD	7:4	Comparison x Trigger Update
CENUPD	0	Comparison x Enable Update

PWM_CMPV5PWM Comparison 0 Value Register

Address: 0x4005C180
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CVM	24	Comparison x Value Mode `0` Compare when counter is incrementing `1` Compare when counter is decrementing
CV	23:0	Comparison x Value

PWM_CMPVUPD5PWM Comparison 0 Value Update Register

Address: 0x4005C184
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CVMUPD	24	Comparison x Value Mode Update
CVUPD	23:0	Comparison x Value Update

PWM_CMPM5PWM Comparison 0 Mode Register

Address: 0x4005C188
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CUPRCNT	23:20	Comparison x Update Period Counter
CUPR	19:16	Comparison x Update Period
CPRCNT	15:12	Comparison x Period Counter
CPR	11:8	Comparison x Period
CTR	7:4	Comparison x Trigger
CEN	0	Comparison x Enable

PWM_CMPMUPD5PWM Comparison 0 Mode Update Register

Address: 0x4005C18C
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CUPRUPD	19:16	Comparison x Update Period Update
CPRUPD	11:8	Comparison x Period Update
CTRUPD	7:4	Comparison x Trigger Update
CENUPD	0	Comparison x Enable Update

PWM_CMPV6PWM Comparison 0 Value Register

Address: 0x4005C190
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CVM	24	Comparison x Value Mode `0` Compare when counter is incrementing `1` Compare when counter is decrementing
CV	23:0	Comparison x Value

PWM_CMPVUPD6PWM Comparison 0 Value Update Register

Address: 0x4005C194
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CVMUPD	24	Comparison x Value Mode Update
CVUPD	23:0	Comparison x Value Update

PWM_CMPM6PWM Comparison 0 Mode Register

Address: 0x4005C198
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CUPRCNT	23:20	Comparison x Update Period Counter
CUPR	19:16	Comparison x Update Period
CPRCNT	15:12	Comparison x Period Counter
CPR	11:8	Comparison x Period
CTR	7:4	Comparison x Trigger
CEN	0	Comparison x Enable

PWM_CMPMUPD6PWM Comparison 0 Mode Update Register

Address: 0x4005C19C
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CUPRUPD	19:16	Comparison x Update Period Update
CPRUPD	11:8	Comparison x Period Update
CTRUPD	7:4	Comparison x Trigger Update
CENUPD	0	Comparison x Enable Update

PWM_CMPV7PWM Comparison 0 Value Register

Address: 0x4005C1A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CVM	24	Comparison x Value Mode `0` Compare when counter is incrementing `1` Compare when counter is decrementing
CV	23:0	Comparison x Value

PWM_CMPVUPD7PWM Comparison 0 Value Update Register

Address: 0x4005C1A4
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CVMUPD	24	Comparison x Value Mode Update
CVUPD	23:0	Comparison x Value Update

PWM_CMPM7PWM Comparison 0 Mode Register

Address: 0x4005C1A8
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
CUPRCNT	23:20	Comparison x Update Period Counter
CUPR	19:16	Comparison x Update Period
CPRCNT	15:12	Comparison x Period Counter
CPR	11:8	Comparison x Period
CTR	7:4	Comparison x Trigger
CEN	0	Comparison x Enable

PWM_CMPMUPD7PWM Comparison 0 Mode Update Register

Address: 0x4005C1AC
Reset: 0x00000000
Access: write only
Size: 32-bit

4 fields

Field	Bits	What it does
CUPRUPD	19:16	Comparison x Update Period Update
CPRUPD	11:8	Comparison x Period Update
CTRUPD	7:4	Comparison x Trigger Update
CENUPD	0	Comparison x Enable Update

PWM_CH_NUM0.PWM_CMRPWM Channel Mode Register

Address: 0x4005C200
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
PPM	19	Push-Pull Mode
DTLI	18	Dead-Time PWMLx Output Inverted
DTHI	17	Dead-Time PWMHx Output Inverted
DTE	16	Dead-Time Generator Enable
TCTS	13	Timer Counter Trigger Selection
DPOLI	12	Disabled Polarity Inverted
UPDS	11	Update Selection `0` At the next end of PWM period `1` At the next end of Half PWM period
CES	10	Counter Event Selection `0` At the end of PWM period `1` At half of PWM period AND at the end of PWM period
CPOL	9	Channel Polarity `0` Waveform starts at low level `1` Waveform starts at high level
CALG	8	Channel Alignment `0` Left aligned `1` Center aligned
CPRE	3:0	Channel Pre-scaler `0` Peripheral clock `1` Peripheral clock/2 `2` Peripheral clock/4 `3` Peripheral clock/8 `4` Peripheral clock/16 `5` Peripheral clock/32 `6` Peripheral clock/64 `7` Peripheral clock/128 `8` Peripheral clock/256 `9` Peripheral clock/512 `10` Peripheral clock/1024 `11` Clock A `12` Clock B

PWM_CH_NUM0.PWM_CDTYPWM Channel Duty Cycle Register

Address: 0x4005C204
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CDTY	23:0	Channel Duty-Cycle

PWM_CH_NUM0.PWM_CDTYUPDPWM Channel Duty Cycle Update Register

Address: 0x4005C208
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CDTYUPD	23:0	Channel Duty-Cycle Update

PWM_CH_NUM0.PWM_CPRDPWM Channel Period Register

Address: 0x4005C20C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CPRD	23:0	Channel Period

PWM_CH_NUM0.PWM_CPRDUPDPWM Channel Period Update Register

Address: 0x4005C210
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CPRDUPD	23:0	Channel Period Update

PWM_CH_NUM0.PWM_CCNTPWM Channel Counter Register

Address: 0x4005C214
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CNT	23:0	Channel Counter Register

PWM_CH_NUM0.PWM_DTPWM Channel Dead Time Register

Address: 0x4005C218
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DTH	15:0	Dead-Time Value for PWMHx Output
DTL	31:16	Dead-Time Value for PWMLx Output

PWM_CH_NUM0.PWM_DTUPDPWM Channel Dead Time Update Register

Address: 0x4005C21C
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
DTHUPD	15:0	Dead-Time Value Update for PWMHx Output
DTLUPD	31:16	Dead-Time Value Update for PWMLx Output

PWM_CH_NUM1.PWM_CMRPWM Channel Mode Register

Address: 0x4005C220
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
PPM	19	Push-Pull Mode
DTLI	18	Dead-Time PWMLx Output Inverted
DTHI	17	Dead-Time PWMHx Output Inverted
DTE	16	Dead-Time Generator Enable
TCTS	13	Timer Counter Trigger Selection
DPOLI	12	Disabled Polarity Inverted
UPDS	11	Update Selection `0` At the next end of PWM period `1` At the next end of Half PWM period
CES	10	Counter Event Selection `0` At the end of PWM period `1` At half of PWM period AND at the end of PWM period
CPOL	9	Channel Polarity `0` Waveform starts at low level `1` Waveform starts at high level
CALG	8	Channel Alignment `0` Left aligned `1` Center aligned
CPRE	3:0	Channel Pre-scaler `0` Peripheral clock `1` Peripheral clock/2 `2` Peripheral clock/4 `3` Peripheral clock/8 `4` Peripheral clock/16 `5` Peripheral clock/32 `6` Peripheral clock/64 `7` Peripheral clock/128 `8` Peripheral clock/256 `9` Peripheral clock/512 `10` Peripheral clock/1024 `11` Clock A `12` Clock B

PWM_CH_NUM1.PWM_CDTYPWM Channel Duty Cycle Register

Address: 0x4005C224
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CDTY	23:0	Channel Duty-Cycle

PWM_CH_NUM1.PWM_CDTYUPDPWM Channel Duty Cycle Update Register

Address: 0x4005C228
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CDTYUPD	23:0	Channel Duty-Cycle Update

PWM_CH_NUM1.PWM_CPRDPWM Channel Period Register

Address: 0x4005C22C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CPRD	23:0	Channel Period

PWM_CH_NUM1.PWM_CPRDUPDPWM Channel Period Update Register

Address: 0x4005C230
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CPRDUPD	23:0	Channel Period Update

PWM_CH_NUM1.PWM_CCNTPWM Channel Counter Register

Address: 0x4005C234
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CNT	23:0	Channel Counter Register

PWM_CH_NUM1.PWM_DTPWM Channel Dead Time Register

Address: 0x4005C238
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DTH	15:0	Dead-Time Value for PWMHx Output
DTL	31:16	Dead-Time Value for PWMLx Output

PWM_CH_NUM1.PWM_DTUPDPWM Channel Dead Time Update Register

Address: 0x4005C23C
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
DTHUPD	15:0	Dead-Time Value Update for PWMHx Output
DTLUPD	31:16	Dead-Time Value Update for PWMLx Output

PWM_CH_NUM2.PWM_CMRPWM Channel Mode Register

Address: 0x4005C240
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
PPM	19	Push-Pull Mode
DTLI	18	Dead-Time PWMLx Output Inverted
DTHI	17	Dead-Time PWMHx Output Inverted
DTE	16	Dead-Time Generator Enable
TCTS	13	Timer Counter Trigger Selection
DPOLI	12	Disabled Polarity Inverted
UPDS	11	Update Selection `0` At the next end of PWM period `1` At the next end of Half PWM period
CES	10	Counter Event Selection `0` At the end of PWM period `1` At half of PWM period AND at the end of PWM period
CPOL	9	Channel Polarity `0` Waveform starts at low level `1` Waveform starts at high level
CALG	8	Channel Alignment `0` Left aligned `1` Center aligned
CPRE	3:0	Channel Pre-scaler `0` Peripheral clock `1` Peripheral clock/2 `2` Peripheral clock/4 `3` Peripheral clock/8 `4` Peripheral clock/16 `5` Peripheral clock/32 `6` Peripheral clock/64 `7` Peripheral clock/128 `8` Peripheral clock/256 `9` Peripheral clock/512 `10` Peripheral clock/1024 `11` Clock A `12` Clock B

PWM_CH_NUM2.PWM_CDTYPWM Channel Duty Cycle Register

Address: 0x4005C244
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CDTY	23:0	Channel Duty-Cycle

PWM_CH_NUM2.PWM_CDTYUPDPWM Channel Duty Cycle Update Register

Address: 0x4005C248
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CDTYUPD	23:0	Channel Duty-Cycle Update

PWM_CH_NUM2.PWM_CPRDPWM Channel Period Register

Address: 0x4005C24C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CPRD	23:0	Channel Period

PWM_CH_NUM2.PWM_CPRDUPDPWM Channel Period Update Register

Address: 0x4005C250
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CPRDUPD	23:0	Channel Period Update

PWM_CH_NUM2.PWM_CCNTPWM Channel Counter Register

Address: 0x4005C254
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CNT	23:0	Channel Counter Register

PWM_CH_NUM2.PWM_DTPWM Channel Dead Time Register

Address: 0x4005C258
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DTH	15:0	Dead-Time Value for PWMHx Output
DTL	31:16	Dead-Time Value for PWMLx Output

PWM_CH_NUM2.PWM_DTUPDPWM Channel Dead Time Update Register

Address: 0x4005C25C
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
DTHUPD	15:0	Dead-Time Value Update for PWMHx Output
DTLUPD	31:16	Dead-Time Value Update for PWMLx Output

PWM_CH_NUM3.PWM_CMRPWM Channel Mode Register

Address: 0x4005C260
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
PPM	19	Push-Pull Mode
DTLI	18	Dead-Time PWMLx Output Inverted
DTHI	17	Dead-Time PWMHx Output Inverted
DTE	16	Dead-Time Generator Enable
TCTS	13	Timer Counter Trigger Selection
DPOLI	12	Disabled Polarity Inverted
UPDS	11	Update Selection `0` At the next end of PWM period `1` At the next end of Half PWM period
CES	10	Counter Event Selection `0` At the end of PWM period `1` At half of PWM period AND at the end of PWM period
CPOL	9	Channel Polarity `0` Waveform starts at low level `1` Waveform starts at high level
CALG	8	Channel Alignment `0` Left aligned `1` Center aligned
CPRE	3:0	Channel Pre-scaler `0` Peripheral clock `1` Peripheral clock/2 `2` Peripheral clock/4 `3` Peripheral clock/8 `4` Peripheral clock/16 `5` Peripheral clock/32 `6` Peripheral clock/64 `7` Peripheral clock/128 `8` Peripheral clock/256 `9` Peripheral clock/512 `10` Peripheral clock/1024 `11` Clock A `12` Clock B

PWM_CH_NUM3.PWM_CDTYPWM Channel Duty Cycle Register

Address: 0x4005C264
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CDTY	23:0	Channel Duty-Cycle

PWM_CH_NUM3.PWM_CDTYUPDPWM Channel Duty Cycle Update Register

Address: 0x4005C268
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CDTYUPD	23:0	Channel Duty-Cycle Update

PWM_CH_NUM3.PWM_CPRDPWM Channel Period Register

Address: 0x4005C26C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CPRD	23:0	Channel Period

PWM_CH_NUM3.PWM_CPRDUPDPWM Channel Period Update Register

Address: 0x4005C270
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CPRDUPD	23:0	Channel Period Update

PWM_CH_NUM3.PWM_CCNTPWM Channel Counter Register

Address: 0x4005C274
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CNT	23:0	Channel Counter Register

PWM_CH_NUM3.PWM_DTPWM Channel Dead Time Register

Address: 0x4005C278
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DTH	15:0	Dead-Time Value for PWMHx Output
DTL	31:16	Dead-Time Value for PWMLx Output

PWM_CH_NUM3.PWM_DTUPDPWM Channel Dead Time Update Register

Address: 0x4005C27C
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
DTHUPD	15:0	Dead-Time Value Update for PWMHx Output
DTLUPD	31:16	Dead-Time Value Update for PWMLx Output

PWM_CMUPD0PWM Channel Mode Update Register (ch_num = 0)

Address: 0x4005C400
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CPOLINVUP	13	Channel Polarity Inversion Update
CPOLUP	9	Channel Polarity Update

PWM_CMUPD1PWM Channel Mode Update Register (ch_num = 1)

Address: 0x4005C420
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CPOLINVUP	13	Channel Polarity Inversion Update
CPOLUP	9	Channel Polarity Update

PWM_ETRG1PWM External Trigger Register (trg_num = 1)

Address: 0x4005C42C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TRGSRC	30	Trigger Source
TRGFILT	29	Filtered input
TRGEDGE	28	Edge Selection `0` TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 `1` TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
TRGMODE	25:24	External Trigger Mode `0` External trigger is not enabled. `1` External PWM Reset Mode `2` External PWM Start Mode `3` Cycle-by-cycle Duty Mode
MAXCNT	23:0	Maximum Counter value
RFEN	31	Recoverable Fault Enable

PWM_LEBR1PWM Leading-Edge Blanking Register (trg_num = 1)

Address: 0x4005C430
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
PWMHREN	19	PWMH Rising Edge Enable
PWMHFEN	18	PWMH Falling Edge Enable
PWMLREN	17	PWML Rising Edge Enable
PWMLFEN	16	PWML Falling Edge Enable
LEBDELAY	6:0	Leading-Edge Blanking Delay for TRGINx

PWM_CMUPD2PWM Channel Mode Update Register (ch_num = 2)

Address: 0x4005C440
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CPOLINVUP	13	Channel Polarity Inversion Update
CPOLUP	9	Channel Polarity Update

PWM_ETRG2PWM External Trigger Register (trg_num = 2)

Address: 0x4005C44C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
TRGSRC	30	Trigger Source
TRGFILT	29	Filtered input
TRGEDGE	28	Edge Selection `0` TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 `1` TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
TRGMODE	25:24	External Trigger Mode `0` External trigger is not enabled. `1` External PWM Reset Mode `2` External PWM Start Mode `3` Cycle-by-cycle Duty Mode
MAXCNT	23:0	Maximum Counter value
RFEN	31	Recoverable Fault Enable

PWM_LEBR2PWM Leading-Edge Blanking Register (trg_num = 2)

Address: 0x4005C450
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
PWMHREN	19	PWMH Rising Edge Enable
PWMHFEN	18	PWMH Falling Edge Enable
PWMLREN	17	PWML Rising Edge Enable
PWMLFEN	16	PWML Falling Edge Enable
LEBDELAY	6:0	Leading-Edge Blanking Delay for TRGINx

PWM_CMUPD3PWM Channel Mode Update Register (ch_num = 3)

Address: 0x4005C460
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
CPOLINVUP	13	Channel Polarity Inversion Update
CPOLUP	9	Channel Polarity Update

PWM1 Pulse Width Modulation Controller

PWM1 Pulse Width Modulation Controller