The 32 registers of SystemControl (System Control Registers), from 0xE000E004, with their reset value and every field. The PIC32CZ2051CA90100 has 5746 registers in 63 peripherals, one page each.
SystemControl System Control Registers
ICTRInterrupt Controller Type Register
Address
0xE000E004
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
INTLINESNUM
3:0
ACTLRAuxiliary Control Register
Address
0xE000E008
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
DISOOFP
9
Disable out-of-order FP instructions
DISFPCA
8
Disable automatic update of CONTROL.FPCA
DISFOLD
2
Disable IT folding
DISDEFWBUF
1
Disable wruite buffer use during default memory map accesses
DISMCYCINT
0
Disable interruption of LDM/STM instructions
CPUIDCPUID Base Register
Address
0xE000ED00
Reset
0x410FC240
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
VARIANT
23:20
Variant number
CONSTANT
19:16
Constant
PARTNO
15:4
Process Part Number, 0xC24=Cortex-M4
REVISION
3:0
Processor revision number
IMPLEMENTER
31:24
Implementer code, 0x41=ARM
ICSRInterrupt Control and State Register
Address
0xE000ED04
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
PENDSVSET
28
PendSV set-pending bit
0 Write: no effect; read: PendSV exception is not pending
1 Write: changes PendSV exception state to pending; read: PendSV exception is pending
PENDSVCLR
27
PendSV clear-pending bit
0 No effect
1 Removes the pending state from the PendSV exception
PENDSTSET
26
SysTick set-pending bit
0 Write: no effect; read: SysTick exception is not pending
1 Write: changes SysTick exception state to pending; read: SysTick exception is pending
PENDSTCLR
25
SysTick clear-pending bit
0 No effect
1 Removes the pending state from the SysTick exception
ISRPREEMPT
23
Debug only
ISRPENDING
22
Interrupt pending flag
VECTPENDING
17:12
Exception number of the highest priority pending enabled exception
RETTOBASE
11
No preempted active exceptions to execute
VECTACTIVE
8:0
Active exception number
NMIPENDSET
31
NMI set-pending bit
0 Write: no effect; read: NMI exception is not pending
1 Write: changes NMI exception state to pending; read: NMI exception is pending
VTORVector Table Offset Register
Address
0xE000ED08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TBLOFF
31:7
Vector table base offset
AIRCRApplication Interrupt and Reset Control Register
Address
0xE000ED0C
Reset
0xFA050000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ENDIANNESS
15
Data endianness, 0=little, 1=big
0 Little-endian
1 Big-endian
PRIGROUP
10:8
Interrupt priority grouping
SYSRESETREQ
2
System Reset Request
0 No system reset request
1 Asserts a signal to the outer system that requests a reset
VECTCLRACTIVE
1
Must write 0
VECTRESET
0
Must write 0
VECTKEY
31:16
Register key
SCRSystem Control Register
Address
0xE000ED10
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
SEVONPEND
4
Send Event on Pending bit
0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
SLEEPDEEP
2
Deep Sleep used as low power mode
0 Sleep
1 Deep sleep
SLEEPONEXIT
1
Sleep-on-exit on handler return
0 Do not sleep when returning to Thread mode
1 Enter sleep, or deep sleep, on return from an ISR
CCRConfiguration and Control Register
Address
0xE000ED14
Reset
0x00000200
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
STKALIGN
9
Indicates stack alignment on exception entry
0 4-byte aligned
1 8-byte aligned
BFHFNMIGN
8
Ignore LDM/STM BusFault for -1/-2 priority handlers
DIV_0_TRP
4
Enables divide by 0 trap
UNALIGN_TRP
3
Enables unaligned access traps
0 Do not trap unaligned halfword and word accesses
1 Trap unaligned halfword and word accesses
USERSETMPEND
1
Enables unprivileged software access to STIR register
NONBASETHRDENA
0
Indicates how processor enters Thread mode
SHPR1System Handler Priority Register 1
Address
0xE000ED18
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
PRI_6
23:16
Priority of system handler 6, UsageFault
PRI_5
15:8
Priority of system handler 5, BusFault
PRI_4
7:0
Priority of system handler 4, MemManage
SHPR2System Handler Priority Register 2
Address
0xE000ED1C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PRI_11
31:24
Priority of system handler 11, SVCall
SHPR3System Handler Priority Register 3
Address
0xE000ED20
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
PRI_14
23:16
Priority of system handler 14, PendSV
PRI_15
31:24
Priority of system handler 15, SysTick exception
SHCSRSystem Handler Control and State Register
Address
0xE000ED24
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
USGFAULTENA
18
UsageFault enable bit
BUSFAULTENA
17
BusFault enable bit
MEMFAULTENA
16
MemManage enable bit
SVCALLPENDED
15
SVCall pending bit
BUSFAULTPENDED
14
BusFault exception pending bit
MEMFAULTPENDED
13
MemManage exception pending bit
USGFAULTPENDED
12
UsageFault exception pending bit
SYSTICKACT
11
SysTick exception active bit
PENDSVACT
10
PendSV exception active bit
MONITORACT
8
DebugMonitor exception active bit
SVCALLACT
7
SVCall active bit
USGFAULTACT
3
UsageFault exception active bit
BUSFAULTACT
1
BusFault exception active bit
MEMFAULTACT
0
MemManage exception active bit
CFSRConfigurable Fault Status Register
Address
0xE000ED28
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
Field
Bits
What it does
DIVBYZERO
25
Divide by zero UsageFault
UNALIGNED
24
Unaligned access UsageFault
NOCP
19
No coprocessor UsageFault
INVPC
18
Invalid PC load UsageFault
INVSTATE
17
Invalid state UsageFault
UNDEFINSTR
16
Undefined instruction UsageFault
BFARVALID
15
BusFault Address Register valid
LSPERR
13
BusFault occured during FP lazy state preservation
STKERR
12
BusFault on stacking for exception entry
UNSTKERR
11
BusFault on unstacking for exception return
IMPRECISERR
10
Imprecise data bus error
PRECISERR
9
Precise data bus error
IBUSERR
8
Instruction bus error
MMARVALID
7
MemManage Fault Address Register valid
MLSPERR
5
MemManager Fault occured during FP lazy state preservation
MSTKERR
4
MemManage Fault on stacking for exception entry
MUNSTKERR
3
MemManage Fault on unstacking for exception return
DACCVIOL
1
Data access violation
IACCVIOL
0
Instruction access violation
HFSRHardFault Status Register
Address
0xE000ED2C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
FORCED
30
Forced Hard Fault
VECTTBL
1
BusFault on a Vector Table read during exception processing