The 11 registers of SUPC (Supply Controller), from 0x44020000, with their reset value and every field. The PIC32CZ2051CA91100 has 5746 registers in 63 peripherals, one page each.
SUPC Supply Controller
INTENCLRInterrupt Enable Clear
Address
0x44020000
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ADDVREGRDY2
10
Additional Regulator ready 2 Interrupt Enable
ADDVREGRDY1
9
Additional Regulator ready 1 Interrupt Enable
ADDVREGRDY0
8
Additional Regulator ready 0 Interrupt Enable
BORVDDUSB
6:5
BORVDDUSB Interrupt Enable
LVDRDY
1
Low Voltage Detector Ready Interrupt Enable
LVDET
0
Low Voltage Detector Interrupt Enable
INTENSETInterrupt Enable Set
Address
0x44020004
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ADDVREGRDY2
10
Additional Regulator ready 2 Interrupt Enable
ADDVREGRDY1
9
Additional Regulator ready 1 Interrupt Enable
ADDVREGRDY0
8
Additional Regulator ready 0 Interrupt Enable
BORVDDUSB
6:5
BORVDDUSB Interrupt Enable
LVDRDY
1
Low Voltage Detector Ready Interrupt Enable
LVDET
0
Low Voltage Detector Interrupt Enable
INTFLAGInterrupt Flag Status and Clear
Address
0x44020008
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ADDVREGRDY2
10
Additional Regulator ready 2 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct.
ADDVREGRDY1
9
Additional Regulator ready 1 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct.
ADDVREGRDY0
8
Additional Regulator ready 0 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct.
BORVDDUSB
6:5
BORVDDUSB Interrupt. Set to one if VDDUSB issue is detected.
LVDRDY
1
Low Voltage Detector Ready Interrupt. Set to one if LVD is ready to operate.
LVDET
0
Low Voltage Detector Interrupt. Set to one if VDDIO crosses the treshold voltage in the good direction according to LVD.DIR.
STATUSFlag status
Address
0x4402000C
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
Field
Bits
What it does
ADDVREGRDY2
10
Additional Regulator ready 2 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator.
ADDVREGRDY1
9
Additional Regulator ready 1 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator.
ADDVREGRDY0
8
Additional Regulator ready 0 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator.
BORVDDUSB
6:5
BORVDDUSB Status. One if VDDUSB is OK. It corresponds to bor_vddusb_n_mv signal of SMOR.
LVDRDY
1
Low Voltage Detector Ready Status
LVDET
0
Low Voltage Detector Status.
SYNCBUSYSynchronisation Busy
Address
0x44020010
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
BOR
0
BOR Synchronization Busy
BORBOR Control
Address
0x44020014
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
BORFILT
9:8
BOR filtering
0 No digital filtering
1 32us filtering
2 125us filtering
3 250us filtering
DCBORPSEL
6:4
Duty Cycle BOR Prescaler Select
0 Not Divided
1 Divide clock by 2
2 Divide clock by 4
3 Divide clock by 8
4 Divide clock by 16
5 Divide clock by 32
6 Divide clock by 64
7 Divide clock by 128
LVDLVD Control
Address
0x44020018
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
LEVEL
19:16
Threshold Level. See "pwr_smor_[nn]_v1 DOS" - level section to get details.
RUNSTDBY
4
Run during Standby
OEVEN
3
Output Event Enable
DIR
2
Direction
0 Rising detection
1 Falling detection
ENABLE
1
Enable
VREGCTRLVREG Control
Address
0x4402001C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
AVREGSTDBY
26:24
Additional Voltage Regulator Configuration
0 Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well.
1 Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well.
AVREGEN
18:16
Additional Voltage Regulator Enable
CPEN
10:8
Charge Pump Enable and Auto-enable.
BKUP_VLD
5
Backup Valid Status Bit
SRAM_VLD
4
SRAM Valid Status Bit
OFFSTDBY
2
Off in Standby Control for VREGSW[N-1]. Useful for Riverside only.
0 In standby mode, VREGSW1,2,3 are OFF
1 In standby mode, VREGSW1,2,3 are ON
VREGOUT
1:0
VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN
0 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v.
1 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v.
2 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v.
VREFCTRLVREF Control
Address
0x44020020
Reset
0x00000003
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
TSEN
4
Temperature Sensor Output Enable
LPHIB
1
Bandgap and Regulators Low Power Hibernate Enable
0 In hibernate mode, bandgap is set to nominal power mode. As a consequence, enabled regulator(s) are set to nominal power mode.
1 In hibernate mode, bandgap is set to low power mode. As a consequence, enabled regulator(s) are set to low power mode.
LPSTDBY
0
Bandgap and Regulators Low Power Standby Enable
0 In standby mode, bandgap and enabled regulator(s) are set to nominal power mode.
1 In standby mode, bandgap and enabled regulator(s) are set to low power mode.
BKOUTBackup Output Control
Address
0x44020028
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
TGLOM1
27:26
Toggle Output Mode
0 The output does not toggle.
1 The output toggles on RTC event.
2 The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software.
TGLOM0
25:24
Toggle Output Mode
0 The output does not toggle.
1 The output toggles on RTC event.
2 The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software.
BETA