PIC32CZ2051CA91144 FUSES registers The 121 registers of FUSES (Defines FUSE parameters), from 0x0A000000, with their reset value and every field. The PIC32CZ2051CA91144 has 5988 registers in 67 peripherals, one page each.
FUSES Defines FUSE parameters FSEQFlash Sequence Number
Address 0x0A000000
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SEQNUM 15:0 Sequence Number SEQBAR 31:16 Sequence Number Bar (Negeated)
AFSEQFlash Alternate Sequence Number
Address 0x0A000020
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does ASEQNUM 15:0 Alternate Sequence Number ASEQBAR 31:16 Alternate Sequence Number Bar (Negeated)
FUCFG0WDT Configuration
Address 0x0A000040
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does WDT_EWOFFSET 19:16 Early Warning Interrupt Time Offset WDT_WINDOW 15:12 Window Mode Time-out Period WDT_PER 11:8 Time-out Period WDT_ALWAYSON 7 Always On WDT_RUNSTDBY 6 Run in Standby WDT_WEN 2 Window Mode Enable WDT_ENABLE 1 Enable
FUCFG1User Configuration 1 (System Bus Configuration)
Address 0x0A000044
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does SSXEXSQI0 23:16 Execute from SQI0 XIP Memory SSXEXEBI 15:8 Execute from EBI attached Memory SSXEXDRM 7:0 Execute from System Memory SSXEXSQI1 31:24 Execute from SQI1 XIP Memory
FUCFG2User Configuration 2 (Deep Sleep SMOR Configuration)
Address 0x0A000048
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does BOR_TRIP 2:1 BOT Trip Points BOR_HYST 0 BOT Trip Hystersis
FUCFG3User Configuration 2 (SMOR Configuration)
Address 0x0A00004C
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does HYST_BOR_VDDREG 10 BOR Trip Point Hystersis for VDDREG BOR_TRIP_VDDA 8:7 BOR Trip Points for VDDANA HYST_BOR_VDDA 6 BOR Trip Point Hystersis for VDDANA BOR_TRIP_VDDIO 2:1 BOR Trip Points for VDDIO HYST_BOR_VDDIO 0 BOR Trip Point Hystersis for VDDIO
FUCFG5User Configuration 5 (VREG Charge Pump Configuration)
Address 0x0A000054
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does UCP3 15:12 Charge Pump Settings UCP2 11:8 Charge Pump Settings UCP1 7:4 Charge Pump Settings UCP0 3:0 Charge Pump Settings
FUCFG6User Configuration 6 (FCR ECCCTRL Configuration)
Address 0x0A000058
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PFM_ECCUNLCK 6 ECC Mode Control Unlock PFM_ECCCTL 5:4 ECC Mode Control
FUCFG7User Configuration 7 (FCR CTRLB Configuration)
Address 0x0A00005C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does PFM_TEMP 1 NVM Operating Temperature Read Mode
FUCFG8User Configuration 8 (FCW CWP Configuration)
Address 0x0A000060
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does PFM_UC2WPLOCK 24 User Configuration Page 2 Write Protection Lock PFM_UC1WPLOCK 16 User Configuration Page 1 Write Protection Lock PFM_UC2WP 8 User Configuration Page 2 Write Protect PFM_UC1WP 0 User Configuration Page 1 Write Protect
FUCFG9User Configuration 9 (RAM BISR and ECC Configuraiton)
Address 0x0A000064
Reset 0x00000202
Access read/write
Size 32-bit 2 fields
Field Bits What it does BISR_RST_EN0 9 Enable RAM Built-In Self Repair at Reset RAM_INIT_ENB 1 Enable RAM ECC Init at Reset
FUCFG16User Configuration 16 (HSM Firmware Metadata 0 Address)
Address 0x0A000080
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does HSM_PTRMETA0 31:0 HSM Firmware Metadata pointer 0
FUCFG24User Configuration 24 (HSM Firmware Metadata 1 Address)
Address 0x0A0000A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does HSM_PTRMETA1 31:0 HSM Firmware Metadata pointer 1
BLDRCFGBootloader Configuration
Address 0x0A002000
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does BROM_EN_DALUN 30 Enable DAL Unlock BROM_EN_PLL 29 Enable PLL (Settings in PLL0_<REGS> are used) BROM_EN_BFMCHK 28 Enable BFM CRC Check0 No verification1 Verify using crc32 PFM_BCWP 1 Boot Configration Page Write Protect PFM_BCRP 0 Boot Configration Page Read Protect BROM_EN_RWLOCKS 31 Enable Read/Write Locks
BROM_BSEQBoot Configuraiton Page Sequence Number
Address 0x0A002004
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SEQNUM 15:0 Sequence Number SEQBAR 31:16 Sequence Number Bar (Negeated)
BFM_CHK_TABLEPTRBFM CRC Table Pointer
Address 0x0A002008
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_TZ0_CE_ALL0Chip Erase Key for TZ0_ALL
Address 0x0A002080
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_TZ0_CE_ALL1Chip Erase Key for TZ0_ALL
Address 0x0A002084
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_TZ0_CE_ALL2Chip Erase Key for TZ0_ALL
Address 0x0A002088
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_TZ0_CE_ALL3Chip Erase Key for TZ0_ALL
Address 0x0A00208C
Reset 0x00000000
Access read/write
Size 32-bit CELOCK_TZ0_CE_ALL0Chip Erase Lock for TZ0_ALL
Address 0x0A002090
Reset 0x00000000
Access read/write
Size 32-bit CELOCK_TZ0_CE_ALL1Chip Erase Lock for TZ0_ALL
Address 0x0A002094
Reset 0x00000000
Access read/write
Size 32-bit CELOCK_TZ0_CE_ALL2Chip Erase Lock for TZ0_ALL
Address 0x0A002098
Reset 0x00000000
Access read/write
Size 32-bit CELOCK_TZ0_CE_ALL3Chip Erase Lock for TZ0_ALL
Address 0x0A00209C
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_CRCCMD0CRC Access Key
Address 0x0A0020A0
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_CRCCMD1CRC Access Key
Address 0x0A0020A4
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_CRCCMD2CRC Access Key
Address 0x0A0020A8
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_CRCCMD3CRC Access Key
Address 0x0A0020AC
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_CRCCMD0CRC Access Key Configuration
Address 0x0A0020B0
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_CRCCMD1CRC Access Key Configuration
Address 0x0A0020B4
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_CRCCMD2CRC Access Key Configuration
Address 0x0A0020B8
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_CRCCMD3CRC Access Key Configuration
Address 0x0A0020BC
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_HOSTDALELEV0Host Authenticated DAL Elevation Key
Address 0x0A0020C0
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_HOSTDALELEV1Host Authenticated DAL Elevation Key
Address 0x0A0020C4
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_HOSTDALELEV2Host Authenticated DAL Elevation Key
Address 0x0A0020C8
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_HOSTDALELEV3Host Authenticated DAL Elevation Key
Address 0x0A0020CC
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_HOSTDALELEV0Host Authenticated DAL Elevation Key Configuration
Address 0x0A0020D0
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_HOSTDALELEV1Host Authenticated DAL Elevation Key Configuration
Address 0x0A0020D4
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_HOSTDALELEV2Host Authenticated DAL Elevation Key Configuration
Address 0x0A0020D8
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_HOSTDALELEV3Host Authenticated DAL Elevation Key Configuration
Address 0x0A0020DC
Reset 0x00000000
Access read/write
Size 32-bit ROM_CTRLAROM CTRLA Settings (BROM_PLLEN must be set)
Address 0x0A0020E0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does PRMWS 10:8 Wait States ENABLE 2 Module Enable SWRST 1 Software Reset
FCR_CTRLAFCR CTRLA Settings (BROM_PLLEN must be set)
Address 0x0A0020E4
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does RDBUFWS 19:16 Data returned from the Read Buffer match the Flash Wait States AUTOWS 15 Automatic Wait State Enable. ADRWS 14 Address Wait State Enable FWS 11:8 Flash Access Time Defined in terms of AHB Clock Wait States ARB 2 AHB Arbitration scheme
RPMU_VREGCTRLRPMU VREGCTRL Settings (BROM_PLLEN must be set)
Address 0x0A0020E8
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does AVREGSTDBY 26:24 Additional Voltage Regulator Configuration0 Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well.1 Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well. AVREGEN 18:16 Additional Voltage Regulator Enable0 Always clear.4 Always clear. ULDOLEVEL 15:14 User LDO Voltage Level Selection0 Vout = 1.2v1 Vout = 1.5v2 Vout = 1.8v3 Vout = 2.5v ULDOSTDBY 13 User LDO Voltage Regulator Configuration0 Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well.1 Regulator is ON in Standby mode. is OFF from Hibernate mode. It is OFF in backup mode as well. ULDOEN 12 User LDO Voltage Regulator Enable CPEN 10:8 Charge Pump Enable and Auto-enable. BKUP_VLD 5 Backup Valid (always clear) SRAM_VLD 4 SRAM Valid (always clear) OFFSTDBY 2 Off in Standby Control for VREGSW[N-1]. Useful for Riverside only.0 In standby mode, VREGSW1,2,3 are OFF1 In standby mode, VREGSW1,2,3 are ON VREGOUT 1:0 VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN0 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v.1 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v.2 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v.
PLL0_CTRLPLL0 CTRL Settings (BROM_PLLEN must be set)
Address 0x0A0020EC
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does BWSEL 13:11 Bandwidth selection0 TBD1 TBD2 TBD3 TBD4 TBD5 TBD6 TBD7 TBD REFSEL 10:8 Reference selection0 Dedicated GCLK clock reference1 XOSC clock reference2 DFLL48M clock reference ONDEMAND 7 On Demand Control WRTLOCK 2 Write Lock ENABLE 1 PLL Enable
PLL0_FBDIVPLL0 FBDIV Settings (BROM_PLLEN must be set)
Address 0x0A0020F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does FBDIV 9:0 PLL Feed-Back Divider Factor
PLL0_REFDIVPLL0 REFDIV Settings (BROM_PLLEN must be set)
Address 0x0A0020F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does REFDIV 5:0 PLL reference division factor
PLL0_POSTDIVAPLL0 POSTDIVA Settings (BROM_PLLEN must be set)
Address 0x0A0020F8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does OUTEN 7 PLL output 0 enable POSTDIV 5:0 PLL output 0 clock division factor
MCLK_CLKDIV1MCLK CLKDIV1 Settings (BROM_PLLEN must be set)
Address 0x0A0020FC
Reset 0x00000000
Access read/write
Size 32-bit GCLK_GENCTRL0GCLK GENCTRL0 Settings (BROM_PLLEN must be set)
Address 0x0A002100
Reset 0x00000000
Access read/write
Size 32-bit BROM_BOOTCFGCRC0Boot Configuraiton Page CRC
Address 0x0A002110
Reset 0x00000000
Access read/write
Size 32-bit BROM_BOOTCFGCRC1Boot Configuraiton Page CRC
Address 0x0A002114
Reset 0x00000000
Access read/write
Size 32-bit BROM_BOOTCFGCRC2Boot Configuraiton Page CRC
Address 0x0A002118
Reset 0x00000000
Access read/write
Size 32-bit BROM_BOOTCFGCRC3Boot Configuraiton Page CRC
Address 0x0A00211C
Reset 0x00000000
Access read/write
Size 32-bit BROM_PAGEENDPage End Marker for Verified Data
Address 0x0A002120
Reset 0x00000000
Access read/write
Size 32-bit DALDebug Access Level
Address 0x0A004000
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CPU1 15:8 HSM DAL Elevation Value CPU0 7:0 Host DAL Elevation Value129 FCW_DAL0_VALUE153 FCW_DAL1_VALUE219 FCW_DAL2_VALUE
FCCFG64PTC Calibration
Address 0x0A007180
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does PTCFG0 15:0
FCCFG65ADC Calibration
Address 0x0A007184
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does ADCFG0 31:0
FCCFG66Comparator Calibration
Address 0x0A007188
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does ACPAIR_SEL 7:0
FCCFG69Temperature calibration values 0
Address 0x0A007194
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does ROOM_ADC_VAL_BUFF1V2 23:12 ROOM_ADC_VAL_PTAT 11:0 ROOM_TEMP_VAL_INT 31:24
FCCFG70Temperature calibration values 1
Address 0x0A007198
Reset 0x00000000
Access read only
Size 32-bit 4 fields
Field Bits What it does HOT_TEMP_VAL_DEC 19:16 ROOM_VREF_VAL 15:4 ROOM_TEMP_VAL_DEC 3:0 Reserved 31:20
FCCFG71Temperature calibration values 2
Address 0x0A00719C
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does HOT_ADC_VAL_BUFF1V2 23:12 HOT_ADC_VAL_PTAT 11:0 HOT_TEMP_VAL_INT 31:24
FCCFG72MAC ID (31 through 0)
Address 0x0A0071A0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does FMAC_31_0 31:0
FCCFG73MAC ID (47 through 32)
Address 0x0A0071A4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does FMAC_47_32 15:0
FCCFG_UNIQID0Factory programed Unique ID
Address 0x0A0071E0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does UID 31:0 Unique ID (programmed at factory)
FCCFG_UNIQID1Factory programed Unique ID
Address 0x0A0071E4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does UID 31:0 Unique ID (programmed at factory)
FCCFG_UNIQID2Factory programed Unique ID
Address 0x0A0071E8
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does UID 31:0 Unique ID (programmed at factory)
FCCFG_UNIQID3Factory programed Unique ID
Address 0x0A0071EC
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does UID 31:0 Unique ID (programmed at factory)
FSEQFlash Sequence Number
Address 0x0A008000
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SEQNUM 15:0 Sequence Number SEQBAR 31:16 Sequence Number Bar (Negeated)
AFSEQFlash Alternate Sequence Number
Address 0x0A008020
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does ASEQNUM 15:0 Alternate Sequence Number ASEQBAR 31:16 Alternate Sequence Number Bar (Negeated)
FUCFG0WDT Configuration
Address 0x0A008040
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does WDT_EWOFFSET 19:16 Early Warning Interrupt Time Offset WDT_WINDOW 15:12 Window Mode Time-out Period WDT_PER 11:8 Time-out Period WDT_ALWAYSON 7 Always On WDT_RUNSTDBY 6 Run in Standby WDT_WEN 2 Window Mode Enable WDT_ENABLE 1 Enable
FUCFG1User Configuration 1 (System Bus Configuration)
Address 0x0A008044
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does SSXEXSQI0 23:16 Execute from SQI0 XIP Memory SSXEXEBI 15:8 Execute from EBI attached Memory SSXEXDRM 7:0 Execute from System Memory SSXEXSQI1 31:24 Execute from SQI1 XIP Memory
FUCFG2User Configuration 2 (Deep Sleep SMOR Configuration)
Address 0x0A008048
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does BOR_TRIP 2:1 BOT Trip Points BOR_HYST 0 BOT Trip Hystersis
FUCFG3User Configuration 2 (SMOR Configuration)
Address 0x0A00804C
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does HYST_BOR_VDDREG 10 BOR Trip Point Hystersis for VDDREG BOR_TRIP_VDDA 8:7 BOR Trip Points for VDDANA HYST_BOR_VDDA 6 BOR Trip Point Hystersis for VDDANA BOR_TRIP_VDDIO 2:1 BOR Trip Points for VDDIO HYST_BOR_VDDIO 0 BOR Trip Point Hystersis for VDDIO
FUCFG5User Configuration 5 (VREG Charge Pump Configuration)
Address 0x0A008054
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does UCP3 15:12 Charge Pump Settings UCP2 11:8 Charge Pump Settings UCP1 7:4 Charge Pump Settings UCP0 3:0 Charge Pump Settings
FUCFG6User Configuration 6 (FCR ECCCTRL Configuration)
Address 0x0A008058
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PFM_ECCUNLCK 6 ECC Mode Control Unlock PFM_ECCCTL 5:4 ECC Mode Control
FUCFG7User Configuration 7 (FCR CTRLB Configuration)
Address 0x0A00805C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does PFM_TEMP 1 NVM Operating Temperature Read Mode
FUCFG8User Configuration 8 (FCW CWP Configuration)
Address 0x0A008060
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does PFM_UC2WPLOCK 24 User Configuration Page 2 Write Protection Lock PFM_UC1WPLOCK 16 User Configuration Page 1 Write Protection Lock PFM_UC2WP 8 User Configuration Page 2 Write Protect PFM_UC1WP 0 User Configuration Page 1 Write Protect
FUCFG9User Configuration 9 (RAM BISR and ECC Configuraiton)
Address 0x0A008064
Reset 0x00000202
Access read/write
Size 32-bit 2 fields
Field Bits What it does BISR_RST_EN0 9 Enable RAM Built-In Self Repair at Reset RAM_INIT_ENB 1 Enable RAM ECC Init at Reset
FUCFG16User Configuration 16 (HSM Firmware Metadata 0 Address)
Address 0x0A008080
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does HSM_PTRMETA0 31:0 HSM Firmware Metadata pointer 0
FUCFG24User Configuration 24 (HSM Firmware Metadata 1 Address)
Address 0x0A0080A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does HSM_PTRMETA1 31:0 HSM Firmware Metadata pointer 1
BLDRCFGBootloader Configuration
Address 0x0A00A000
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does BROM_EN_DALUN 30 Enable DAL Unlock BROM_EN_PLL 29 Enable PLL (Settings in PLL0_<REGS> are used) BROM_EN_BFMCHK 28 Enable BFM CRC Check0 No verification1 Verify using crc32 PFM_BCWP 1 Boot Configration Page Write Protect PFM_BCRP 0 Boot Configration Page Read Protect BROM_EN_RWLOCKS 31 Enable Read/Write Locks
BROM_BSEQBoot Configuraiton Page Sequence Number
Address 0x0A00A004
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does SEQNUM 15:0 Sequence Number SEQBAR 31:16 Sequence Number Bar (Negeated)
BFM_CHK_TABLEPTRBFM CRC Table Pointer
Address 0x0A00A008
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_TZ0_CE_ALL0Chip Erase Key for TZ0_ALL
Address 0x0A00A080
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_TZ0_CE_ALL1Chip Erase Key for TZ0_ALL
Address 0x0A00A084
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_TZ0_CE_ALL2Chip Erase Key for TZ0_ALL
Address 0x0A00A088
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_TZ0_CE_ALL3Chip Erase Key for TZ0_ALL
Address 0x0A00A08C
Reset 0x00000000
Access read/write
Size 32-bit CELOCK_TZ0_CE_ALL0Chip Erase Lock for TZ0_ALL
Address 0x0A00A090
Reset 0x00000000
Access read/write
Size 32-bit CELOCK_TZ0_CE_ALL1Chip Erase Lock for TZ0_ALL
Address 0x0A00A094
Reset 0x00000000
Access read/write
Size 32-bit CELOCK_TZ0_CE_ALL2Chip Erase Lock for TZ0_ALL
Address 0x0A00A098
Reset 0x00000000
Access read/write
Size 32-bit CELOCK_TZ0_CE_ALL3Chip Erase Lock for TZ0_ALL
Address 0x0A00A09C
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_CRCCMD0CRC Access Key
Address 0x0A00A0A0
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_CRCCMD1CRC Access Key
Address 0x0A00A0A4
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_CRCCMD2CRC Access Key
Address 0x0A00A0A8
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_CRCCMD3CRC Access Key
Address 0x0A00A0AC
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_CRCCMD0CRC Access Key Configuration
Address 0x0A00A0B0
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_CRCCMD1CRC Access Key Configuration
Address 0x0A00A0B4
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_CRCCMD2CRC Access Key Configuration
Address 0x0A00A0B8
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_CRCCMD3CRC Access Key Configuration
Address 0x0A00A0BC
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_HOSTDALELEV0Host Authenticated DAL Elevation Key
Address 0x0A00A0C0
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_HOSTDALELEV1Host Authenticated DAL Elevation Key
Address 0x0A00A0C4
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_HOSTDALELEV2Host Authenticated DAL Elevation Key
Address 0x0A00A0C8
Reset 0x00000000
Access read/write
Size 32-bit KEYVAL_HOSTDALELEV3Host Authenticated DAL Elevation Key
Address 0x0A00A0CC
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_HOSTDALELEV0Host Authenticated DAL Elevation Key Configuration
Address 0x0A00A0D0
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_HOSTDALELEV1Host Authenticated DAL Elevation Key Configuration
Address 0x0A00A0D4
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_HOSTDALELEV2Host Authenticated DAL Elevation Key Configuration
Address 0x0A00A0D8
Reset 0x00000000
Access read/write
Size 32-bit KEYCONFIG_HOSTDALELEV3Host Authenticated DAL Elevation Key Configuration
Address 0x0A00A0DC
Reset 0x00000000
Access read/write
Size 32-bit ROM_CTRLAROM CTRLA Settings (BROM_PLLEN must be set)
Address 0x0A00A0E0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does PRMWS 10:8 Wait States ENABLE 2 Module Enable SWRST 1 Software Reset
FCR_CTRLAFCR CTRLA Settings (BROM_PLLEN must be set)
Address 0x0A00A0E4
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does RDBUFWS 19:16 Data returned from the Read Buffer match the Flash Wait States AUTOWS 15 Automatic Wait State Enable. ADRWS 14 Address Wait State Enable FWS 11:8 Flash Access Time Defined in terms of AHB Clock Wait States ARB 2 AHB Arbitration scheme
RPMU_VREGCTRLRPMU VREGCTRL Settings (BROM_PLLEN must be set)
Address 0x0A00A0E8
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does AVREGSTDBY 26:24 Additional Voltage Regulator Configuration0 Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well.1 Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well. AVREGEN 18:16 Additional Voltage Regulator Enable0 Always clear.4 Always clear. ULDOLEVEL 15:14 User LDO Voltage Level Selection0 Vout = 1.2v1 Vout = 1.5v2 Vout = 1.8v3 Vout = 2.5v ULDOSTDBY 13 User LDO Voltage Regulator Configuration0 Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well.1 Regulator is ON in Standby mode. is OFF from Hibernate mode. It is OFF in backup mode as well. ULDOEN 12 User LDO Voltage Regulator Enable CPEN 10:8 Charge Pump Enable and Auto-enable. BKUP_VLD 5 Backup Valid (always clear) SRAM_VLD 4 SRAM Valid (always clear) OFFSTDBY 2 Off in Standby Control for VREGSW[N-1]. Useful for Riverside only.0 In standby mode, VREGSW1,2,3 are OFF1 In standby mode, VREGSW1,2,3 are ON VREGOUT 1:0 VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN0 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v.1 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v.2 In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v.
PLL0_CTRLPLL0 CTRL Settings (BROM_PLLEN must be set)
Address 0x0A00A0EC
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does BWSEL 13:11 Bandwidth selection0 TBD1 TBD2 TBD3 TBD4 TBD5 TBD6 TBD7 TBD REFSEL 10:8 Reference selection0 Dedicated GCLK clock reference1 XOSC clock reference2 DFLL48M clock reference ONDEMAND 7 On Demand Control WRTLOCK 2 Write Lock ENABLE 1 PLL Enable
PLL0_FBDIVPLL0 FBDIV Settings (BROM_PLLEN must be set)
Address 0x0A00A0F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does FBDIV 9:0 PLL Feed-Back Divider Factor
PLL0_REFDIVPLL0 REFDIV Settings (BROM_PLLEN must be set)
Address 0x0A00A0F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does REFDIV 5:0 PLL reference division factor
PLL0_POSTDIVAPLL0 POSTDIVA Settings (BROM_PLLEN must be set)
Address 0x0A00A0F8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does OUTEN 7 PLL output 0 enable POSTDIV 5:0 PLL output 0 clock division factor
MCLK_CLKDIV1MCLK CLKDIV1 Settings (BROM_PLLEN must be set)
Address 0x0A00A0FC
Reset 0x00000000
Access read/write
Size 32-bit GCLK_GENCTRL0GCLK GENCTRL0 Settings (BROM_PLLEN must be set)
Address 0x0A00A100
Reset 0x00000000
Access read/write
Size 32-bit BROM_BOOTCFGCRC0Boot Configuraiton Page CRC
Address 0x0A00A110
Reset 0x00000000
Access read/write
Size 32-bit BROM_BOOTCFGCRC1Boot Configuraiton Page CRC
Address 0x0A00A114
Reset 0x00000000
Access read/write
Size 32-bit BROM_BOOTCFGCRC2Boot Configuraiton Page CRC
Address 0x0A00A118
Reset 0x00000000
Access read/write
Size 32-bit BROM_BOOTCFGCRC3Boot Configuraiton Page CRC
Address 0x0A00A11C
Reset 0x00000000
Access read/write
Size 32-bit BROM_PAGEENDPage End Marker for Verified Data
Address 0x0A00A120
Reset 0x00000000
Access read/write
Size 32-bit 
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