PIC32CZ2051CA91144 SDMMC0 registers

The 46 registers of SDMMC0 (SD/MMC Host Controller), from 0x458A0000, with their reset value and every field. The PIC32CZ2051CA91144 has 5988 registers in 67 peripherals, one page each.

SDMMC0 SD/MMC Host Controller

SSARSDMA System Address / Argument 2

Address: 0x458A0000
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR	31:0	SDMA System Address
ARG2	31:0	Argument 2

BSRBlock Size

Address: 0x458A0004
Reset: 0x0000
Access: read/write
Size: 16-bit

2 fields

Field	Bits	What it does
BOUNDARY	14:12	SDMA Buffer Boundary `0` 4k bytes `1` 8k bytes `2` 16k bytes `3` 32k bytes `4` 64k bytes `5` 128k bytes `6` 256k bytes `7` 512k bytes
BLOCKSIZE	9:0	Transfer Block Size

BCRBlock Count

Address: 0x458A0006
Reset: 0x0000
Access: read/write
Size: 16-bit

1 field

Field	Bits	What it does
BCNT	15:0	Blocks Count for Current Transfer

ARG1RArgument 1

Address: 0x458A0008
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ARG	31:0	Argument 1

TMRTransfer Mode

Address: 0x458A000C
Reset: 0x0000
Access: read/write
Size: 16-bit

5 fields

Field	Bits	What it does
MSBSEL	5	Multi/Single Block Selection `0` Single Block `1` Multiple Block
DTDSEL	4	Data Transfer Direction Selection `0` Write (Host to Card) `1` Read (Card to Host)
ACMDEN	3:2	Auto Command Enable `0` Auto Command Disabled `1` Auto CMD12 Enable `2` Auto CMD23 Enable
BCEN	1	Block Count Enable `0` Disable `1` Enable
DMAEN	0	DMA Enable `0` No data transfer or Non DMA data transfer `1` DMA data transfer

CRCommand

Address: 0x458A000E
Reset: 0x0000
Access: read/write
Size: 16-bit

6 fields

Field	Bits	What it does
CMDIDX	13:8	Command Index
CMDTYP	7:6	Command Type `0` Other commands `1` CMD52 for writing Bus Suspend in CCCR `2` CMD52 for writing Function Select in CCCR `3` CMD12, CMD52 for writing I/O Abort in CCCR
DPSEL	5	Data Present Select `0` No Data Present `1` Data Present
CMDICEN	4	Command Index Check Enable `0` Disable `1` Enable
CMDCCEN	3	Command CRC Check Enable `0` Disable `1` Enable
RESPTYP	1:0	Response Type `0` No response `1` 136-bit response `2` 48-bit response `3` 48-bit response check busy after response

RR0Response

Address: 0x458A0010
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CMDRESP	31:0	Command Response

RR1Response

Address: 0x458A0014
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CMDRESP	31:0	Command Response

RR2Response

Address: 0x458A0018
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CMDRESP	31:0	Command Response

RR3Response

Address: 0x458A001C
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CMDRESP	31:0	Command Response

BDPRBuffer Data Port

Address: 0x458A0020
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
BUFDATA	31:0	Buffer Data

PSRPresent State

Address: 0x458A0024
Reset: 0x00F80000
Access: read only
Size: 32-bit

14 fields

Field	Bits	What it does
CMDLL	24	CMD Line Level
DATLL	23:20	DAT[3:0] Line Level
WRPPL	19	Write Protect Pin Level `0` Write protected (SDWP#=0) `1` Write enabled (SDWP#=1)
CARDDPL	18	Card Detect Pin Level `0` No card present (SDCD#=1) `1` Card present (SDCD#=0)
CARDSS	17	Card State Stable `0` Reset or Debouncing `1` No Card or Insered
CARDINS	16	Card Inserted `0` Reset or Debouncing or No Card `1` Card inserted
BUFRDEN	11	Buffer Read Enable `0` Read disable `1` Read enable
BUFWREN	10	Buffer Write Enable `0` Write disable `1` Write enable
RTACT	9	Read Transfer Active `0` No valid data `1` Transferring data
WTACT	8	Write Transfer Active `0` No valid data `1` Transferring data
RTREQ	3	Re-Tuning Request `0` Fixed or well-tuned sampling clock `1` Sampling clock needs re-tuning
DLACT	2	DAT Line Active `0` DAT Line Inactive `1` DAT Line Active
CMDINHD	1	Command Inhibit (DAT) `0` Can issue command which uses the DAT line `1` Cannot issue command which uses the DAT line
CMDINHC	0	Command Inhibit (CMD) `0` Can issue command using only CMD line `1` Cannot issue command

HC1RHost Control 1

Address: 0x458A0028
Reset: 0x00
Access: read/write

7CARDDSEL
6CARDDTL
5–
4DMASEL1
3DMASEL0
2HSEN
1DW
0LEDCTRL

6 fields

Field	Bits	What it does
CARDDSEL	7	Card Detect Signal Selection `0` SDCD# is selected (for normal use) `1` The Card Select Test Level is selected (for test purpose)
CARDDTL	6	Card Detect Test Level `0` No Card `1` Card Inserted
DMASEL	4:3	DMA Select `0` SDMA is selected `2` 32-bit Address ADMA2 is selected
HSEN	2	High Speed Enable `0` Normal Speed mode `1` High Speed mode
DW	1	Data Width `0` 1-bit mode `1` 4-bit mode
LEDCTRL	0	LED Control `0` LED off `1` LED on

PCRPower Control

Address: 0x458A0029
Reset: 0x0E
Access: read/write

7–
6–
5–
4–
3SDBVSEL2
2SDBVSEL1
1SDBVSEL0
0SDBPWR

2 fields

Field	Bits	What it does
SDBVSEL	3:1	SD Bus Voltage Select `5` 1.8V (Typ.) `6` 3.0V (Typ.) `7` 3.3V (Typ.)
SDBPWR	0	SD Bus Power `0` Power off `1` Power on

BGCRBlock Gap Control

Address: 0x458A002A
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3INTBG
2RWCTRL
1CONTR
0STPBGR

4 fields

Field	Bits	What it does
INTBG	3	Interrupt at Block Gap `0` Disabled `1` Enabled
RWCTRL	2	Read Wait Control `0` Disable Read Wait Control `1` Enable Read Wait Control
CONTR	1	Continue Request `0` Not affected `1` Restart
STPBGR	0	Stop at Block Gap Request `0` Transfer `1` Stop

WCRWakeup Control

Address: 0x458A002B
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2WKENCREM
1WKENCINS
0WKENCINT

3 fields

Field	Bits	What it does
WKENCREM	2	Wakeup Event Enable on Card Removal `0` Disable `1` Enable
WKENCINS	1	Wakeup Event Enable on Card Insertion `0` Disable `1` Enable
WKENCINT	0	Wakeup Event Enable on Card Interrupt `0` Disable `1` Enable

CCRClock Control

Address: 0x458A002C
Reset: 0x0000
Access: read/write
Size: 16-bit

6 fields

Field	Bits	What it does
SDCLKFSEL	15:8	SDCLK Frequency Select
USDCLKFSEL	7:6	Upper Bits of SDCLK Frequency Select
CLKGSEL	5	Clock Generator Select `0` Divided Clock Mode `1` Programmable Clock Mode
SDCLKEN	2	SD Clock Enable `0` Disable `1` Enable
INTCLKS	1	Internal Clock Stable `0` Not Ready `1` Ready
INTCLKEN	0	Internal Clock Enable `0` Stop `1` Oscillate

TCRTimeout Control

Address: 0x458A002E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3DTCVAL3
2DTCVAL2
1DTCVAL1
0DTCVAL0

1 field

Field	Bits	What it does
DTCVAL	3:0	Data Timeout Counter Value

SRRSoftware Reset

Address: 0x458A002F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2SWRSTDAT
1SWRSTCMD
0SWRSTALL

3 fields

Field	Bits	What it does
SWRSTDAT	2	Software Reset For DAT Line `0` Work `1` Reset
SWRSTCMD	1	Software Reset For CMD Line `0` Work `1` Reset
SWRSTALL	0	Software Reset For All `0` Work `1` Reset

NISTRNormal Interrupt Status

Address: 0x458A0030
Reset: 0x0000
Access: read/write
Size: 16-bit

11 fields

Field	Bits	What it does
ERRINT	15	Error Interrupt `0` No Error `1` Error
BOOTAR	14	Boot Acknowledge Received
CINT	8	Card Interrupt `0` No Card Interrupt `1` Generate Card Interrupt
CREM	7	Card Removal `0` Card state stable or Debouncing `1` Card Removed
CINS	6	Card Insertion `0` Card state stable or Debouncing `1` Card inserted
BRDRDY	5	Buffer Read Ready `0` Not ready to read buffer `1` Ready to read buffer
BWRRDY	4	Buffer Write Ready `0` Not ready to write buffer `1` Ready to write buffer
DMAINT	3	DMA Interrupt `0` No DMA Interrupt `1` DMA Interrupt is generated
BLKGE	2	Block Gap Event `0` No Block Gap Event `1` Transaction stopped at block gap
TRFC	1	Transfer Complete `0` Not complete `1` Command execution is completed
CMDC	0	Command Complete `0` No command complete `1` Command complete

EISTRError Interrupt Status

Address: 0x458A0032
Reset: 0x0000
Access: read/write
Size: 16-bit

11 fields

Field	Bits	What it does
BOOTAE	12	Boot Acknowledge Error `0` FIFO contains at least one byte `1` FIFO is empty
ADMA	9	ADMA Error `0` No Error `1` Error
ACMD	8	Auto CMD Error `0` No Error `1` Error
CURLIM	7	Current Limit Error `0` No Error `1` Power Fail
DATEND	6	Data End Bit Error `0` No Error `1` Error
DATCRC	5	Data CRC Error `0` No Error `1` Error
DATTEO	4	Data Timeout Error `0` No Error `1` Timeout
CMDIDX	3	Command Index Error `0` No Error `1` Error
CMDEND	2	Command End Bit Error `0` No error `1` End Bit Error Generated
CMDCRC	1	Command CRC Error `0` No Error `1` CRC Error Generated
CMDTEO	0	Command Timeout Error `0` No Error `1` Timeout

NISTERNormal Interrupt Status Enable

Address: 0x458A0034
Reset: 0x0000
Access: read/write
Size: 16-bit

10 fields

Field	Bits	What it does
BOOTAR	14	Boot Acknowledge Received Status Enable
CINT	8	Card Interrupt Status Enable `0` Masked `1` Enabled
CREM	7	Card Removal Status Enable `0` Masked `1` Enabled
CINS	6	Card Insertion Status Enable `0` Masked `1` Enabled
BRDRDY	5	Buffer Read Ready Status Enable `0` Masked `1` Enabled
BWRRDY	4	Buffer Write Ready Status Enable `0` Masked `1` Enabled
DMAINT	3	DMA Interrupt Status Enable `0` Masked `1` Enabled
BLKGE	2	Block Gap Event Status Enable `0` Masked `1` Enabled
TRFC	1	Transfer Complete Status Enable `0` Masked `1` Enabled
CMDC	0	Command Complete Status Enable `0` Masked `1` Enabled

EISTERError Interrupt Status Enable

Address: 0x458A0036
Reset: 0x0000
Access: read/write
Size: 16-bit

11 fields

Field	Bits	What it does
BOOTAE	12	Boot Acknowledge Error Status Enable
ADMA	9	ADMA Error Status Enable `0` Masked `1` Enabled
ACMD	8	Auto CMD Error Status Enable `0` Masked `1` Enabled
CURLIM	7	Current Limit Error Status Enable `0` Masked `1` Enabled
DATEND	6	Data End Bit Error Status Enable `0` Masked `1` Enabled
DATCRC	5	Data CRC Error Status Enable `0` Masked `1` Enabled
DATTEO	4	Data Timeout Error Status Enable `0` Masked `1` Enabled
CMDIDX	3	Command Index Error Status Enable `0` Masked `1` Enabled
CMDEND	2	Command End Bit Error Status Enable `0` Masked `1` Enabled
CMDCRC	1	Command CRC Error Status Enable `0` Masked `1` Enabled
CMDTEO	0	Command Timeout Error Status Enable `0` Masked `1` Enabled

NISIERNormal Interrupt Signal Enable

Address: 0x458A0038
Reset: 0x0000
Access: read/write
Size: 16-bit

10 fields

Field	Bits	What it does
BOOTAR	14	Boot Acknowledge Received Signal Enable
CINT	8	Card Interrupt Signal Enable `0` Masked `1` Enabled
CREM	7	Card Removal Signal Enable `0` Masked `1` Enabled
CINS	6	Card Insertion Signal Enable `0` Masked `1` Enabled
BRDRDY	5	Buffer Read Ready Signal Enable `0` Masked `1` Enabled
BWRRDY	4	Buffer Write Ready Signal Enable `0` Masked `1` Enabled
DMAINT	3	DMA Interrupt Signal Enable `0` Masked `1` Enabled
BLKGE	2	Block Gap Event Signal Enable `0` Masked `1` Enabled
TRFC	1	Transfer Complete Signal Enable `0` Masked `1` Enabled
CMDC	0	Command Complete Signal Enable `0` Masked `1` Enabled

EISIERError Interrupt Signal Enable

Address: 0x458A003A
Reset: 0x0000
Access: read/write
Size: 16-bit

11 fields

Field	Bits	What it does
BOOTAE	12	Boot Acknowledge Error Signal Enable
ADMA	9	ADMA Error Signal Enable `0` Masked `1` Enabled
ACMD	8	Auto CMD Error Signal Enable `0` Masked `1` Enabled
CURLIM	7	Current Limit Error Signal Enable `0` Masked `1` Enabled
DATEND	6	Data End Bit Error Signal Enable `0` Masked `1` Enabled
DATCRC	5	Data CRC Error Signal Enable `0` Masked `1` Enabled
DATTEO	4	Data Timeout Error Signal Enable `0` Masked `1` Enabled
CMDIDX	3	Command Index Error Signal Enable `0` Masked `1` Enabled
CMDEND	2	Command End Bit Error Signal Enable `0` Masked `1` Enabled
CMDCRC	1	Command CRC Error Signal Enable `0` Masked `1` Enabled
CMDTEO	0	Command Timeout Error Signal Enable `0` Masked `1` Enabled

ACESRAuto CMD Error Status

Address: 0x458A003C
Reset: 0x0000
Access: read only
Size: 16-bit

6 fields

Field	Bits	What it does
CMDNI	7	Command not Issued By Auto CMD12 Error `0` No error `1` Not Issued
ACMDIDX	4	Auto CMD Index Error `0` No error `1` Error
ACMDEND	3	Auto CMD End Bit Error `0` No error `1` End Bit Error Generated
ACMDCRC	2	Auto CMD CRC Error `0` No error `1` CRC Error Generated
ACMDTEO	1	Auto CMD Timeout Error `0` No error `1` Timeout
ACMD12NE	0	Auto CMD12 Not Executed `0` Executed `1` Not executed

HC2RHost Control 2

Address: 0x458A003E
Reset: 0x0000
Access: read/write
Size: 16-bit

8 fields

Field	Bits	What it does
PVALEN	15	Preset Value Enable `0` SDCLK and Driver Strength are controlled by Host Controller `1` Automatic Selection by Preset Value is Enabled
ASINTEN	14	Asynchronous Interrupt Enable `0` Disabled `1` Enabled
SLCKSEL	7	Sampling Clock Select `0` Fixed clock is used to sample data `1` Tuned clock is used to sample data
EXTUN	6	Execute Tuning `0` Not Tuned or Tuning Completed `1` Execute Tuning
DRVSEL	5:4	Driver Strength Select `0` Driver Type B is Selected (Default) `1` Driver Type A is Selected `2` Driver Type C is Selected `3` Driver Type D is Selected
HS200EN	3:0	HS200 Mode Enable `0` SDR12 `1` SDR25 `2` SDR50 `3` SDR104 `4` DDR50
VS18EN	3	1.8V Signaling Enable `0` 3.3V Signaling `1` 1.8V Signaling
UHSMS	2:0	UHS Mode Select `0` SDR12 `1` SDR25 `2` SDR50 `3` SDR104 `4` DDR50

CA0RCapabilities 0

Address: 0x458A0040
Reset: 0x27E8008C
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
ASINTSUP	29	Asynchronous Interrupt Support `0` Asynchronous Interrupt not Supported `1` Asynchronous Interrupt supported
SB64SUP	28	64-Bit System Bus Support `0` 32-bit Address Descriptors and System Bus `1` 64-bit Address Descriptors and System Bus
V18VSUP	26	Voltage Support 1.8V `0` 1.8V Not Supported `1` 1.8V Supported
V30VSUP	25	Voltage Support 3.0V `0` 3.0V Not Supported `1` 3.0V Supported
V33VSUP	24	Voltage Support 3.3V `0` 3.3V Not Supported `1` 3.3V Supported
SRSUP	23	Suspend/Resume Support `0` Suspend/Resume not Supported `1` Suspend/Resume Supported
SDMASUP	22	SDMA Support `0` SDMA not Supported `1` SDMA Supported
HSSUP	21	High Speed Support `0` High Speed not Supported `1` High Speed Supported
ADMA2SUP	19	ADMA2 Support `0` ADMA2 not Supported `1` ADMA2 Supported
ED8SUP	18	8-bit Support for Embedded Device `0` 8-bit Bus Width not Supported `1` 8-bit Bus Width Supported
MAXBLKL	17:16	Max Block Length `0` 512 bytes `1` 1024 bytes `2` 2048 bytes
BASECLKF	15:8	Base Clock Frequency `0` Get information via another method
TEOCLKU	7	Timeout Clock Unit `0` KHz `1` MHz
TEOCLKF	5:0	Timeout Clock Frequency `0` Get information via another method
SLTYPE	31:30	Slot Type `0` Removable Card Slot `1` Embedded Slot for One Device

CA1RCapabilities 1

Address: 0x458A0044
Reset: 0x00010070
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
CLKMULT	23:16	Clock Multiplier `0` Clock Multiplier is Not Supported
TSDR50	13	Use Tuning for SDR50 `0` SDR50 does not require tuning `1` SDR50 requires tuning
TCNTRT	11:8	Timer Count for Re-Tuning `0` Re-Tuning Timer disabled `1` 1 second `2` 2 seconds `3` 4 seconds `4` 8 seconds `5` 16 seconds `6` 32 seconds `7` 64 seconds `8` 128 seconds `9` 256 seconds `10` 512 seconds `11` 1024 seconds `15` Get information from other source
DRVDSUP	6	Driver Type D Support `0` Driver Type D is Not Supported `1` Driver Type D is Supported
DRVCSUP	5	Driver Type C Support `0` Driver Type C is Not Supported `1` Driver Type C is Supported
DRVASUP	4	Driver Type A Support `0` Driver Type A is Not Supported `1` Driver Type A is Supported
DDR50SUP	2	DDR50 Support `0` DDR50 is Not Supported `1` DDR50 is Supported
SDR104SUP	1	SDR104 Support `0` SDR104 is Not Supported `1` SDR104 is Supported
SDR50SUP	0	SDR50 Support `0` SDR50 is Not Supported `1` SDR50 is Supported

MCCARMaximum Current Capabilities

Address: 0x458A0048
Reset: 0x00000000
Access: read only
Size: 32-bit

3 fields

Field	Bits	What it does
MAXCUR18V	23:16	Maximum Current for 1.8V `0` Get information via another method `1` 4mA `2` 8mA `3` 12mA
MAXCUR30V	15:8	Maximum Current for 3.0V `0` Get information via another method `1` 4mA `2` 8mA `3` 12mA
MAXCUR33V	7:0	Maximum Current for 3.3V `0` Get information via another method `1` 4mA `2` 8mA `3` 12mA

FERACESForce Event for Auto CMD Error Status

Address: 0x458A0050
Reset: 0x0000
Access: write only
Size: 16-bit

6 fields

Field	Bits	What it does
CMDNI	7	Force Event for Command Not Issued By Auto CMD12 Error `0` No Interrupt `1` Interrupt is generated
ACMDIDX	4	Force Event for Auto CMD Index Error `0` No Interrupt `1` Interrupt is generated
ACMDEND	3	Force Event for Auto CMD End Bit Error `0` No Interrupt `1` Interrupt is generated
ACMDCRC	2	Force Event for Auto CMD CRC Error `0` No Interrupt `1` Interrupt is generated
ACMDTEO	1	Force Event for Auto CMD Timeout Error `0` No Interrupt `1` Interrupt is generated
ACMD12NE	0	Force Event for Auto CMD12 Not Executed `0` No Interrupt `1` Interrupt is generated

FEREISForce Event for Error Interrupt Status

Address: 0x458A0052
Reset: 0x0000
Access: write only
Size: 16-bit

11 fields

Field	Bits	What it does
BOOTAE	12	Force Event for Boot Acknowledge Error `0` No Interrupt `1` Interrupt is generated
ADMA	9	Force Event for ADMA Error `0` No Interrupt `1` Interrupt is generated
ACMD	8	Force Event for Auto CMD Error `0` No Interrupt `1` Interrupt is generated
CURLIM	7	Force Event for Current Limit Error `0` No Interrupt `1` Interrupt is generated
DATEND	6	Force Event for Data End Bit Error `0` No Interrupt `1` Interrupt is generated
DATCRC	5	Force Event for Data CRC Error `0` No Interrupt `1` Interrupt is generated
DATTEO	4	Force Event for Data Timeout Error `0` No Interrupt `1` Interrupt is generated
CMDIDX	3	Force Event for Command Index Error `0` No Interrupt `1` Interrupt is generated
CMDEND	2	Force Event for Command End Bit Error `0` No Interrupt `1` Interrupt is generated
CMDCRC	1	Force Event for Command CRC Error `0` No Interrupt `1` Interrupt is generated
CMDTEO	0	Force Event for Command Timeout Error `0` No Interrupt `1` Interrupt is generated

AESRADMA Error Status

Address: 0x458A0054
Reset: 0x00
Access: read only

7–
6–
5–
4–
3–
2LMIS
1ERRST1
0ERRST0

2 fields

Field	Bits	What it does
LMIS	2	ADMA Length Mismatch Error `0` No Error `1` Error
ERRST	1:0	ADMA Error State `0` ST_STOP (Stop DMA) `1` ST_FDS (Fetch Descriptor) `3` ST_TFR (Transfer Data)

ASARADMA System Address n

Address: 0x458A0058
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADMASA	31:0	ADMA System Address

PVR0Preset Value n

Address: 0x458A0060
Reset: 0x0000
Access: read/write
Size: 16-bit

3 fields

Field	Bits	What it does
DRVSEL	15:14	Driver Strength Select Value for Initialization `0` Driver Type B is Selected `1` Driver Type A is Selected `2` Driver Type C is Selected `3` Driver Type D is Selected
CLKGSEL	10	Clock Generator Select Value for Initialization `0` Host Controller Ver2.00 Compatible Clock Generator (Divider) `1` Programmable Clock Generator
SDCLKFSEL	9:0	SDCLK Frequency Select Value for Initialization

PVR1Preset Value n

Address: 0x458A0062
Reset: 0x0000
Access: read/write
Size: 16-bit

3 fields

Field	Bits	What it does
DRVSEL	15:14	Driver Strength Select Value for Initialization `0` Driver Type B is Selected `1` Driver Type A is Selected `2` Driver Type C is Selected `3` Driver Type D is Selected
CLKGSEL	10	Clock Generator Select Value for Initialization `0` Host Controller Ver2.00 Compatible Clock Generator (Divider) `1` Programmable Clock Generator
SDCLKFSEL	9:0	SDCLK Frequency Select Value for Initialization

PVR2Preset Value n

Address: 0x458A0064
Reset: 0x0000
Access: read/write
Size: 16-bit

3 fields

Field	Bits	What it does
DRVSEL	15:14	Driver Strength Select Value for Initialization `0` Driver Type B is Selected `1` Driver Type A is Selected `2` Driver Type C is Selected `3` Driver Type D is Selected
CLKGSEL	10	Clock Generator Select Value for Initialization `0` Host Controller Ver2.00 Compatible Clock Generator (Divider) `1` Programmable Clock Generator
SDCLKFSEL	9:0	SDCLK Frequency Select Value for Initialization

SISRSlot Interrupt Status

Address: 0x458A00FC
Reset: 0x0000
Access: read only
Size: 16-bit

1 field

Field	Bits	What it does
INTSSL	1:0	Interrupt Signal for Each Slot

HCVRHost Controller Version

Address: 0x458A00FE
Reset: 0x2002
Access: read only
Size: 16-bit

2 fields

Field	Bits	What it does
VVER	15:8	Vendor Version
SVER	7:0	Spec Version

MC1Re.MMC Control 1

Address: 0x458A0204
Reset: 0x00
Access: read/write

7FCD
6RSTN
5BOOTA
4OPD
3DDR
2–
1CMDTYP1
0CMDTYP0

6 fields

Field	Bits	What it does
FCD	7	e.MMC Force Card Detect
RSTN	6	e.MMC Reset Signal
BOOTA	5	e.MMC Boot Acknowledge Enable
OPD	4	e.MMC Open Drain Mode
DDR	3	e.MMC HSDDR Mode
CMDTYP	1:0	e.MMC Command Type `0` Not a MMC specific command `1` Wait IRQ Command `2` Stream Command `3` Boot Command

MC2Re.MMC Control 2

Address: 0x458A0205
Reset: 0x00
Access: write only

7–
6–
5–
4–
3–
2–
1ABOOT
0SRESP

2 fields

Field	Bits	What it does
ABOOT	1	e.MMC Abort Boot
SRESP	0	e.MMC Abort Wait IRQ

DEBRDebounce Register

Address: 0x458A0207
Reset: 0x03
Access: read/write

7–
6–
5–
4–
3–
2–
1CDDVAL1
0CDDVAL0

1 field

Field	Bits	What it does
CDDVAL	1:0	Card Detect Debounce Value `0` 1 slow clock cycle `1` 8 slow clock cycles `2` 33 slow clock cycle `3` 328 slow clock cycle

ACRAHB Control

Address: 0x458A0208
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
BMAX	1:0	AHB Maximum Burst `0` `1` `2` `3`

CC2RClock Control 2

Address: 0x458A020C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FSDCLKD	0	Force SDCK Disabled `0` No effect `1` SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled

CACRCapabilities Control

Address: 0x458A0230
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
KEY	15:8	Key (0x46)
CAPWREN	0	Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers)

DBGRDebug

Address: 0x458A0234
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
NIDBG	0	Non-intrusive debug enable `0` Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) `1` Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer)