PIC32CZ4010CA90144 MLB registers

The 35 registers of MLB (Media Local Bus), from 0x458C0000, with their reset value and every field. The PIC32CZ4010CA90144 has 5988 registers in 67 peripherals, one page each.

MLB Media Local Bus

MLB_CTRLAMLB Wrapper Control Register

Address
0x458C0000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
RUNSTDBY6Run In Standby
ENABLE1MediaLB Enable (ON) bit
SWRST0Software Reset

INTENCLRInterrupt Enable Clear Register

Address
0x458C0010
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
INT1AHB2AHB Interrupt 1 Enable Clear
INT0AHB1AHB Interrupt 0 Enable Clear
INTMLB0MLB General Interrupt Enable Clear

INTENSETInterrupt Enable Set Register

Address
0x458C0014
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
INT1AHB2AHB Interrupt 1 Enable Set
INT0AHB1AHB Interrupt 0 Enable Set
INTMLB0MLB General Interrupt Enable Set

INTFLAGInterrupt Status and Clear Register

Address
0x458C0018
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
INT1AHB2AHB Interrupt 1 Flag
INT0AHB1AHB Interrupt 0 Flag
INTMLB0MLB General Interrupt Flag

DBGCTRLDebug Control Register

Address
0x458C001C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DBGRUN0Debug Run Enable

SYNCBUSYSYNCBUSY Register

Address
0x458C0020
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
ENABLE1Module Enable Synchronization Busy
SWRST0Software Reset Synchronization Busy

MLBC0MediaLB Control 0 Register

Address
0x458C0400
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
FCNT17:15Number of frames per sub-buffer (synchronous channels)
CTLRETRY14Control Tx packet retry
ASYRETRY12Asynchronous Tx packet retry
MLBLK7MediaLB lock status (read-only)
MLBPEN5MediaLB 6-pin enable.
MLBCLK4:2MediaLB clock speed select
  • 0 256x Frame Speed
  • 1 512x Frame Speed
  • 2 1024x Frame Speed
  • 3 Only for MLBPEN==1
MLBEN0MediaLB enable

MS0MediaLB Channel Status 0 Register

Address
0x458C040C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MCS31:0MediaLB channel status (for channels 31 to 0)

MS1MediaLB Channel Status 1 Register

Address
0x458C0414
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MCS31:0MediaLB channel status (for channels 63 to 32)

MSSMediaLB System Status Register

Address
0x458C0420
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
SERVREQ5Service request enable
SWSYSCMD4Software system command detected
CSSYSCMD3Channel scan system command detected
ULKSYSCMD2Network unlock system command detected
LKSYSCMD1Network lock system command detected
RSTSYSCMD0Reset system command detected

MSDMediaLB System Data Register (Read-only)

Address
0x458C0424
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
FieldBitsWhat it does
SD223:16System data (byte 2)
SD115:8System data (byte 1)
SD07:0System data (byte 0) - LSB
SD331:24System data (byte 3) - MSB

MIENMediaLB Interrupt Enable Register

Address
0x458C042C
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
CTX_BREAK29Control Tx break enable
CTX_PE28Control Tx protocol error enable
CTX_DONE27Control Tx packet done enable
CRX_BREAK26Control Rx break enable
CRX_PE25Control Rx protocol error enable
CRX_DONE24Control Rx packet done enable
ATX_BREAK22Asynchronous Tx break enable
ATX_PE21Asynchronous Tx protocol error enable
ATX_DONE20Asynchronous Tx packet done enable
ARX_BREAK19Asynchronous Rx break enable
ARX_PE18Asynchronous Rx protocol error enable
ARX_DONE17Asynchronous Rx packet done enable
SYNC_PE16Synchronous protocol error enable
ISOC_BUFO1Isochronous Rx buffer overflow enable
ISOC_PE0Isochronous Rx protocol error enable

MLBC1MediaLB Control 1 Register

Address
0x458C043C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
NDA15:8Node device address
CLKM7MediaLB clock missing status
LOCK6MediaLB lock error status

HCTLHBI Control Register

Address
0x458C0480
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
EN15HBI enable: 1 = enabled, 0 = disabled
RST11AGU1 software reset: 1 = reset active, 0 = reset inactive
RST00AGU0 software reset: 1 = reset active, 0 = reset inactive

HCMR0HBI Channel Mask 0 Register

Address
0x458C0488
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHM31:0Bitwise channel mask bit: 0 = masked, 1 = unmasked

HCMR1HBI Channel Mask 1 Register

Address
0x458C048C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHM31:0Bitwise channel mask bit: 0 = masked, 1 = unmasked

HCER0HBI Channel Error 0 Register

Address
0x458C0490
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CERR31:0Bitwise channel error bit

HCER1HBI Channel Error 1 Register

Address
0x458C0494
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CERR31:0Bitwise channel error bit

HCBR0HBI Channel Busy 0 Register

Address
0x458C0498
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
CHB31:0Bitwise channel busy bit: 0 = idle, 1 = busy

HCBR1HBI Channel Busy 1 Register

Address
0x458C049C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
CHB31:0Bitwise channel busy bit: 0 = idle, 1 = busy

MDAT0MIF Data 0 Register

Address
0x458C04C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0CTR data - bits[31:0] of 128-bit entry or DBR data - bits[7:0] of 8-bit entry

MDAT1MIF Data 1 Register

Address
0x458C04C4
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0CTR data - bits[63:32] of 128-bit entry

MDAT2MIF Data 2 Register

Address
0x458C04C8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0CTR data - bits[95:64] of 128-bit entry

MDAT3MIF Data 3 Register

Address
0x458C04CC
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0CTR data - bits[127:96] of 128-bit entry

MDWE0MIF Data Write Enable 0 Register

Address
0x458C04D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MASK31:0Bitwise write enable for CTR data - bits[31:0] (0 = disabled, 1 = enabled)

MDWE1MIF Data Write Enable 1 Register

Address
0x458C04D4
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MASK31:0Bitwise write enable for CTR data - bits[63:32] (0 = disabled, 1 = enabled)

MDWE2MIF Data Write Enable 2 Register

Address
0x458C04D8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MASK31:0Bitwise write enable for CTR data - bits[95:64] (0 = disabled, 1 = enabled)

MDWE3MIF Data Write Enable 3 Register

Address
0x458C04DC
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
MASK31:0Bitwise write enable for CTR data - bits[127:96] (0 = disabled, 1 = enabled)

MCTLMIF Control Register

Address
0x458C04E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
XCMP0Transfer complete (write 0 to clear)

MADRMIF Address Register

Address
0x458C04E4
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
TB30Target location bit (0 = selects CTR, 1 = selects DBR)
ADDR13:0DBR address of 8-bit entry - bits[13:8].CTR address of 128-bit entry or DBR address of 8-bit entry - bits[7:0]
WNR31Write-Not-Read selection (0 = read, 1 = write)

ACTLAHB Control Register

Address
0x458C07C0
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
MPB4Packet buffering mode: 0 = single-packet mode 1 = multiple-packet mode
DMAMODE2DMA Mode: 0 = DMA Mode 0 1 = DMA Mode 1
SMX1AHB interrupt mux enable: 0 = ACSR0 generates an interrupt on ahb_int[0]; ACSR1 generates an interrupt on ahb_int[1] 1 = ACSR0 and ACSR1 generate an interrupts on ahb_int[0] only
SCE0Software clear enable: 0 = Hardware clears interrupt after a ACSRn register read 1 = Software clears interrupt

ACSR0AHB Channel Status 0 Register

Address
0x458C07D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHS31:0Interrupt status for logical channels 31 to 0: 0 = None 1 = Interrupt

ACSR1AHB Channel Status 1 Register

Address
0x458C07D4
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHS31:0Interrupt status for logical channels 63 to 32: 0 = None 1 = Interrupt

ACMR0AHB Channel Mask 0 Register

Address
0x458C07D8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHM31:0Bitwise channel mask bit:0 = Masked 1 = Unmasked

ACMR1AHB Channel Mask 1 Register

Address
0x458C07DC
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CHM31:0Bitwise channel mask bit:0 = Masked 1 = Unmasked