PIC32CZ4010CA90208 USBHS0 Registers – 164 with their bits and fields

CTRLAUSBHS Control Register A. (All bits except ENABLE and SWRST are Enable protected)

Address: 0x4F010000
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
REFCLKSEL	10	Select USB PLL Reference Clock Speed
IDOVEN	9	ID Source Select
IDVAL	8	Override Valud of ID
ENABLE	1	USBHS Enable
SWRST	0	USBHS Software Reset

CTRLBUSBHS Control Register B

Address: 0x4F010004
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
BLANK	19:0	Blank the wakeup monitoring for a specific real time `0` No blank delay `1048575` Maximum blank delay

CTRLCUSBHS Control Register C

Address: 0x4F010008
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
T1MSEN	4	REFCLK and SUSPENDM override

INTENCLRUSBHS Interrupt Enable Clear Register

Address: 0x4F01000C
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
PHYRDY	5	Clear PHYRDY Interrupt Enable
T1MS	4	Clear T1MS Interrupt Enable
DMA	3	Clear DMA Interrupt Enable
USB	2	Clear USBCORE General Interrupt Enable
RESUME	1	Clear Resume Interrupt Enable
WAKEUP	0	Clear USCORE Detaction Interrupt Enable

INTENSETUSBHS Interrupt Enable Clear Register

Address: 0x4F010010
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
PHYRDY	5	PHYRDY Interrupt Enable
T1MS	4	T1MS Interrupt Enable
DMA	3	DMA Interrupt Enable
USB	2	USBCORE General Interrupt Enable
RESUME	1	Resume Interrupt Enable
WAKEUP	0	USCORE Detaction Interrupt Enable

INTFLAGUSBHS Interrupt Flag Register

Address: 0x4F010014
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
PHYRDY	5	PHY Ready Interrupt
T1MS	4	Timer 1ms Tick Interrupt
DMA	3	DMA Interrupt
USB	2	USBCORE General Interrupt
RESUME	1	Resume Interrupt
WAKEUP	0	USB Activity Detection Interrupt

STATUSUSBHS Status Register

Address: 0x4F010018
Reset: 0x00000000
Access: read only
Size: 32-bit

3 fields

Field	Bits	What it does
VREGRDY	2	USB Voltage Regulator Status
PHYON	1	Power On of PHY Complete
PHYRDY	0	PHY Is Ready for USBCORE Activity

SYNCBUSYUSBHS Syncbusy Register

Address: 0x4F01001C
Reset: 0x00000000
Access: read only
Size: 32-bit

3 fields

Field	Bits	What it does
T1MSEN	2	T1MS enable busy bit
ENABLE	1	Enable busy bit
SWRST	0	Software reset busy bit

FADDRFunction Address Register

Address: 0x4F011000
Reset: 0x00
Access: read/write

7–
6FUNCADDR6
5FUNCADDR5
4FUNCADDR4
3FUNCADDR3
2FUNCADDR2
1FUNCADDR1
0FUNCADDR0

1 field

Field	Bits	What it does
FUNCADDR	6:0	Function address

POWERUsed For Controlling Suspend And Resume Signaling And Some Basic Operation Of USBCORE

Address: 0x4F011001
Reset: 0x20
Access: read/write

7ISOUPDATE
6SOFTCONN
5HSENABLE
4HSMODE
3RESET
2RESUME
1SUSPENDMODE
0ENABLESUSPENDM

8 fields

Field	Bits	What it does
ISOUPDATE	7	when set by cpu the usbcore will wait for an sof token
SOFTCONN	6	if enabled the D+ D- lines are enabled when this bit is set by the cpu
HSENABLE	5	when set by cpu the usbcore will negotiate the high speed mode
HSMODE	4	when set this read only bit indicates high speed mode successfully negotiated during usb reset
RESET	3	this bit is set when reset signaling is present on the bus
RESUME	2	set by cpu to generate resume signaling when te device is in suspend
SUSPENDMODE	1	set by cpu to enter suspend mode
ENABLESUSPENDM	0	set by the cpu to enable suspendm output

INTRTXRead Only Register Which Indicates Which Interrupts Are Currently Active For EP0 And TX EP1-15

Address: 0x4F011002
Reset: 0x0000
Access: read only
Size: 16-bit

8 fields

Field	Bits	What it does
EP7TX	7	Interrupts Active For TX7 Endpoint
EP6TX	6	Interrupts Active For TX6 Endpoint
EP5TX	5	Interrupts Active For TX5 Endpoint
EP4TX	4	Interrupts Active For TX4 Endpoint
EP3TX	3	Interrupts Active For TX3 Endpoint
EP2TX	2	Interrupts Active For TX2 Endpoint
EP1TX	1	Interrupts Active For TX1 Endpoint
EP0TX	0	Interrupts Active For TX0 Endpoint

INTRRXRead Only Register Which Indicates Which Interrupts Are Currently Active For RX EP1-15

Address: 0x4F011004
Reset: 0x0000
Access: read only
Size: 16-bit

7 fields

Field	Bits	What it does
EP7RX	7	Interrupts Active For Which RX7 Endpoint
EP6RX	6	Interrupts Active For Which RX6 Endpoint
EP5RX	5	Interrupts Active For Which RX5 Endpoint
EP4RX	4	Interrupts Active For Which RX4 Endpoint
EP3RX	3	Interrupts Active For Which RX3 Endpoint
EP2RX	2	Interrupts Active For Which RX2 Endpoint
EP1RX	1	Interrupts Active For Which RX1 Endpoint

INTRTXEInterrupt Enable Bits for INTRTX

Address: 0x4F011006
Reset: 0xFFFF
Access: read/write
Size: 16-bit

8 fields

Field	Bits	What it does
EP7TXEN	7	Interrupt Enabled for TX EP7
EP6TXEN	6	Interrupt Enabled for TX EP6
EP5TXEN	5	Interrupt Enabled for TX EP5
EP4TXEN	4	Interrupt Enabled for TX EP4
EP3TXEN	3	Interrupt Enabled for TX EP3
EP2TXEN	2	Interrupt Enabled for TX EP2
EP1TXEN	1	Interrupt Enabled for TX EP1
EP0TXEN	0	Interrupt Enabled for TX EP0

INTRRXEInterrupt Enable Bits for INTRRX

Address: 0x4F011008
Reset: 0xFFFE
Access: read/write
Size: 16-bit

7 fields

Field	Bits	What it does
EP7RXE	7	Interrupt Enabled for RX EP7
EP6RXE	6	Interrupt Enabled for RX EP6
EP5RXE	5	Interrupt Enabled for RX EP5
EP4RXE	4	Interrupt Enabled for RX EP4
EP3RXE	3	Interrupt Enabled for RX EP3
EP2RXE	2	Interrupt Enabled for RX EP2
EP1RXE	1	Interrupt Enabled for RX EP1

INTRUSBRead Only Register Which Indicates Which USB Interrupts Are Currently Active.

Address: 0x4F01100A
Reset: 0x00
Access: read only

7VBUSERR
6SESSREQ
5DISCON
4CONN
3SOF
2RESET
1RESUME
0SUSPEND

8 fields

Field	Bits	What it does
VBUSERR	7	Set When VBus Drops Below The VBus Valid Threshold During A Session.
SESSREQ	6	Set When Session Request Signaling Has Been Detected.
DISCON	5	Set In Host Mode When A Device Disconnect Is Detected.Set In Peripheral Mode When A Session Ends
CONN	4	Set When A Device Connection Is Detected
SOF	3	Set When A New Frame Starts
RESET	2	Set In Peripheral Mode when Reset Is Detected On The Bus. In HostMode When Babble Is Detected
RESUME	1	Set When Resume Signal Is Detected On The Bus
SUSPEND	0	Set When Suspend Signal Is Detected On The Bus

INTRUSBEInterrupt Enable Bits for USB Interrupts

Address: 0x4F01100B
Reset: 0x06
Access: read/write

7VBUSERREN
6SESSREQEN
5DISCONEN
4CONNEN
3SOFEN
2RESETEN
1RESUMEEN
0SUSPENDEN

8 fields

Field	Bits	What it does
VBUSERREN	7	VBus Error Interrupt Enable
SESSREQEN	6	SESSREQ Interrupt Enable
DISCONEN	5	DISCONN Interrupt Enable
CONNEN	4	CONN Interrupt Enable
SOFEN	3	SOF Interrupt Enable
RESETEN	2	RESET/BABBLE Interrupt Enable
RESUMEEN	1	RESUME Interrupt Enable
SUSPENDEN	0	SUSEPND Interrupt Enable

FRAMEHolds The Last Received Frame Number

Address: 0x4F01100C
Reset: 0x0000
Access: read only
Size: 16-bit

1 field

Field	Bits	What it does
FRMNUM	10:0	Frame Number

INDEXIndex Is A 4-Bit Register That Determines Which Endpoint Control/Status Registers Are Accessed

Address: 0x4F01100E
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3SELEP3
2SELEP2
1SELEP1
0SELEP0

1 field

Field	Bits	What it does
SELEP	3:0	The Selected Endpoint `0` Endpoint 0 Select `1` Endpoint 1 Select `2` Endpoint 2 Select `3` Endpoint 3 Select `4` Endpoint 4 Select `5` Endpoint 5 Select `6` Endpoint 6 Select `7` Endpoint 7 Select `8` Endpoint 8 Select

TESTMODENot Used In Normal Operation. Configuration To Put the USBCORE Into One Of The Four Test Modes For HighSpeed Operation

Address: 0x4F01100F
Reset: 0x00
Access: read/write

7FORCEHOST
6FIFOACCESS
5FORCEFS
4FORCEHS
3TESTPACKET
2TESTK
1TESTJ
0TESTSE0NAK

8 fields

Field	Bits	What it does
FORCEHOST	7	The CPU Sets This Bit To Instruct The Core To Enter Host Mode When The Session Bit Is Set
FIFOACCESS	6	The CPU Sets This Bit To Transfer The Packet In The Endpoint 0 TX FIFO To The Endpoint 0 Rx FIFO. It Is Cleared Automatically.
FORCEFS	5	Depending On Bit 7 Force Controller Into FS Speed Mode
FORCEHS	4	Depending On Bit 7 Force Controller Into High Speed Mode
TESTPACKET	3	Set To Enter The Test_Packet mode
TESTK	2	Set To Enter The Test_K mode
TESTJ	1	Set To Enter The Test_J mode
TESTSE0NAK	0	Set To Enter The Test_SE0_NAK mode

ENDPOINTX.TXMAXPENDPOINTX Maximum Amount Of Data That Can Be Transferred Through The Selected TX Endpoint In A Single Operation

Address: 0x4F011010
Reset: 0x0000
Access: read/write
Size: 16-bit

2 fields

Field	Bits	What it does
MULTIPLIER	15:11	Multiplier Value (m-1)
MAXPAYLOAD	10:0	Maximum Payload/Transactions

ENDPOINT0.CSR0LENDPOINT0 Control And Status Bits for TX Endpoint 0

Address: 0x4F011012
Reset: 0x00
Access: read/write

7NAKTIMEOUT
6SERVICEDRXPKTRDY
5REQPKT
4ERROR
3DATAEND
2RXSTALL
1TXPKTRDY
0RXPKTRDY

14 fields

Field	Bits	What it does
NAKTIMEOUT	7	This Bit Will Be Set When Endpoint 0 Is Halted Following The Receipt Of NAK Responses For Longer Than The Time Set By The NAKLimit0 register.
SERVICEDSETUPEND	7	The CPU Writes A 1 To This Bit To Clear The SetupEnd Bit. It Is Cleared Automatically.
SERVICEDRXPKTRDY	6	The CPU Writes A 1 To This Bit To Clear The RxPktRdy Bit. It Is Cleared Automatically
STATUSPKT	6	The CPU Sets This Bit At The Same Time As The TxPktRdy Or ReqPkt Bit Is Set, To Perform A Status Stage Transaction
REQPKT	5	The CPU Sets This Bit To Request An IN Transaction
SENDSTALL	5	The CPU Writes A 1 To This Bit To Terminate The Current Transaction
ERROR	4	This Bit Will Be Set When Three Attempts Have Been Made To Perform A Transaction With No Response From The Peripheral
SETUPEND	4	This Bit Will Be Set When A Control Transaction Ends Before The DataEnd Bit Has Been Set
DATAEND	3	The CPU Sets This Bit 1. When Setting TxPktRdy For The Last Data Packet 2. When Clearing RxPktRdy After Unloading The Last Data Packet.3. When Setting TxPktRdy For A Zero Length Data Packet.
SETUPPKT	3	The CPU Sets This Bit, At The Same Time As The TxPktRdy Bit Is Set, To Send A SETUP Token Instead Of An OUT Token For The Transaction
RXSTALL	2	This Bit Is Set When A Stall Handshake Is Received.
SENTSTALL	2	This Bit Is Set When A Stall Handshake Is Transmitted.
TXPKTRDY	1	The CPU Sets This Bit After Loading A Data Packet Into The FIFO.
RXPKTRDY	0	This Bit Is Set When A Data Packet Has Been Received

ENDPOINTX.TXCSRLENDPOINTX Control And Status Bits for TX Endpoints 1-15

Address: 0x4F011012
Reset: 0x00
Access: read/write

7INCOMPTX
6CLRDATATOG
5RXSTALL
4SENDSTALL
3FLUSHFIFO
2ERROR
1FIFONOTEMPTY
0TXPKTRDY

12 fields

Field	Bits	What it does
INCOMPTX	7	When The Endpoint Is Being Used For High-Bandwidth Isochronous, This Bit Is Set To Indicate Where A Large Packet Has Been Split Into 2 Or 3 Packets For Transmission But Insufficient IN Tokens Have Been Received To Send All The Parts.
NAKTIMEOUT	7	This Bit Will Be Set When Endpoint 0 Is Halted Following The Receipt Of NAK Responses For Longer Than The Time Set By The NAKLimit0 register.
CLRDATATOG	6	The CPU Writes A 1 To This Bit To Reset The Endpoint Data Toggle To 0.
RXSTALL	5	This Bit Is Set When A Stall Handshake Is Received.
SENTSTALL	5	This Bit Is Set When A Stall Handshake Is Transmitted.
SENDSTALL	4	The CPU Writes A 1 To This Bit To Issue A Stall Handshake To An In Token
SETUPPKT	4	The CPU Sets This Bit, At The Same Time As The TxPktRdy Bit Is Set, To Send A SETUP Token Instead Of An OUT Token For The Transaction
FLUSHFIFO	3	The CPU Writes A 1 To This Bit To Flush The Latest Packet From The Endpoint TX FIFO
ERROR	2	This Bit Will Be Set When Three Attempts Have Been Made To Perform A Transaction With No Response From The Peripheral
UNDERRUN	2	The USB Sets This Bit If An In Token Is Received When TxPktRdy Is Not Set.
FIFONOTEMPTY	1	The USB Sets This Bit When There Is At Least 1 Packet In The TX FIFO.
TXPKTRDY	0	The CPU Sets This Bit After Loading A Data Packet Into The FIFO.

ENDPOINT0.CSR0HENDPOINT0 Additional Control And Status Bits For TX Endpoint 0

Address: 0x4F011013
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3DISPING
2DATATOGGLEWRTENABLE
1DATATOGGLE
0FLUSHFIFO

4 fields

Field	Bits	What it does
DISPING	3	The CPU Writes A 1 To This Bit To Instruct The Core Not To Issue PING Tokens In Data And Status Phases Of A High-Speed Control Transfer
DATATOGGLEWRTENABLE	2	The CPU Writes A 1 To This Bit To Enable The Current State Of The Endpoint 0 Data Toggle To Be Written
DATATOGGLE	1	When Read, This Bit Indicates The Current State Of The Endpoint 0 Data Toggle
FLUSHFIFO	0	Flush The Next Packet To Be Transmitted/Read

ENDPOINTX.TXCSRHENDPOINTX Additional Control And Status Bits For TX Endpoints 1-15

Address: 0x4F011013
Reset: 0x00
Access: read/write

7AUTOSET
6ISO
5MODE
4DMAREQENAB
3FRCDATATOG
2DMAREQMODE
1DATATOGGLEWRENABLE
0DATATOGGLE

12 fields

Field	Bits	What it does
AUTOSET	7	If The CPU Sets This Bit, TxPktRdy Will Be Automatically Set When Data Of The Maximum P
AUTOSET	7	If The CPU Sets This Bit, TxPktRdy Will Be Automatically Set When Data Of The Maximum Packet Size Is Loaded Into The TX FIFO.
ISO	6	The CPU Sets This Bit To Enable The TX Endpoint For Isochronous Transfers
MODE	5	The CPU Sets This Bit To Enable The Endpoint Direction As TX
DMAREQENAB	4	The CPU Sets This Bit To Enable The DMA Request For The RX Endpoint
DMAREQENAB	4	The CPU Sets This Bit To Enable The DMA Request For The TX Endpoint
FRCDATATOG	3	The CPU Sets This Bit To Force The Endpoint Data Toggle To Switch And The Data Packe
FRCDATATOG	3	The CPU Sets This Bit To Force The Endpoint Data Toggle To Switch And The Data Packet To Be Cleared From The FIFO.
DMAREQMODE	2	The CPU Sets This Bit To Select DMA Request Mode
DMAREQMODE	2	The CPU Sets This Bit To Select DMA Request Mode 1 And Clears It To Select DMA Request Mode 0.
DATATOGGLEWRENABLE	1	The CPU Writes A 1 To This Bit To Enable The Current State Of The Endpoint 0 Data Toggle To Be Written
DATATOGGLE	0	When Read, This Bit Indicates The Current State Of The Endpoint

ENDPOINTX.RXMAXPENDPOINTX Maximum Amount Of Data That Can Be Transferred Through The Selected RX Endpoint In A Single Operation

Address: 0x4F011014
Reset: 0x0000
Access: read/write
Size: 16-bit

2 fields

Field	Bits	What it does
MULTIPLIER	15:11	Multiplier Value (m-1)
MAXPAYLOAD	10:0	Maximum Payload/Transactions

ENDPOINTX.RXCSRLENDPOINTX Control And Status Bits for RX Endpoint 0 Or Endpoint 1-15

Address: 0x4F011016
Reset: 0x00
Access: read/write

7CLRDATATOG
6RXSTALL
5REQPKT
4FLUSHFIFO
3DATAERROR
2ERROR
1FIFOFULL
0RXPKTRDY

13 fields

Field	Bits	What it does
CLRDATATOG	7	The CPU Writes A 1 To This Bit To Reset The Endpoint Data Toggle To 0.
RXSTALL	6	When A STALL Handshake Is Received, This Bit Is Set And An Interrupt Is Generated.
SENTSTALL	6	This Bit Is Set When A STALL Handshake Is Transmitted.
REQPKT	5	The CPU Writes A 1 To This Bit To Request An IN Transaction.
SENDSTALL	5	The CPU Writes A 1 To This Bit To Issue A STALL Handshake.
FLUSHFIFO	4	The CPU Writes A 1 To This Bit To Flush The Next Packet To Be Read From The Endpoint Rx FIFO
DATAERROR	3	This Bit Is Set When RxPktRdy Is Set If The Data Packet Has A CRC Or Bit-stuff Error.
NAKTIMEOUT	3	This Bit Is Set When RxPktRdy Is Set If The Data Packet Has A CRC Or Bit-stuff Error.
ERROR	2	The USB Sets This Bit When 3 Attempts Have Been Made To Receive A Packet And No Data Packet Has Been Received.
OVERRUN	2	This Bit Is Set If An OUT Packet Cannot Be Loaded Into The Rx FIFO.
FIFOFULL	1	This Bit Is Set When No More Packets Can Be Loaded
FIFOFULL	1	This Bit Is Set When No More Packets Can Be Loaded Into The Rx FIFO.
RXPKTRDY	0	This Bit Is Set When A Data Packet Has Been Received.

ENDPOINTX.RXCSRHENDPOINTX Additional Control And Status Bits for RX Endpoint 0 Or Endpoint 1-15

Address: 0x4F011017
Reset: 0x00
Access: read/write

7AUTOCLEAR
6AUTOREQ
5DMAREQENAB
4DISNYET
3DMAREQMODE
2DATATOGGLEWRTENABLE
1DATATOGGLE
0INCOMPRX

12 fields

Field	Bits	What it does
AUTOCLEAR	7	If The CPU Sets This Bit Then The RxPktRdy Bit Will Be Automatically Cleared Whean A Packet Of RxMaxP Bytes Has Benn Unloaded Froim The Rx FIFO
AUTOCLEAR	7	If The CPU Sets This Bit, TxPktRdy Will Be Automatically Cleared When A Packet Of RxMaxP Bytes Has Been Unloaded From The RX FIFO
AUTOREQ	6	If The CPU Sets This Bit, The ReqPkt Bit Will Be Automatically Set When The RxPktRdy Bit Is Cleared.
ISO	6	The CPU Sets This Bit To Enable the RX Endpoint For Isochronous Transfers
DMAREQENAB	5	The CPU Sets This Bit To Enable The DMA Request For The RX Endpoint
DISNYET	4	The CPU Sets This Bit To Disable The Sending Of NYET Handshakes
PIDERROR	4	Indicates A PID Error In The Received Packet
DMAREQMODE	3	The CPU Sets This Bit To Select DMA Request Mode
DATATOGGLEWRTENABLE	2	The CPU Writes A 1 To This Bit To Enable The Current State Of The Endpoint 0 Data Toggle To Be Written
DATATOGGLE	1	When Read, This Bit Indicates The Current State Of The Endpoint
INCOMPRX	0	This Bit Is Set In A High-Bandwidth Isochronous/Interrupt Transfer If The Packet In The Rx FIFO Is Incomplete
INCOMPRX	0	This Bit Is Set In A High-Bandwidth Isochronous/Interrupt Transfer If The Packet In The Rx FIFO Is Incomplete Because Parts Of The Data Were Not Received.

ENDPOINT0.COUNT0ENDPOINT0 Number Of Received Bytes In Endpoint 0 FIFO

Address: 0x4F011018
Reset: 0x00
Access: read only

7–
6EP0RXCOUNT6
5EP0RXCOUNT5
4EP0RXCOUNT4
3EP0RXCOUNT3
2EP0RXCOUNT2
1EP0RXCOUNT1
0EP0RXCOUNT0

1 field

Field	Bits	What it does
EP0RXCOUNT	6:0	Number Of Received Data Bytes In Endpoint 0 FIFO

ENDPOINTX.RXCOUNTENDPOINTX Number Of Data Bytes In The Packet Currently In Line To Be Read From The RX FIFO.

Address: 0x4F011018
Reset: 0x0000
Access: read only
Size: 16-bit

1 field

Field	Bits	What it does
ENDPOINTRXCOUNT	13:0	Number Of Data Bytes In The Packet Currently In Line To Be Read From The RX FIFO.

ENDPOINT0.TYPE0ENDPOINT0 Host Mode Only: Operating Speed Of The Targeted Device

Address: 0x4F01101A
Reset: 0x00
Access: read/write

7SPEED1
6SPEED0
5–
4–
3–
2–
1–
0–

1 field

Field	Bits	What it does
SPEED	7:6	Operating Speed Of The Target Device `1` Device In High Speed `2` Device In Full Speed `3` Device In Low Speed

ENDPOINTX.TXTYPEENDPOINTX Host Mode Only: Should Be Written With The Endpoint Number To Be Targeted By The Endpoint

Address: 0x4F01101A
Reset: 0x00
Access: read/write

7SPEED1
6SPEED0
5PROTOCOL1
4PROTOCOL0
3ENDPOINTNUMBER3
2ENDPOINTNUMBER2
1ENDPOINTNUMBER1
0ENDPOINTNUMBER0

3 fields

Field	Bits	What it does
SPEED	7:6	operating speed of the target device when the core is configured with the multipoint option: 00: unused (note: if selected, the target will be assumed to be using the same connection speed as the core.) 01: high 10: full 11: low `1` Device In High Speed `2` Device In Full Speed `3` Device In Low Speed
PROTOCOL	5:4	the cpu should set this to select the required protocol for the tx endpoint 00: control 01: isochronous 10: bulk 11: interrupt `0` `1` `2` `3`
ENDPOINTNUMBER	3:0	the cpu should set this value to the endpoint number contained in the tx endpoint descriptor

ENDPOINT0.NAKLIMIT0ENDPOINT0 Host Mode Only: Sets The NAK Response Timeout On Endpoint 0.

Address: 0x4F01101B
Reset: 0x00
Access: read/write

7–
6–
5–
4EP0NAKLIMIT4
3EP0NAKLIMIT3
2EP0NAKLIMIT2
1EP0NAKLIMIT1
0EP0NAKLIMIT0

1 field

Field	Bits	What it does
EP0NAKLIMIT	4:0	Number Of Frames/Microframes After Which Endpoint 0 Should Timeout

ENDPOINTX.TXINTERVALENDPOINTX Host Mode Only: Defines The Polling Interval For The Currently Selected TX Endpoint.

Address: 0x4F01101B
Reset: 0x00
Access: read/write

7TXPOLLINGINTERVAL7
6TXPOLLINGINTERVAL6
5TXPOLLINGINTERVAL5
4TXPOLLINGINTERVAL4
3TXPOLLINGINTERVAL3
2TXPOLLINGINTERVAL2
1TXPOLLINGINTERVAL1
0TXPOLLINGINTERVAL0

1 field

Field	Bits	What it does
TXPOLLINGINTERVAL	7:0	polling interval

ENDPOINTX.RXTYPEENDPOINTX Host Mode Only: Should Be Written With The Endpoint Number To Be Targeted By The Endpoint

Address: 0x4F01101C
Reset: 0x00
Access: read/write

7SPEED1
6SPEED0
5PROTOCOL1
4PROTOCOL0
3ENDPOINTNUMBER3
2ENDPOINTNUMBER2
1ENDPOINTNUMBER1
0ENDPOINTNUMBER0

3 fields

Field	Bits	What it does
SPEED	7:6	operating speed of the target device when the core is configured with the multipoint option: 00: unused (note: if selected, the target will be assumed to be using the same connection speed as the core.) 01: high 10: full 11: low `0` `1` `2` `3`
PROTOCOL	5:4	the cpu should set this to select the required protocol for the rx endpoint 00: control 01: isochronous 10: bulk 11: interrupt `0` `1` `2` `3`
ENDPOINTNUMBER	3:0	the cpu should set this value to the endpoint number contained in the rx endpoint descriptor returned to the musbmhdrc during device enumeration.

ENDPOINTX.RXINTERVALENDPOINTX Host Mode Only: Defines The Polling Interval For The Currently Selected RX Endpoint.

Address: 0x4F01101D
Reset: 0x00
Access: read/write

7RXPOLLINGINTERVAL7
6RXPOLLINGINTERVAL6
5RXPOLLINGINTERVAL5
4RXPOLLINGINTERVAL4
3RXPOLLINGINTERVAL3
2RXPOLLINGINTERVAL2
1RXPOLLINGINTERVAL1
0RXPOLLINGINTERVAL0

1 field

Field	Bits	What it does
RXPOLLINGINTERVAL	7:0	polling interval

ENDPOINT0.CONFIGDATAENDPOINT0 Returns Information About The Selected Core Configuration. Only Applicable when INDEX Regsiter Is 0. That Is Endpoint0 Is Selected.

Address: 0x4F01101F
Reset: 0x00
Access: read only

7MPRXE
6MPTXE
5BIGENDIAN
4HBRXE
3HBTXE
2DYNFIFOSIZING
1SOFTCONE
0UTMIDATAWIDTH

8 fields

Field	Bits	What it does
MPRXE	7	Automatic Splitting Of Bulk Amalgamation Is Selected
MPTXE	6	Automatic Splitting Of Bulk Packets Is Selected
BIGENDIAN	5	Indicates Little Endian Ordering
HBRXE	4	Indicates High Bandwidth RX ISO Endpoint Support Selected
HBTXE	3	Indicates High Bandwidth TX ISO Endpoint Support Selected
DYNFIFOSIZING	2	Dynamic FIFO Sizing Is Selected Or Not
SOFTCONE	1	Indicates Soft Connect Or Disconnect
UTMIDATAWIDTH	0	Indicates Selected UTMI+ DataWidth. Always 0 Indicates 8 Bits

ENDPOINTX.FIFOSIZEENDPOINTX Read Only Register That Returns The Sizes Of The FIFO's Associated With The Selected Additional TX/RX Endpoints. INDEX Regsiter should be set 1-15

Address: 0x4F01101F
Reset: 0x00
Access: read only

7RXFIFOSIZE3
6RXFIFOSIZE2
5RXFIFOSIZE1
4RXFIFOSIZE0
3TXFIFOSIZE3
2TXFIFOSIZE2
1TXFIFOSIZE1
0TXFIFOSIZE0

2 fields

Field	Bits	What it does
RXFIFOSIZE	7:4	Rx FIFO Size
TXFIFOSIZE	3:0	Tx FIFO Size

FIFOX0Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint

Address: 0x4F011020
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOADDR	31:0	Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint

FIFOX1Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint

Address: 0x4F011024
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOADDR	31:0	Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint

FIFOX2Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint

Address: 0x4F011028
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOADDR	31:0	Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint

FIFOX3Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint

Address: 0x4F01102C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOADDR	31:0	Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint

FIFOX4Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint

Address: 0x4F011030
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOADDR	31:0	Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint

FIFOX5Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint

Address: 0x4F011034
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOADDR	31:0	Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint

FIFOX6Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint

Address: 0x4F011038
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOADDR	31:0	Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint

FIFOX7Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint

Address: 0x4F01103C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOADDR	31:0	Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint

DEVCTLSelects Whether The Core Is Operating In Peripheral Or Host Mode

Address: 0x4F011060
Reset: 0x80
Access: read/write

7BDEVICE
6FSDEV
5LSDEV
4VBUS1
3VBUS0
2HOSTMODE
1HOSTREQ
0SESSION

7 fields

Field	Bits	What it does
BDEVICE	7	indicates whether the core is operating as a 'A' device or 'B' device
FSDEV	6	host mode only: this bit is set when a full or high speed device has been detected being connected to the port
LSDEV	5	host mode only: this bit is set when a low speed device has been detected being connected to the port
VBUS	4:3	encoded value for the VBus level `0` Below SessionEnd `1` Above SessionEnd, below AValid `2` Above AValid, below VBus Valid `3` Above VBusValid
HOSTMODE	2	this read-only bit is set when the USBCORE is acting as a host
HOSTREQ	1	when set, the USBCORE will initiate the host negotiation when suspend mode is entered.
SESSION	0	when operating as an 'A' device, this bit is set or cleared by CPU to state or end a session. when operating as a 'B' device, this bit is set/cleared by the USBCORE when a session starts/ends

MISCRX/TX Early DMA Enable Bits

Address: 0x4F011061
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1TXEDMA
0RXEDMA

2 fields

Field	Bits	What it does
TXEDMA	1	DMA_REQ signal for all IN endpoints will be deasserted based on this bit selection `0` Dma_req signal for all in endpoints will be de-asserted when maxp bytes have been written to an endpoint. this is late mode. `1` Dma_req signal for all in endpoints will be de-asserted when maxp-8 bytes have been written to an endpoint. this is early mode.
RXEDMA	0	DMA_REQ signal for all OUT endpoints will be deasserted based on this bit selection `0` Dma_req signal for all out endpoints will be de-asserted when maxp bytes have been written to an endpoint. this is late mode. `1` Dma_req signal for all out endpoints will be de-asserted when maxp-8 bytes have been written to an endpoint. this is early mode.

TXFIFOSZControls The Size Of The Selected TX Endpoint FIFO

Address: 0x4F011062
Reset: 0x00
Access: read/write

7–
6–
5–
4DPB
3SZ3
2SZ2
1SZ1
0SZ0

2 fields

Field	Bits	What it does
DPB	4	double packet buffering supported or not
SZ	3:0	maximum packet size to be allowed `0` 8 BYTES `1` 16 BYTES `2` 32 BYTES `3` 64 BYTES `4` 128 BYTES `5` 256 BYTES `6` 512 BYTES `7` 1024 BYTES `8` 2048 BYTES `9` 4096 BYTES

RXFIFOSZControls The Size Of The Selected RX Endpoint FIFO

Address: 0x4F011063
Reset: 0x00
Access: read/write

7–
6–
5–
4DPB
3SZ3
2SZ2
1SZ1
0SZ0

2 fields

Field	Bits	What it does
DPB	4	double packet buffering enabled or not
SZ	3:0	maximum packet size to be allowed `0` 8 BYTES `1` 16 BYTES `2` 32 BYTES `3` 64 BYTES `4` 128 BYTES `5` 256 BYTES `6` 512 BYTES `7` 1024 BYTES `8` 2048 BYTES `9` 4096 BYTES

TXFIFOADDControls The Start Address Of the Selected TX Endpoint FIFO

Address: 0x4F011064
Reset: 0x0000
Access: read/write
Size: 16-bit

1 field

Field	Bits	What it does
ADDR	12:0	start address of the endpoint FIFO

RXFIFOADDControls The Start Address Of the Selected RX Endpoint FIFO

Address: 0x4F011066
Reset: 0x0000
Access: read/write
Size: 16-bit

1 field

Field	Bits	What it does
ADDR	12:0	start address of the endpoint FIFO

EPINFOAllows Read-Back Of The Number Of TX And RX Endpoints

Address: 0x4F011078
Reset: 0xFF
Access: read only

7RXENDPOINTS3
6RXENDPOINTS2
5RXENDPOINTS1
4RXENDPOINTS0
3TXENDPOINTS3
2TXENDPOINTS2
1TXENDPOINTS1
0TXENDPOINTS0

2 fields

Field	Bits	What it does
RXENDPOINTS	7:4	number of rx endpoints
TXENDPOINTS	3:0	number of tx endpoints

RAMINFODetails About Width Of RAM and DMA Channels

Address: 0x4F011079
Reset: 0x8D
Access: read only

7DMACHANS3
6DMACHANS2
5DMACHANS1
4DMACHANS0
3RAMBITS3
2RAMBITS2
1RAMBITS1
0RAMBITS0

2 fields

Field	Bits	What it does
DMACHANS	7:4	number of dma channels implemented in the design
RAMBITS	3:0	width of the ram address bus

LINKINFOAllows Some Delays To Be Specified

Address: 0x4F01107A
Reset: 0x5C
Access: read/write

7WTCON3
6WTCON2
5WTCON1
4WTCON0
3WTID3
2WTID2
1WTID1
0WTID0

2 fields

Field	Bits	What it does
WTCON	7:4	sets the wait to be applied to allow for the user's connect/disconnect filter in units of 533.3ns
WTID	3:0	sets the delay to be applied from idpullup being asserted to iddig being considered valid in units of 4.369ms

VPLENSets The Duration Of The VBus Pulsing Charge

Address: 0x4F01107B
Reset: 0x3C
Access: read/write

7VPLEN7
6VPLEN6
5VPLEN5
4VPLEN4
3VPLEN3
2VPLEN2
1VPLEN1
0VPLEN0

1 field

Field	Bits	What it does
VPLEN	7:0	duration of VBus pulsing charge in units of 546.1us

HSEOF1Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For HS Transactions

Address: 0x4F01107C
Reset: 0x80
Access: read/write

7HSEOF17
6HSEOF16
5HSEOF15
4HSEOF14
3HSEOF13
2HSEOF12
1HSEOF11
0HSEOF10

1 field

Field	Bits	What it does
HSEOF1	7:0	sets for high-speed transactions the time before eof to stop beginning new transactions, in units of 133.3ns. (the default setting corresponds to 17.07us.)

FSEOF1Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For FS Transactions

Address: 0x4F01107D
Reset: 0x77
Access: read/write

7FSEOF17
6FSEOF16
5FSEOF15
4FSEOF14
3FSEOF13
2FSEOF12
1FSEOF11
0FSEOF10

1 field

Field	Bits	What it does
FSEOF1	7:0	sets for full-speed transactions the time before eof to stop beginning new transactions, in units of 533.3ns. (the default setting corresponds to 63.46us.)

LSEOF1Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For LS Transactions

Address: 0x4F01107E
Reset: 0x72
Access: read/write

7LSEOF17
6LSEOF16
5LSEOF15
4LSEOF14
3LSEOF13
2LSEOF12
1LSEOF11
0LSEOF10

1 field

Field	Bits	What it does
LSEOF1	7:0	sets for low-speed transactions the time before eof to stop beginning new transactions, in units of 1.067us. (the default setting corresponds to 121.6us.)

SOFTRSTAssert Low The Output Reset Signals NRSTO and NRSTXO

Address: 0x4F01107F
Reset: 0x00
Access: read/write

7–
6–
5–
4–
3–
2–
1NRSTX
0NRST

2 fields

Field	Bits	What it does
NRSTX	1	when a 1 is written to this bit, the output nrstxo will be asserted (low) within a minimum delay of 7 cycles of the clk input. the output nrstxo will be asynchronously asserted and synchronously de-asserted with respect to xclk.
NRST	0	when a 1 is written to this bit, the output nrsto will be asserted (low) within a minimum delay of 7 cycles of the clk input. the output nrsto will be asynchronously asserted and synchronously de-asserted with respect to clk.

TXFUNADDR0.TXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F011080
Reset: 0x00
Access: read/write

7–
6TXFUNCADDR6
5TXFUNCADDR5
4TXFUNCADDR4
3TXFUNCADDR3
2TXFUNCADDR2
1TXFUNCADDR1
0TXFUNCADDR0

1 field

Field	Bits	What it does
TXFUNCADDR	6:0	address of the target function

TXFUNADDR0.TXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F011082
Reset: 0x00
Access: read/write

7MULTRANS
6TXHUBADDR6
5TXHUBADDR5
4TXHUBADDR4
3TXHUBADDR3
2TXHUBADDR2
1TXHUBADDR1
0TXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
TXHUBADDR	6:0	hub address

TXFUNADDR0.TXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F011083
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR0.RXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F011084
Reset: 0x00
Access: read/write

7–
6RXFUNCADDR6
5RXFUNCADDR5
4RXFUNCADDR4
3RXFUNCADDR3
2RXFUNCADDR2
1RXFUNCADDR1
0RXFUNCADDR0

1 field

Field	Bits	What it does
RXFUNCADDR	6:0	address of the target function

TXFUNADDR0.RXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F011086
Reset: 0x00
Access: read/write

7MULTRANS
6RXHUBADDR6
5RXHUBADDR5
4RXHUBADDR4
3RXHUBADDR3
2RXHUBADDR2
1RXHUBADDR1
0RXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
RXHUBADDR	6:0	hub address

TXFUNADDR0.RXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F011087
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR1.TXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F011088
Reset: 0x00
Access: read/write

7–
6TXFUNCADDR6
5TXFUNCADDR5
4TXFUNCADDR4
3TXFUNCADDR3
2TXFUNCADDR2
1TXFUNCADDR1
0TXFUNCADDR0

1 field

Field	Bits	What it does
TXFUNCADDR	6:0	address of the target function

TXFUNADDR1.TXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F01108A
Reset: 0x00
Access: read/write

7MULTRANS
6TXHUBADDR6
5TXHUBADDR5
4TXHUBADDR4
3TXHUBADDR3
2TXHUBADDR2
1TXHUBADDR1
0TXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
TXHUBADDR	6:0	hub address

TXFUNADDR1.TXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F01108B
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR1.RXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F01108C
Reset: 0x00
Access: read/write

7–
6RXFUNCADDR6
5RXFUNCADDR5
4RXFUNCADDR4
3RXFUNCADDR3
2RXFUNCADDR2
1RXFUNCADDR1
0RXFUNCADDR0

1 field

Field	Bits	What it does
RXFUNCADDR	6:0	address of the target function

TXFUNADDR1.RXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F01108E
Reset: 0x00
Access: read/write

7MULTRANS
6RXHUBADDR6
5RXHUBADDR5
4RXHUBADDR4
3RXHUBADDR3
2RXHUBADDR2
1RXHUBADDR1
0RXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
RXHUBADDR	6:0	hub address

TXFUNADDR1.RXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F01108F
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR2.TXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F011090
Reset: 0x00
Access: read/write

7–
6TXFUNCADDR6
5TXFUNCADDR5
4TXFUNCADDR4
3TXFUNCADDR3
2TXFUNCADDR2
1TXFUNCADDR1
0TXFUNCADDR0

1 field

Field	Bits	What it does
TXFUNCADDR	6:0	address of the target function

TXFUNADDR2.TXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F011092
Reset: 0x00
Access: read/write

7MULTRANS
6TXHUBADDR6
5TXHUBADDR5
4TXHUBADDR4
3TXHUBADDR3
2TXHUBADDR2
1TXHUBADDR1
0TXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
TXHUBADDR	6:0	hub address

TXFUNADDR2.TXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F011093
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR2.RXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F011094
Reset: 0x00
Access: read/write

7–
6RXFUNCADDR6
5RXFUNCADDR5
4RXFUNCADDR4
3RXFUNCADDR3
2RXFUNCADDR2
1RXFUNCADDR1
0RXFUNCADDR0

1 field

Field	Bits	What it does
RXFUNCADDR	6:0	address of the target function

TXFUNADDR2.RXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F011096
Reset: 0x00
Access: read/write

7MULTRANS
6RXHUBADDR6
5RXHUBADDR5
4RXHUBADDR4
3RXHUBADDR3
2RXHUBADDR2
1RXHUBADDR1
0RXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
RXHUBADDR	6:0	hub address

TXFUNADDR2.RXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F011097
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR3.TXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F011098
Reset: 0x00
Access: read/write

7–
6TXFUNCADDR6
5TXFUNCADDR5
4TXFUNCADDR4
3TXFUNCADDR3
2TXFUNCADDR2
1TXFUNCADDR1
0TXFUNCADDR0

1 field

Field	Bits	What it does
TXFUNCADDR	6:0	address of the target function

TXFUNADDR3.TXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F01109A
Reset: 0x00
Access: read/write

7MULTRANS
6TXHUBADDR6
5TXHUBADDR5
4TXHUBADDR4
3TXHUBADDR3
2TXHUBADDR2
1TXHUBADDR1
0TXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
TXHUBADDR	6:0	hub address

TXFUNADDR3.TXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F01109B
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR3.RXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F01109C
Reset: 0x00
Access: read/write

7–
6RXFUNCADDR6
5RXFUNCADDR5
4RXFUNCADDR4
3RXFUNCADDR3
2RXFUNCADDR2
1RXFUNCADDR1
0RXFUNCADDR0

1 field

Field	Bits	What it does
RXFUNCADDR	6:0	address of the target function

TXFUNADDR3.RXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F01109E
Reset: 0x00
Access: read/write

7MULTRANS
6RXHUBADDR6
5RXHUBADDR5
4RXHUBADDR4
3RXHUBADDR3
2RXHUBADDR2
1RXHUBADDR1
0RXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
RXHUBADDR	6:0	hub address

TXFUNADDR3.RXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F01109F
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR4.TXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F0110A0
Reset: 0x00
Access: read/write

7–
6TXFUNCADDR6
5TXFUNCADDR5
4TXFUNCADDR4
3TXFUNCADDR3
2TXFUNCADDR2
1TXFUNCADDR1
0TXFUNCADDR0

1 field

Field	Bits	What it does
TXFUNCADDR	6:0	address of the target function

TXFUNADDR4.TXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F0110A2
Reset: 0x00
Access: read/write

7MULTRANS
6TXHUBADDR6
5TXHUBADDR5
4TXHUBADDR4
3TXHUBADDR3
2TXHUBADDR2
1TXHUBADDR1
0TXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
TXHUBADDR	6:0	hub address

TXFUNADDR4.TXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F0110A3
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR4.RXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F0110A4
Reset: 0x00
Access: read/write

7–
6RXFUNCADDR6
5RXFUNCADDR5
4RXFUNCADDR4
3RXFUNCADDR3
2RXFUNCADDR2
1RXFUNCADDR1
0RXFUNCADDR0

1 field

Field	Bits	What it does
RXFUNCADDR	6:0	address of the target function

TXFUNADDR4.RXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F0110A6
Reset: 0x00
Access: read/write

7MULTRANS
6RXHUBADDR6
5RXHUBADDR5
4RXHUBADDR4
3RXHUBADDR3
2RXHUBADDR2
1RXHUBADDR1
0RXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
RXHUBADDR	6:0	hub address

TXFUNADDR4.RXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F0110A7
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR5.TXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F0110A8
Reset: 0x00
Access: read/write

7–
6TXFUNCADDR6
5TXFUNCADDR5
4TXFUNCADDR4
3TXFUNCADDR3
2TXFUNCADDR2
1TXFUNCADDR1
0TXFUNCADDR0

1 field

Field	Bits	What it does
TXFUNCADDR	6:0	address of the target function

TXFUNADDR5.TXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F0110AA
Reset: 0x00
Access: read/write

7MULTRANS
6TXHUBADDR6
5TXHUBADDR5
4TXHUBADDR4
3TXHUBADDR3
2TXHUBADDR2
1TXHUBADDR1
0TXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
TXHUBADDR	6:0	hub address

TXFUNADDR5.TXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F0110AB
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR5.RXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F0110AC
Reset: 0x00
Access: read/write

7–
6RXFUNCADDR6
5RXFUNCADDR5
4RXFUNCADDR4
3RXFUNCADDR3
2RXFUNCADDR2
1RXFUNCADDR1
0RXFUNCADDR0

1 field

Field	Bits	What it does
RXFUNCADDR	6:0	address of the target function

TXFUNADDR5.RXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F0110AE
Reset: 0x00
Access: read/write

7MULTRANS
6RXHUBADDR6
5RXHUBADDR5
4RXHUBADDR4
3RXHUBADDR3
2RXHUBADDR2
1RXHUBADDR1
0RXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
RXHUBADDR	6:0	hub address

TXFUNADDR5.RXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F0110AF
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR6.TXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F0110B0
Reset: 0x00
Access: read/write

7–
6TXFUNCADDR6
5TXFUNCADDR5
4TXFUNCADDR4
3TXFUNCADDR3
2TXFUNCADDR2
1TXFUNCADDR1
0TXFUNCADDR0

1 field

Field	Bits	What it does
TXFUNCADDR	6:0	address of the target function

TXFUNADDR6.TXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F0110B2
Reset: 0x00
Access: read/write

7MULTRANS
6TXHUBADDR6
5TXHUBADDR5
4TXHUBADDR4
3TXHUBADDR3
2TXHUBADDR2
1TXHUBADDR1
0TXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
TXHUBADDR	6:0	hub address

TXFUNADDR6.TXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F0110B3
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR6.RXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F0110B4
Reset: 0x00
Access: read/write

7–
6RXFUNCADDR6
5RXFUNCADDR5
4RXFUNCADDR4
3RXFUNCADDR3
2RXFUNCADDR2
1RXFUNCADDR1
0RXFUNCADDR0

1 field

Field	Bits	What it does
RXFUNCADDR	6:0	address of the target function

TXFUNADDR6.RXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F0110B6
Reset: 0x00
Access: read/write

7MULTRANS
6RXHUBADDR6
5RXHUBADDR5
4RXHUBADDR4
3RXHUBADDR3
2RXHUBADDR2
1RXHUBADDR1
0RXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
RXHUBADDR	6:0	hub address

TXFUNADDR6.RXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F0110B7
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR7.TXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F0110B8
Reset: 0x00
Access: read/write

7–
6TXFUNCADDR6
5TXFUNCADDR5
4TXFUNCADDR4
3TXFUNCADDR3
2TXFUNCADDR2
1TXFUNCADDR1
0TXFUNCADDR0

1 field

Field	Bits	What it does
TXFUNCADDR	6:0	address of the target function

TXFUNADDR7.TXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F0110BA
Reset: 0x00
Access: read/write

7MULTRANS
6TXHUBADDR6
5TXHUBADDR5
4TXHUBADDR4
3TXHUBADDR3
2TXHUBADDR2
1TXHUBADDR1
0TXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
TXHUBADDR	6:0	hub address

TXFUNADDR7.TXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F0110BB
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

TXFUNADDR7.RXFUNCADDREPRelevant In Host Mode Only. Address Of The Target Function.

Address: 0x4F0110BC
Reset: 0x00
Access: read/write

7–
6RXFUNCADDR6
5RXFUNCADDR5
4RXFUNCADDR4
3RXFUNCADDR3
2RXFUNCADDR2
1RXFUNCADDR1
0RXFUNCADDR0

1 field

Field	Bits	What it does
RXFUNCADDR	6:0	address of the target function

TXFUNADDR7.RXHUBADDREPRelevant In Host Mode Only. HUB Address

Address: 0x4F0110BE
Reset: 0x00
Access: read/write

7MULTRANS
6RXHUBADDR6
5RXHUBADDR5
4RXHUBADDR4
3RXHUBADDR3
2RXHUBADDR2
1RXHUBADDR1
0RXHUBADDR0

2 fields

Field	Bits	What it does
MULTRANS	7	hub has multiple or single translator
RXHUBADDR	6:0	hub address

TXFUNADDR7.RXHUBPORTRelevant In Host Mode Only. HUB Address

Address: 0x4F0110BF
Reset: 0x00
Access: read/write

7–
6HUBPORT6
5HUBPORT5
4HUBPORT4
3HUBPORT3
2HUBPORT2
1HUBPORT1
0HUBPORT0

1 field

Field	Bits	What it does
HUBPORT	6:0	Hub Port

DMAINTRDMA Interrupt Status for Each Channel

Address: 0x4F011200
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMAINTR	7:0	DMA Interrupt for each channel

DMACNT0.DMACNTLDMA Transfer Control For Each Channel

Address: 0x4F011204
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	burst mode `0` Burst Mode 0 `1` Burst Mode 1 `2` Burst Mode 2 `3` Burst Mode 3
DMAERR	8	bus error bit
DMAEP	7:4	endpoint number this channel is assigned to
DMAIE	3	interrupt enable
DMAMODE	2	transfer mode `0` Mode 0 Transfer `1` Mode1 Transfer
DMADIR	1	transfer direction `0` DMA Write (RX Endpoint) `1` DMA Read (TX Endpoint)
DMAEN	0	dma transfer enable

DMACNT0.DMAADDRMemory Address Of The Corresponding DMA Channel

Address: 0x4F011208
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR10	1:0	Lower 2 bits of DMA memory address
ADDR312	31:2	upper 30 bits of address

DMACNT0.DMACOUNTCurrent DMA Count Of The Transfer

Address: 0x4F01120C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0	current dma count of the transfer

DMACNT1.DMACNTLDMA Transfer Control For Each Channel

Address: 0x4F011214
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	burst mode `0` Burst Mode 0 `1` Burst Mode 1 `2` Burst Mode 2 `3` Burst Mode 3
DMAERR	8	bus error bit
DMAEP	7:4	endpoint number this channel is assigned to
DMAIE	3	interrupt enable
DMAMODE	2	transfer mode `0` Mode 0 Transfer `1` Mode1 Transfer
DMADIR	1	transfer direction `0` DMA Write (RX Endpoint) `1` DMA Read (TX Endpoint)
DMAEN	0	dma transfer enable

DMACNT1.DMAADDRMemory Address Of The Corresponding DMA Channel

Address: 0x4F011218
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR10	1:0	Lower 2 bits of DMA memory address
ADDR312	31:2	upper 30 bits of address

DMACNT1.DMACOUNTCurrent DMA Count Of The Transfer

Address: 0x4F01121C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0	current dma count of the transfer

DMACNT2.DMACNTLDMA Transfer Control For Each Channel

Address: 0x4F011224
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	burst mode `0` Burst Mode 0 `1` Burst Mode 1 `2` Burst Mode 2 `3` Burst Mode 3
DMAERR	8	bus error bit
DMAEP	7:4	endpoint number this channel is assigned to
DMAIE	3	interrupt enable
DMAMODE	2	transfer mode `0` Mode 0 Transfer `1` Mode1 Transfer
DMADIR	1	transfer direction `0` DMA Write (RX Endpoint) `1` DMA Read (TX Endpoint)
DMAEN	0	dma transfer enable

DMACNT2.DMAADDRMemory Address Of The Corresponding DMA Channel

Address: 0x4F011228
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR10	1:0	Lower 2 bits of DMA memory address
ADDR312	31:2	upper 30 bits of address

DMACNT2.DMACOUNTCurrent DMA Count Of The Transfer

Address: 0x4F01122C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0	current dma count of the transfer

DMACNT3.DMACNTLDMA Transfer Control For Each Channel

Address: 0x4F011234
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	burst mode `0` Burst Mode 0 `1` Burst Mode 1 `2` Burst Mode 2 `3` Burst Mode 3
DMAERR	8	bus error bit
DMAEP	7:4	endpoint number this channel is assigned to
DMAIE	3	interrupt enable
DMAMODE	2	transfer mode `0` Mode 0 Transfer `1` Mode1 Transfer
DMADIR	1	transfer direction `0` DMA Write (RX Endpoint) `1` DMA Read (TX Endpoint)
DMAEN	0	dma transfer enable

DMACNT3.DMAADDRMemory Address Of The Corresponding DMA Channel

Address: 0x4F011238
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR10	1:0	Lower 2 bits of DMA memory address
ADDR312	31:2	upper 30 bits of address

DMACNT3.DMACOUNTCurrent DMA Count Of The Transfer

Address: 0x4F01123C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0	current dma count of the transfer

DMACNT4.DMACNTLDMA Transfer Control For Each Channel

Address: 0x4F011244
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	burst mode `0` Burst Mode 0 `1` Burst Mode 1 `2` Burst Mode 2 `3` Burst Mode 3
DMAERR	8	bus error bit
DMAEP	7:4	endpoint number this channel is assigned to
DMAIE	3	interrupt enable
DMAMODE	2	transfer mode `0` Mode 0 Transfer `1` Mode1 Transfer
DMADIR	1	transfer direction `0` DMA Write (RX Endpoint) `1` DMA Read (TX Endpoint)
DMAEN	0	dma transfer enable

DMACNT4.DMAADDRMemory Address Of The Corresponding DMA Channel

Address: 0x4F011248
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR10	1:0	Lower 2 bits of DMA memory address
ADDR312	31:2	upper 30 bits of address

DMACNT4.DMACOUNTCurrent DMA Count Of The Transfer

Address: 0x4F01124C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0	current dma count of the transfer

DMACNT5.DMACNTLDMA Transfer Control For Each Channel

Address: 0x4F011254
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	burst mode `0` Burst Mode 0 `1` Burst Mode 1 `2` Burst Mode 2 `3` Burst Mode 3
DMAERR	8	bus error bit
DMAEP	7:4	endpoint number this channel is assigned to
DMAIE	3	interrupt enable
DMAMODE	2	transfer mode `0` Mode 0 Transfer `1` Mode1 Transfer
DMADIR	1	transfer direction `0` DMA Write (RX Endpoint) `1` DMA Read (TX Endpoint)
DMAEN	0	dma transfer enable

DMACNT5.DMAADDRMemory Address Of The Corresponding DMA Channel

Address: 0x4F011258
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR10	1:0	Lower 2 bits of DMA memory address
ADDR312	31:2	upper 30 bits of address

DMACNT5.DMACOUNTCurrent DMA Count Of The Transfer

Address: 0x4F01125C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0	current dma count of the transfer

DMACNT6.DMACNTLDMA Transfer Control For Each Channel

Address: 0x4F011264
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	burst mode `0` Burst Mode 0 `1` Burst Mode 1 `2` Burst Mode 2 `3` Burst Mode 3
DMAERR	8	bus error bit
DMAEP	7:4	endpoint number this channel is assigned to
DMAIE	3	interrupt enable
DMAMODE	2	transfer mode `0` Mode 0 Transfer `1` Mode1 Transfer
DMADIR	1	transfer direction `0` DMA Write (RX Endpoint) `1` DMA Read (TX Endpoint)
DMAEN	0	dma transfer enable

DMACNT6.DMAADDRMemory Address Of The Corresponding DMA Channel

Address: 0x4F011268
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR10	1:0	Lower 2 bits of DMA memory address
ADDR312	31:2	upper 30 bits of address

DMACNT6.DMACOUNTCurrent DMA Count Of The Transfer

Address: 0x4F01126C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0	current dma count of the transfer

DMACNT7.DMACNTLDMA Transfer Control For Each Channel

Address: 0x4F011274
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
DMABRSTM	10:9	burst mode `0` Burst Mode 0 `1` Burst Mode 1 `2` Burst Mode 2 `3` Burst Mode 3
DMAERR	8	bus error bit
DMAEP	7:4	endpoint number this channel is assigned to
DMAIE	3	interrupt enable
DMAMODE	2	transfer mode `0` Mode 0 Transfer `1` Mode1 Transfer
DMADIR	1	transfer direction `0` DMA Write (RX Endpoint) `1` DMA Read (TX Endpoint)
DMAEN	0	dma transfer enable

DMACNT7.DMAADDRMemory Address Of The Corresponding DMA Channel

Address: 0x4F011278
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
ADDR10	1:0	Lower 2 bits of DMA memory address
ADDR312	31:2	upper 30 bits of address

DMACNT7.DMACOUNTCurrent DMA Count Of The Transfer

Address: 0x4F01127C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMACOUNT	31:0	current dma count of the transfer

RQPKTCOUNT0Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer

Address: 0x4F011304
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCOUNT	15:0	sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set.

RQPKTCOUNT1Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer

Address: 0x4F011308
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCOUNT	15:0	sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set.

RQPKTCOUNT2Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer

Address: 0x4F01130C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCOUNT	15:0	sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set.

RQPKTCOUNT3Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer

Address: 0x4F011310
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCOUNT	15:0	sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set.

RQPKTCOUNT4Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer

Address: 0x4F011314
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCOUNT	15:0	sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set.

RQPKTCOUNT5Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer

Address: 0x4F011318
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCOUNT	15:0	sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set.

RQPKTCOUNT6Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer

Address: 0x4F01131C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RQPKTCOUNT	15:0	sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set.

RXDPKTBUFDISIndicates Which Of The RX Endpoints Have Disabled Double Packet Buffer Functionality

Address: 0x4F011340
Reset: 0x0000
Access: read/write
Size: 16-bit

1 field

Field	Bits	What it does
EPxRXDIS	15:1	each bit indicates which of the Rx endpoint have disabled double buffer functionality

TXDPKTBUFDISIndicates Which Of The TX Endpoints Have Disabled Double Packet Buffer Functionality

Address: 0x4F011342
Reset: 0x0000
Access: read/write
Size: 16-bit

1 field

Field	Bits	What it does
EPxTXDIS	15:1	each bit indicates which of the Tx endpoint have disabled double buffer functionality

CTUCHChirp Timeout. Number Of XCLK Cycles Before The Timeout

Address: 0x4F011344
Reset: 0x4074
Access: read/write
Size: 16-bit

1 field

Field	Bits	What it does
CTUCH	15:0	this number when multiplied by 4 represents the number of xclk cycles before the timeout occurs

CTHHSRTNSets The Delay From The End Of High-Speed Resume Signaling (Acting As A Host) To Enable The UTM Normal Operating Mode

Address: 0x4F011346
Reset: 0x0032
Access: read/write
Size: 16-bit

1 field

Field	Bits	What it does
CTHHSRTN	15:0	the delay from the end of high speed resume signaling to enabling utm normal operating mode.

CTHSBTThis Register Represents The Value To Be Added To The Minimum High Speed Timeout Period Of 736 Bit Times.

Address: 0x4F011348
Reset: 0x0000
Access: read/write
Size: 16-bit

1 field

Field	Bits	What it does
HSTMEOUTADD	3:0	this register represents the value to be added to the mimumum high speed timeout period of 736 bit times

LPMATTRDefines The Attributes Of An LPM Transaction And Sleep Cycle.

Address: 0x4F011360
Reset: 0x0000
Access: read/write
Size: 16-bit

4 fields

Field	Bits	What it does
ENDPOINT	15:12	this is the endpnt that in the token packet of the lpm transaction.
RMTWAK	8	this bit is the remote wakeup enable bit.
HIRD	7:4	this is the host initiated resume duration.
LINKSTATE	3:0	this value is provided by the host to the peripheral to indicate what state the peripheral must transition to after the receipt and acceptance of a lpm transaction. `1` Sleep State (L1)

LPMCNTRLLPM Control Register

Address: 0x4F011362
Reset: 0x00
Access: read/write

7–
6–
5–
4LPMNAK
3LPMEN1
2LPMEN0
1LPMRES
0LPMXMT

6 fields

Field	Bits	What it does
LPMNAK	4	this bit is used to place all end points in a state such that the response to all transactions other then an lpm transaction will be a nak.
LPMEN	3:2	this register is used to enable lpm in the musbmhdrc. `0` Core supports LPM extended transactions `1` LPM is not supported but extended transactions are supported. `2` LPM and extended transactions are not supported `3` LPM and extended transactions are not supported
LPMRES	1	this bit is used by software to initiate a resume from the l1 state
LPMRES	1	this bit is used by software to initiate resume (remote wakeup).
LPMXMT	0	software should set this bit to transmit an lpm transaction.
LPMXMT	0	this bit is set by software to instruct the core to transition to the l1 state upon the receipt of the next lpm transaction.

LPMINTRENLPM Interrupts Enable Register

Address: 0x4F011363
Reset: 0x00
Access: read/write

7–
6–
5LPMERREN
4LPMRESEN
3LPMNCEN
2LPMACKEN
1LPMNYEN
0LPMSTEN

6 fields

Field	Bits	What it does
LPMERREN	5	LPMERR interrupt
LPMRESEN	4	LPMRES interrupt
LPMNCEN	3	LPMNC interrupt
LPMACKEN	2	LPMACK interrupt
LPMNYEN	1	LPMMNY interrupt
LPMSTEN	0	LPMMST interrupt

LPMINTRStatus Of The LPM Power State

Address: 0x4F011364
Reset: 0x00
Access: read/write

7–
6–
5LPMERR
4LPMRES
3LPMNC
2LPMACK
1LPMNY
0LPMST

12 fields

Field	Bits	What it does
LPMERR	5	this bit is set if a response to the lpm transaction is received with a bit stuff error or a pid error
LPMERR	5	this bit is set if an lpm transaction is received that has a linkstate field that is not supported
LPMRES	4	this bit is set if the core has been resumed for any reason.
LPMRES	4	this bit is set when the core has been resumed for any reason.
LPMNC	3	this bit is set when an lpm transaction has been transmitted and has failed to complete.
LPMNC	3	this bit is set when an lpm transaction is received and the core responds with a nyet due to data pending in the rx fifos.
LPMACK	2	this bit is set when an lpm transaction is received and the core responds with an ack.
LPMACK	2	this bit is set when an lpm transaction is transmitted and the device responds with an ack.
LPMNY	1	this bit is set when an lpm transaction is received and the core responds with a nyet
LPMNY	1	this bit is set when an lpm transaction is transmitted and the device responds with a nyet.
LPMST	0	this bit is set when an lpm transaction is received and the core responds with a stall.
LPMST	0	this bit is set when an lpm transaction is transmitted and the device responds with a stall.

LPMFADDRFunction Address In LPM Payload

Address: 0x4F011365
Reset: 0x00
Access: read/write

7–
6FUNCADDR6
5FUNCADDR5
4FUNCADDR4
3FUNCADDR3
2FUNCADDR2
1FUNCADDR1
0FUNCADDR0

1 field

Field	Bits	What it does
FUNCADDR	6:0	function address that will be placed in the LPM payload

PHY00USBHPHY Control Register.

Address: 0x4F011500
Reset: 0x00000019
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
RXPHSSEL	7:5	RX clock phase select `0` Earliest phase `7` Latest phase
SLEWRATE	4:3	adjust FS/LS slew rate `0` Highest slew rate `1` Middle slew rate `2` Middle slew rate `3` Smallest slew rate
PREEMP	2:0	enables pre-emphasis `0` Enable pre-emphasis during SOF and EOP `1` Enable pre-emphasis during chirp `2` Enable pre-emphasis in non-chirp state `3` Always enable pre-emphasis

PHY04USBHPHY Control Register.

Address: 0x4F011504
Reset: 0x0000008F
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
SQUELCH210	7:5	Lower 3 bits of RX squelch trigger point configuration
HIZ	4	Set D+/D- to a high impedence state
RSVD0	3	Reserved
TXPHSSEL	2:0	set the Tx clock phase select

PHY08USBHPHY Control Register.

Address: 0x4F011508
Reset: 0x00000007
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
RSVD0	7:1	Reserved
SQUELCH3	0	MSB of Squelch configuration

PHY0CUSBHPHY Control Register.

Address: 0x4F01150C
Reset: 0x000000E0
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
TUNE210	7:5	Lower 3 bits for HS amplitude tuning
RSVD0	4:0	Reserved

PHY10USBHPHY Control Register.

Address: 0x4F011510
Reset: 0x000000AA
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
DRVTUNE210	7:5	Lower 3 bits for HS/FS/LS driver strength tuning
TUNE76543	4:0	Upper 5 bits for HS amplitude tuning

PHY14USBHPHY Control Register.

Address: 0x4F011514
Reset: 0x00000012
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
ODT0	7	On die termination compensation voltage reference
BYPSSSQUELCH	4	Bypass squelch trigger point configure in chirp mode
COMPBYPSS	3:2	Auto compensation bypass
DRVTUNE43	1:0	Upper 2 bits for HS/FS/LS driver strength tuning

PHY18USBHPHY Control Register.

Address: 0x4F011518
Reset: 0x00000008
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
RSVD0	5:2	reserved
ODT21	1:0	Upper 3 bits for on die termination compensation voltage reference

PHY1CUSBHPHY Control Register.

Address: 0x4F01151C
Reset: 0x00000082
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
FSLSDIFF	7	Turn off FS/LS differential receiver in suspend mode
RSVD1	6:2	reserved
ODTBYPASS	1	ODT auto-refresh bypass
RSVD0	0	reserved

PHY20USBHPHY Control Register.

Address: 0x4F011520
Reset: 0x00000080
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
HSSLEW10	7:6	Lower 2 bits for HS slew adjust rate
RSVD0	5:0	Reserved

PHY24USBHPHY Control Register.

Address: 0x4F011524
Reset: 0x0000000C
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
HSDRIVST10	7:6	HS transmit drive strength
HSPREEMPST	5:3	HS transmit pre emphasis strength
RSVD0	2	Reserved
HSSLEW2	0	MSB of HS slew rate adjust

PHY28USBHPHY Control Register.

Address: 0x4F011528
Reset: 0x0000001B
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
HSDRVCOMP	7:5	HS drive current compensation voltage reference
DISCONDET	4:1	HOST disconnects detection trigger point
HSDRIVST2	0	MSB of HS transmit driver strength

PHY44USBHPHY Control Register.

Address: 0x4F011544
Reset: 0x00000040
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
FRCSESSEND	7	force session end
RSVD1	6:4	reserved
FRCVBUSVAL	3	Force output vbus_valid
DIGDBG	2	Digital debug interface
PLLDAMP	1	PLL damping factor
RSVD0	0	reserved

PHY48USBHPHY Control Register.

Address: 0x4F011548
Reset: 0x00000004
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
SESSENDTUNE	7:5	Session end reference tuning
RSVD0	4:3	reserved
VBUSCHRGE	2	VBus charging/discharging bypass
FRCBSESSVAL	1	force B_sessionvalid
FRCASESSVAL	0	force A_sessionvalid

PHY4CUSBHPHY Control Register.

Address: 0x4F01154C
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
BSESSVALIDTUNE10	7:6	Lower 2 B_sessionvalid reference tune
RSVD0	5:3	reserved
VBUSVALTUNE	2:0	VBus_valid reference tuning

PHY50USBHPHY Control Register.

Address: 0x4F011550
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
COMPCURREF	7:5	Compensation current tuning reference
RSVD0	4	reserved
ASESSVALIDTUNE	3:1	A_sessionvalid reference tune
BSESSVALIDTUNE2	0	MSB of B_sessionvalid reference tune

USBHS0 USB High Speed