PIC32CZ4010CA91176 DMA registers The 312 registers of DMA (Direct Memory Access Controller), from 0x44850000, with their reset value and every field. The PIC32CZ4010CA91176 has 6864 registers in 76 peripherals, one page each.
DMA Direct Memory Access Controller CTRLADMA CONTROL A REGISTER
Address 0x44850000
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ENABLE 1 DMA Enable
DBGCTRLDEBUG CONTROL REGISTER
Address 0x44850008
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DBGRUN 0 Debug Run
CRCPOLYADMA CRC POLYNOMIAL A REGISTER
Address 0x4485000C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does POLYA 31:0 CRC Polynomial Coefficients A Register
CRCPOLYBDMA CRC POLYNOMIAL B REGISTER
Address 0x44850010
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does POLYB 31:0 CRC Polynomial Coefficients B Register
INTSTAT4DMA INTERRUPT PRIORITY 4 STATUS REGISTER
Address 0x44850014
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does CH23 23 DMA Channel active interrupt at priority 4 CH22 22 DMA Channel active interrupt at priority 4 CH21 21 DMA Channel active interrupt at priority 4 CH20 20 DMA Channel active interrupt at priority 4 CH19 19 DMA Channel active interrupt at priority 4 CH18 18 DMA Channel active interrupt at priority 4 CH17 17 DMA Channel active interrupt at priority 4 CH16 16 DMA Channel active interrupt at priority 4 CH15 15 DMA Channel active interrupt at priority 4 CH14 14 DMA Channel active interrupt at priority 4 CH13 13 DMA Channel active interrupt at priority 4 CH12 12 DMA Channel active interrupt at priority 4 CH11 11 DMA Channel active interrupt at priority 4 CH10 10 DMA Channel active interrupt at priority 4 CH9 9 DMA Channel active interrupt at priority 4 CH8 8 DMA Channel active interrupt at priority 4 CH7 7 DMA Channel active interrupt at priority 4 CH6 6 DMA Channel active interrupt at priority 4 CH5 5 DMA Channel active interrupt at priority 4 CH4 4 DMA Channel active interrupt at priority 4 CH3 3 DMA Channel active interrupt at priority 4 CH2 2 DMA Channel active interrupt at priority 4 CH1 1 DMA Channel active interrupt at priority 4 CH0 0 DMA Channel active interrupt at priority 4
INTSTAT3DMA INTERRUPT PRIORITY 3 STATUS REGISTER
Address 0x44850018
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does CH23 23 DMA Channel active interrupt at priority 3 CH22 22 DMA Channel active interrupt at priority 3 CH21 21 DMA Channel active interrupt at priority 3 CH20 20 DMA Channel active interrupt at priority 3 CH19 19 DMA Channel active interrupt at priority 3 CH18 18 DMA Channel active interrupt at priority 3 CH17 17 DMA Channel active interrupt at priority 3 CH16 16 DMA Channel active interrupt at priority 3 CH15 15 DMA Channel active interrupt at priority 3 CH14 14 DMA Channel active interrupt at priority 3 CH13 13 DMA Channel active interrupt at priority 3 CH12 12 DMA Channel active interrupt at priority 3 CH11 11 DMA Channel active interrupt at priority 3 CH10 10 DMA Channel active interrupt at priority 3 CH9 9 DMA Channel active interrupt at priority 3 CH8 8 DMA Channel active interrupt at priority 3 CH7 7 DMA Channel active interrupt at priority 3 CH6 6 DMA Channel active interrupt at priority 3 CH5 5 DMA Channel active interrupt at priority 3 CH4 4 DMA Channel active interrupt at priority 3 CH3 3 DMA Channel active interrupt at priority 3 CH2 2 DMA Channel active interrupt at priority 3 CH1 1 DMA Channel active interrupt at priority 3 CH0 0 DMA Channel active interrupt at priority 3
INTSTAT2DMA INTERRUPT PRIORITY 2 STATUS REGISTER
Address 0x4485001C
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does CH23 23 DMA Channel active interrupt at priority 2 CH22 22 DMA Channel active interrupt at priority 2 CH21 21 DMA Channel active interrupt at priority 2 CH20 20 DMA Channel active interrupt at priority 2 CH19 19 DMA Channel active interrupt at priority 2 CH18 18 DMA Channel active interrupt at priority 2 CH17 17 DMA Channel active interrupt at priority 2 CH16 16 DMA Channel active interrupt at priority 2 CH15 15 DMA Channel active interrupt at priority 2 CH14 14 DMA Channel active interrupt at priority 2 CH13 13 DMA Channel active interrupt at priority 2 CH12 12 DMA Channel active interrupt at priority 2 CH11 11 DMA Channel active interrupt at priority 2 CH10 10 DMA Channel active interrupt at priority 2 CH9 9 DMA Channel active interrupt at priority 2 CH8 8 DMA Channel active interrupt at priority 2 CH7 7 DMA Channel active interrupt at priority 2 CH6 6 DMA Channel active interrupt at priority 2 CH5 5 DMA Channel active interrupt at priority 2 CH4 4 DMA Channel active interrupt at priority 2 CH3 3 DMA Channel active interrupt at priority 2 CH2 2 DMA Channel active interrupt at priority 2 CH1 1 DMA Channel active interrupt at priority 2 CH0 0 DMA Channel active interrupt at priority 2
INTSTAT1DMA INTERRUPT PRIORITY 1 STATUS REGISTER
Address 0x44850020
Reset 0x00000000
Access read only
Size 32-bit 24 fields
Field Bits What it does CH23 23 DMA Channel active interrupt at priority 1 CH22 22 DMA Channel active interrupt at priority 1 CH21 21 DMA Channel active interrupt at priority 1 CH20 20 DMA Channel active interrupt at priority 1 CH19 19 DMA Channel active interrupt at priority 1 CH18 18 DMA Channel active interrupt at priority 1 CH17 17 DMA Channel active interrupt at priority 1 CH16 16 DMA Channel active interrupt at priority 1 CH15 15 DMA Channel active interrupt at priority 1 CH14 14 DMA Channel active interrupt at priority 1 CH13 13 DMA Channel active interrupt at priority 1 CH12 12 DMA Channel active interrupt at priority 1 CH11 11 DMA Channel active interrupt at priority 1 CH10 10 DMA Channel active interrupt at priority 1 CH9 9 DMA Channel active interrupt at priority 1 CH8 8 DMA Channel active interrupt at priority 1 CH7 7 DMA Channel active interrupt at priority 1 CH6 6 DMA Channel active interrupt at priority 1 CH5 5 DMA Channel active interrupt at priority 1 CH4 4 DMA Channel active interrupt at priority 1 CH3 3 DMA Channel active interrupt at priority 1 CH2 2 DMA Channel active interrupt at priority 1 CH1 1 DMA Channel active interrupt at priority 1 CH0 0 DMA Channel active interrupt at priority 1
CHANNEL0.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850050
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL0.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850054
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL0.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850058
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL0.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485005C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL0.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850060
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL0.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850064
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL0.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850068
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL0.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485006C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL0.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850070
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL0.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850074
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL0.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850078
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL0.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485007C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL0.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850080
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL0.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850084
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL0.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850088
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL0.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485008C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL0.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850090
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL0.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850094
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL0.CHSTATCHANNEL STATUS REGISTER
Address 0x44850098
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL1.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448500A0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL1.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448500A4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL1.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448500A8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL1.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448500AC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL1.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448500B0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL1.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448500B4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL1.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448500B8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL1.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448500BC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL1.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448500C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL1.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448500C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL1.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448500C8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL1.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448500CC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL1.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448500D0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL1.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448500D4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL1.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448500D8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL1.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448500DC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL1.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448500E0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL1.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448500E4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL1.CHSTATCHANNEL STATUS REGISTER
Address 0x448500E8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL2.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448500F0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL2.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448500F4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL2.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448500F8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL2.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448500FC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL2.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850100
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL2.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850104
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL2.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850108
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL2.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485010C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL2.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850110
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL2.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850114
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL2.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850118
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL2.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485011C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL2.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850120
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL2.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850124
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL2.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850128
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL2.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485012C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL2.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850130
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL2.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850134
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL2.CHSTATCHANNEL STATUS REGISTER
Address 0x44850138
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL3.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850140
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL3.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850144
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL3.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850148
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL3.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485014C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL3.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850150
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL3.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850154
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL3.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850158
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL3.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485015C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL3.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850160
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL3.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850164
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL3.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850168
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL3.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485016C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL3.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850170
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL3.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850174
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL3.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850178
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL3.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485017C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL3.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850180
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL3.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850184
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL3.CHSTATCHANNEL STATUS REGISTER
Address 0x44850188
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL4.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850190
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL4.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850194
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL4.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850198
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL4.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485019C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL4.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448501A0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL4.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448501A4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL4.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448501A8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL4.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448501AC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL4.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448501B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL4.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448501B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL4.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448501B8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL4.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448501BC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL4.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448501C0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL4.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448501C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL4.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448501C8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL4.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448501CC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL4.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448501D0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL4.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448501D4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL4.CHSTATCHANNEL STATUS REGISTER
Address 0x448501D8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL5.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448501E0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL5.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448501E4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL5.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448501E8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL5.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448501EC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL5.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448501F0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL5.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448501F4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL5.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448501F8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL5.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448501FC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL5.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850200
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL5.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850204
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL5.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850208
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL5.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485020C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL5.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850210
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL5.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850214
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL5.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850218
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL5.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485021C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL5.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850220
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL5.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850224
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL5.CHSTATCHANNEL STATUS REGISTER
Address 0x44850228
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL6.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850230
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL6.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850234
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL6.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850238
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL6.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485023C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL6.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850240
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL6.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850244
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL6.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850248
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL6.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485024C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL6.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850250
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL6.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850254
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL6.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850258
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL6.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485025C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL6.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850260
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL6.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850264
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL6.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850268
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL6.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485026C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL6.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850270
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL6.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850274
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL6.CHSTATCHANNEL STATUS REGISTER
Address 0x44850278
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL7.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850280
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL7.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850284
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL7.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850288
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL7.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485028C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL7.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850290
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL7.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850294
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL7.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850298
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL7.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485029C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL7.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448502A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL7.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448502A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL7.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448502A8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL7.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448502AC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL7.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448502B0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL7.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448502B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL7.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448502B8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL7.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448502BC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL7.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448502C0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL7.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448502C4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL7.CHSTATCHANNEL STATUS REGISTER
Address 0x448502C8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL8.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448502D0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL8.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448502D4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL8.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448502D8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL8.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448502DC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL8.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448502E0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL8.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448502E4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL8.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448502E8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL8.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448502EC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL8.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448502F0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL8.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448502F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL8.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448502F8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL8.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448502FC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL8.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850300
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL8.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850304
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL8.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850308
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL8.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485030C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL8.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850310
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL8.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850314
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL8.CHSTATCHANNEL STATUS REGISTER
Address 0x44850318
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL9.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850320
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL9.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850324
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL9.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850328
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL9.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485032C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL9.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850330
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL9.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850334
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL9.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850338
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL9.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485033C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL9.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850340
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL9.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850344
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL9.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850348
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL9.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485034C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL9.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850350
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL9.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850354
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL9.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850358
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL9.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485035C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL9.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850360
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL9.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850364
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL9.CHSTATCHANNEL STATUS REGISTER
Address 0x44850368
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL10.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850370
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL10.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850374
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL10.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850378
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL10.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485037C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL10.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850380
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL10.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850384
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL10.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850388
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL10.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485038C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL10.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850390
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL10.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850394
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL10.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850398
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL10.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485039C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL10.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448503A0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL10.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448503A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL10.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448503A8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL10.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448503AC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL10.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448503B0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL10.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448503B4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL10.CHSTATCHANNEL STATUS REGISTER
Address 0x448503B8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL11.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448503C0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL11.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448503C4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL11.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448503C8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL11.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448503CC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL11.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448503D0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL11.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448503D4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL11.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448503D8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL11.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448503DC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL11.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448503E0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL11.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448503E4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL11.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448503E8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL11.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448503EC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL11.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448503F0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL11.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448503F4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL11.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448503F8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL11.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448503FC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL11.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850400
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL11.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850404
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL11.CHSTATCHANNEL STATUS REGISTER
Address 0x44850408
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL12.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850410
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL12.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850414
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL12.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850418
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL12.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485041C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL12.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850420
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL12.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850424
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL12.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850428
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL12.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485042C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL12.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850430
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL12.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850434
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL12.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850438
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL12.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485043C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL12.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850440
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL12.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850444
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL12.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850448
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL12.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485044C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL12.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850450
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL12.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850454
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL12.CHSTATCHANNEL STATUS REGISTER
Address 0x44850458
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL13.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850460
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL13.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850464
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL13.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850468
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL13.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485046C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL13.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850470
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL13.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850474
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL13.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850478
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL13.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485047C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL13.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850480
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL13.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850484
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL13.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850488
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL13.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485048C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL13.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850490
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL13.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850494
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL13.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850498
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL13.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485049C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL13.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448504A0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL13.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448504A4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL13.CHSTATCHANNEL STATUS REGISTER
Address 0x448504A8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL14.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448504B0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL14.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448504B4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL14.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448504B8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL14.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448504BC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL14.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448504C0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL14.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448504C4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL14.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448504C8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL14.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448504CC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL14.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448504D0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL14.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448504D4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL14.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448504D8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL14.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448504DC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL14.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448504E0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL14.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448504E4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL14.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448504E8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL14.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448504EC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL14.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448504F0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL14.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448504F4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL14.CHSTATCHANNEL STATUS REGISTER
Address 0x448504F8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL15.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44850500
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL15.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44850504
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE1, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 33 Channel Priority is 4 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL15.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44850508
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Bock Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger
CHANNEL15.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4485050C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL15.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44850510
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL15.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44850514
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL15.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44850518
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL15.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4485051C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL15.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44850520
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL15.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44850524
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL15.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44850528
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL15.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4485052C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL15.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44850530
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL15.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44850534
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL15.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44850538
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL15.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4485053C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL15.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44850540
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL15.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44850544
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL15.CHSTATCHANNEL STATUS REGISTER
Address 0x44850548
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
BETA