The 15 registers of SPI_IXS0 (Audio SPI with 8 channels compatibilty), from 0x46030000, with their reset value and every field. The PIC32CZ4010CA91176 has 6864 registers in 76 peripherals, one page each.
SPI_IXS0 Audio SPI with 8 channels compatibilty
CTRLASPI Control Enable Register
Address
0x46030000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
RUNSTDBY
6
RUN STANDBY Mode Enable bit
ENABLE
1
SPI Enable (ON) bit
SWRST
0
SPI Software Reset
SELCTRLSPI Control Options Select Register
Address
0x46030004
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
DATFILL
24
DATFILL undefined bits 1 or 0
TURSAMP
23
Transmit Under-run last sample sent
DATFMTLR
16
Packed data format -- left or right justified
IGNTUR
14
Ignore Transmit Underrun (for Audio Data Transmissions)
STXISEL
13:12
SPI Transmit Service Request Interrupt Select
0 TXB And SR Empty
1 TXB Empty
2 TXB Half Empty
3 TXB Not Full
CPOL
11
Clock Polarity Select bit
CPHA
10
SPI Clock Edge Select bit
IGNROV
6
Ignore Receive Overflow (for Audio Data Transmissions)
SRXISEL
5:4
SPI Receive Service Request Interrupt Select
0 RXB Empty
1 RXB Not Empty
2 RXB Half Full
3 RXB Full
CLKINDLY
1:0
Serial Clock Input Delay for SDI sampling
0 0 Tap Delays
1 1 Tap Delay
2 2 Tap Delay
3 3 Tap Delay
MODEEN
31:30
MACRO MODE ENABLED
0 Default Mode
1 Audio Mode
2 Framed Mode
3 Broadcast Mode
SPICTRLSPI Control Register
Address
0x46030008
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
SMP
10
SPI Data Input Sample Phase bit
SPISGNEXT
9
Sign Extend Read Data from the RX FIFO
MSSEN
6
Master/Slave Mode Select Enable bit
MSTEN
5
Master Mode Enable bit
DISSDO
4
Disable SDO bit
DISSDI
3
Disable SDI bit
MODE
1:0
Serial Word Length bits for AUDEN=0, not used when AUDEN=1
0 8 Bits Mode
1 16 Bits Mode
2 32 Bits Mode
FRAMECTRLSPI Control Frame Register
Address
0x4603000C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
TDMSSZ
26:24
TDM Number of Bits in a Slot Size
0 Slot Size 8
1 Slot Size 12
2 Slot Size 16
3 Slot Size 20
4 Slot Size 24
5 Slot Size 28
6 Slot Size 32
FRMCNT
20:16
Frame sync pulse counter
0 Generate a Frame sync pulse on each serial word
1 Number of slots per frame sync pulse is 2
2 Number of slots per frame sync pulse is 3
3 Number of slots per frame sync pulse is 4
4 Number of slots per frame sync pulse is 5
5 Number of slots per frame sync pulse is 6
6 Number of slots per frame sync pulse is 8
7 Number of slots per frame sync pulse is 10
8 Number of slots per frame sync pulse is 12
9 Number of slots per frame sync pulse is 14
10 Number of slots per frame sync pulse is 16
11 Number of slots per frame sync pulse is 18
12 Number of slots per frame sync pulse is 20
13 Number of slots per frame sync pulse is 22
14 Number of slots per frame sync pulse is 24
15 Number of slots per frame sync pulse is 26
16 Number of slots per frame sync pulse is 28
17 Number of slots per frame sync pulse is 30
18 Number of slots per frame sync pulse is 32
FRMSLV
14
Frame Sync Pulse Direction Control bit
FRMPOL
13
Frame Sync / Slave Select Polarity bit
FRMCOINC
8
Frame Sync Pulse Edge Select bit
FRMSYPW
3:0
Frame sync pulse width in serial words
0 Frame sync pulse is one clock wide
1 Frame sync pulse is one slots wide
2 Frame sync pulse is two slots wide
3 Frame sync pulse is three slots wide
4 Frame sync pulse is four slots wide
5 Frame sync pulse is five slots wide
6 Frame sync pulse is six slots wide
7 Frame sync pulse is seven slots wide
8 Frame sync pulse is eight slots wide
9 Frame sync pulse is sixteen slots wide
10 Frame sync pulse is thirty one slots wide
TDMWSZ
31:29
TDM Number of Bits in a Word Size
0 Word Size 8
1 Word Size 12
2 Word Size 16
3 Word Size 20
4 Word Size 24
5 Word Size 28
6 Word Size 32
AUDCTRLSPI Control Audio Register
Address
0x46030010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
AUDWDMODE
9:8
Serial Word Length bits (Ignored when AUDEN=0)
AUDFMT
6:4
Audio Protocol Format
0 Legacy I2S Mode
1 I2S Raw Audio Format
2 I2S Other AM824 Format
4 I8S Other Format
5 I8S Raw Audio Format
6 I8S Other AM824 Format
AUDMONO
3
Transmit audio data format
AUDMOD
1:0
Audio Protocol Mode
0 I2S/I8S Standard Mode
1 I2S/I8S Left Or Right Justified
3 PCM/DSP Mode
TPDCTRLSPI Control Tpd Register
Address
0x46030014
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
SLVNUM
10:8
Number of the Slave designated: to be used with the PKFMT to determine the slave.
0 SLAVE 0
1 SLAVE 1
2 SLAVE 2
3 SLAVE 3
4 SLAVE 4
PKFMT
2:0
Master Slave TPD mode.
0 32 bit data in 4x32 packed format
1 32 bit data in 3x32 packed format
2 24 bit data in 4x24 packed format
3 24 bit data in 3x24 packed format
4 16 bit data in 6x16 packed format
5 16 bit data in 4x16 packed format
6 16 bit data in 2x16 packed format
INTENSETSPI Interrupt Enable Set Register
Address
0x46030018
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
SPIROVEN
30
Enable Interrupt Events via SPIROV
SPITUREN
27
Enable Interrupt Events via SPITUR
FRMERREN
15
Enable Interrupt Events via FRMERR
SPITXBEEN
4
Enablie Interrupt Events via SPITXBE
SPIRXBFEN
0
Enablie Interrupt Events via SPIRXBF
INTENCLRSPI Interrupt Enable Clear Register
Address
0x4603001C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
SPIROVEN
30
Enable Interrupt Events via SPIROV
SPITUREN
27
Enable Interrupt Events via SPITUR
FRMERREN
15
Enable Interrupt Events via FRMERR
SPITXBEEN
4
Enablie Interrupt Events via SPITXBE
SPIRXBFEN
0
Enablie Interrupt Events via SPIRXBF
INTFLAGSPI Interrupt Flag Register
Address
0x46030020
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
SPIROV
30
Receive Overflow Status bit
SPITUR
27
Transmit Underrun Status bit
FRMERR
15
SPI Frame Error Status bit
SPITXBE
4
SPI Transmit Buffer Empty Status Bit
SPIRXBF
0
SPI Receive Buffer Full Status Bit
STATUSSPI Status Register
Address
0x46030024
Reset
0x90000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
SPIRBF
29
SPI Receive Buffer Full status bit
SPITBE
28
SPI Transmit Buffer Empty status bit
SPITBF
26
SPI Transmit Buffer Full Status bit
TXBUFELM
24:16
Transmit Buffer Element Count bits
SPIBUSY
14
SPI activity status bit
SRMT
13
Register (SR) Empty bit
RXBUFELM
8:0
Receive Buffer Element Count bits
SPIRBE
31
RX Buffer Empty bit
BUFSPI Buffer Register
Address
0x46030028
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
FIFO Data bits
BRGSPI Baud Rate Register
Address
0x4603002C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BRG
12:0
Baud Rate Divisor bits
DBGCTRLSPI Debug Control Register
Address
0x46030030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DBGRUN
0
Debug Running State
SYNCBUSYSPI Sync Busy Register
Address
0x46030034
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
SWRSTBSY
0
Software reset busy bit --- Synchronizing Busy bit for swrst
BETA