PIC32CZ5125CA70100 MATRIX registers

The 48 registers of MATRIX (AHB Bus Matrix), from 0x40088000, with their reset value and every field. The PIC32CZ5125CA70100 has 2835 registers in 63 peripherals, one page each.

MATRIX AHB Bus Matrix

MATRIX_MCFG0Master Configuration Register 0

Address
0x40088000
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG1Master Configuration Register 0

Address
0x40088004
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG2Master Configuration Register 0

Address
0x40088008
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG3Master Configuration Register 0

Address
0x4008800C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG4Master Configuration Register 0

Address
0x40088010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG5Master Configuration Register 0

Address
0x40088014
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG6Master Configuration Register 0

Address
0x40088018
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG7Master Configuration Register 0

Address
0x4008801C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG8Master Configuration Register 0

Address
0x40088020
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG9Master Configuration Register 0

Address
0x40088024
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG10Master Configuration Register 0

Address
0x40088028
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG11Master Configuration Register 0

Address
0x4008802C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_MCFG12Master Configuration Register 0

Address
0x40088030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte addr
  • 1 Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
  • 2 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
  • 3 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
  • 4 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
  • 5 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
  • 6 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
  • 7 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

MATRIX_SCFG0Slave Configuration Register 0

Address
0x40088040
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_SCFG1Slave Configuration Register 0

Address
0x40088044
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_SCFG2Slave Configuration Register 0

Address
0x40088048
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_SCFG3Slave Configuration Register 0

Address
0x4008804C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_SCFG4Slave Configuration Register 0

Address
0x40088050
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_SCFG5Slave Configuration Register 0

Address
0x40088054
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_SCFG6Slave Configuration Register 0

Address
0x40088058
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_SCFG7Slave Configuration Register 0

Address
0x4008805C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_SCFG8Slave Configuration Register 0

Address
0x40088060
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
  • 1 Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
  • 2 Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave ag
SLOT_CYCLE8:0Maximum Bus Grant Duration for Masters

MATRIX_PRAS0Priority Register A for Slave 0

Address
0x40088080
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS0Priority Register B for Slave 0

Address
0x40088084
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_PRAS1Priority Register A for Slave 0

Address
0x40088088
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS1Priority Register B for Slave 0

Address
0x4008808C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_PRAS2Priority Register A for Slave 0

Address
0x40088090
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS2Priority Register B for Slave 0

Address
0x40088094
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_PRAS3Priority Register A for Slave 0

Address
0x40088098
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS3Priority Register B for Slave 0

Address
0x4008809C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_PRAS4Priority Register A for Slave 0

Address
0x400880A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS4Priority Register B for Slave 0

Address
0x400880A4
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_PRAS5Priority Register A for Slave 0

Address
0x400880A8
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS5Priority Register B for Slave 0

Address
0x400880AC
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_PRAS6Priority Register A for Slave 0

Address
0x400880B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS6Priority Register B for Slave 0

Address
0x400880B4
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_PRAS7Priority Register A for Slave 0

Address
0x400880B8
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS7Priority Register B for Slave 0

Address
0x400880BC
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_PRAS8Priority Register A for Slave 0

Address
0x400880C0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M7PR29:28Master 7 Priority
M6PR25:24Master 6 Priority
M5PR21:20Master 5 Priority
M4PR17:16Master 4 Priority
M3PR13:12Master 3 Priority
M2PR9:8Master 2 Priority
M1PR5:4Master 1 Priority
M0PR1:0Master 0 Priority

MATRIX_PRBS8Priority Register B for Slave 0

Address
0x400880C4
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
M12PR17:16Master 12 Priority
M11PR13:12Master 11 Priority
M10PR9:8Master 10 Priority
M9PR5:4Master 9 Priority
M8PR1:0Master 8 Priority

MATRIX_MRCRMaster Remap Control Register

Address
0x40088100
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
RCB1212Remap Command Bit for Master 12
RCB1111Remap Command Bit for Master 11
RCB1010Remap Command Bit for Master 10
RCB99Remap Command Bit for Master 9
RCB88Remap Command Bit for Master 8
RCB77Remap Command Bit for Master 7
RCB66Remap Command Bit for Master 6
RCB55Remap Command Bit for Master 5
RCB44Remap Command Bit for Master 4
RCB33Remap Command Bit for Master 3
RCB22Remap Command Bit for Master 2
RCB11Remap Command Bit for Master 1
RCB00Remap Command Bit for Master 0

CCFG_CAN0CAN0 Configuration Register

Address
0x40088110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CAN0DMABA31:16CAN0 DMA Base Address

CCFG_SYSIOSystem I/O and CAN1 Configuration Register

Address
0x40088114
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
SYSIO1212PB12 or ERASE Assignment
SYSIO77PB7 or TCK/SWCLK Assignment
SYSIO66PB6 or TMS/SWDIO Assignment
SYSIO55PB5 or TDO/TRACESWO Assignment
SYSIO44PB4 or TDI Assignment
CAN1DMABA31:16CAN1 DMA Base Address

CCFG_PCCRPeripheral Clock Configuration Register

Address
0x40088118
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
I2SC1CC22I2SC1 Clock Configuration
I2SC0CC21I2SC0 Clock Configuration
TC0CC20TC0 Clock Configuration

CCFG_DYNCKGDynamic Clock Gating Register

Address
0x4008811C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
EFCCKG2EFC Dynamic Clock Gating Enable
BRIDCKG1Bridge Dynamic Clock Gating Enable
MATCKG0MATRIX Dynamic Clock Gating

CCFG_SMCNFCSSMC NAND Flash Chip Select Configuration Register

Address
0x40088124
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
SMC_NFCS33SMC NAND Flash Chip Select 3 Assignment
SMC_NFCS22SMC NAND Flash Chip Select 2 Assignment
SMC_NFCS11SMC NAND Flash Chip Select 1 Assignment
SMC_NFCS00SMC NAND Flash Chip Select 0 Assignment

MATRIX_WPMRWrite Protection Mode Register

Address
0x400881E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5062996 Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

MATRIX_WPSRWrite Protection Status Register

Address
0x400881E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC23:8Write Protection Violation Source
WPVS0Write Protection Violation Status