PIC32CZ5125CA70144 PMC registers The 44 registers of PMC (Power Management Controller), from 0x400E0600, with their reset value and every field. The PIC32CZ5125CA70144 has 2990 registers in 68 peripherals, one page each.
PMC Power Management Controller PMC_SCERSystem Clock Enable Register
Address 0x400E0600
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does PCK7 15 Programmable Clock 7 Output Enable PCK6 14 Programmable Clock 6 Output Enable PCK5 13 Programmable Clock 5 Output Enable PCK4 12 Programmable Clock 4 Output Enable PCK3 11 Programmable Clock 3 Output Enable PCK2 10 Programmable Clock 2 Output Enable PCK1 9 Programmable Clock 1 Output Enable PCK0 8 Programmable Clock 0 Output Enable USBCLK 5 Enable USB FS Clock
PMC_SCDRSystem Clock Disable Register
Address 0x400E0604
Reset 0x00000000
Access write only
Size 32-bit 9 fields
Field Bits What it does PCK7 15 Programmable Clock 7 Output Disable PCK6 14 Programmable Clock 6 Output Disable PCK5 13 Programmable Clock 5 Output Disable PCK4 12 Programmable Clock 4 Output Disable PCK3 11 Programmable Clock 3 Output Disable PCK2 10 Programmable Clock 2 Output Disable PCK1 9 Programmable Clock 1 Output Disable PCK0 8 Programmable Clock 0 Output Disable USBCLK 5 Disable USB FS Clock
PMC_SCSRSystem Clock Status Register
Address 0x400E0608
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does PCK7 15 Programmable Clock 7 Output Status PCK6 14 Programmable Clock 6 Output Status PCK5 13 Programmable Clock 5 Output Status PCK4 12 Programmable Clock 4 Output Status PCK3 11 Programmable Clock 3 Output Status PCK2 10 Programmable Clock 2 Output Status PCK1 9 Programmable Clock 1 Output Status PCK0 8 Programmable Clock 0 Output Status USBCLK 5 USB FS Clock Status HCLKS 0 HCLK Status
PMC_PCER0Peripheral Clock Enable Register 0
Address 0x400E0610
Reset 0x00000000
Access write only
Size 32-bit 25 fields
Field Bits What it does PID30 30 Peripheral Clock 30 Enable PID29 29 Peripheral Clock 29 Enable PID28 28 Peripheral Clock 28 Enable PID27 27 Peripheral Clock 27 Enable PID26 26 Peripheral Clock 26 Enable PID25 25 Peripheral Clock 25 Enable PID24 24 Peripheral Clock 24 Enable PID23 23 Peripheral Clock 23 Enable PID22 22 Peripheral Clock 22 Enable PID21 21 Peripheral Clock 21 Enable PID20 20 Peripheral Clock 20 Enable PID19 19 Peripheral Clock 19 Enable PID18 18 Peripheral Clock 18 Enable PID17 17 Peripheral Clock 17 Enable PID16 16 Peripheral Clock 16 Enable PID15 15 Peripheral Clock 15 Enable PID14 14 Peripheral Clock 14 Enable PID13 13 Peripheral Clock 13 Enable PID12 12 Peripheral Clock 12 Enable PID11 11 Peripheral Clock 11 Enable PID10 10 Peripheral Clock 10 Enable PID9 9 Peripheral Clock 9 Enable PID8 8 Peripheral Clock 8 Enable PID7 7 Peripheral Clock 7 Enable PID31 31 Peripheral Clock 31 Enable
PMC_PCDR0Peripheral Clock Disable Register 0
Address 0x400E0614
Reset 0x00000000
Access write only
Size 32-bit 25 fields
Field Bits What it does PID30 30 Peripheral Clock 30 Disable PID29 29 Peripheral Clock 29 Disable PID28 28 Peripheral Clock 28 Disable PID27 27 Peripheral Clock 27 Disable PID26 26 Peripheral Clock 26 Disable PID25 25 Peripheral Clock 25 Disable PID24 24 Peripheral Clock 24 Disable PID23 23 Peripheral Clock 23 Disable PID22 22 Peripheral Clock 22 Disable PID21 21 Peripheral Clock 21 Disable PID20 20 Peripheral Clock 20 Disable PID19 19 Peripheral Clock 19 Disable PID18 18 Peripheral Clock 18 Disable PID17 17 Peripheral Clock 17 Disable PID16 16 Peripheral Clock 16 Disable PID15 15 Peripheral Clock 15 Disable PID14 14 Peripheral Clock 14 Disable PID13 13 Peripheral Clock 13 Disable PID12 12 Peripheral Clock 12 Disable PID11 11 Peripheral Clock 11 Disable PID10 10 Peripheral Clock 10 Disable PID9 9 Peripheral Clock 9 Disable PID8 8 Peripheral Clock 8 Disable PID7 7 Peripheral Clock 7 Disable PID31 31 Peripheral Clock 31 Disable
PMC_PCSR0Peripheral Clock Status Register 0
Address 0x400E0618
Reset 0x00000000
Access read only
Size 32-bit 25 fields
Field Bits What it does PID30 30 Peripheral Clock 30 Status PID29 29 Peripheral Clock 29 Status PID28 28 Peripheral Clock 28 Status PID27 27 Peripheral Clock 27 Status PID26 26 Peripheral Clock 26 Status PID25 25 Peripheral Clock 25 Status PID24 24 Peripheral Clock 24 Status PID23 23 Peripheral Clock 23 Status PID22 22 Peripheral Clock 22 Status PID21 21 Peripheral Clock 21 Status PID20 20 Peripheral Clock 20 Status PID19 19 Peripheral Clock 19 Status PID18 18 Peripheral Clock 18 Status PID17 17 Peripheral Clock 17 Status PID16 16 Peripheral Clock 16 Status PID15 15 Peripheral Clock 15 Status PID14 14 Peripheral Clock 14 Status PID13 13 Peripheral Clock 13 Status PID12 12 Peripheral Clock 12 Status PID11 11 Peripheral Clock 11 Status PID10 10 Peripheral Clock 10 Status PID9 9 Peripheral Clock 9 Status PID8 8 Peripheral Clock 8 Status PID7 7 Peripheral Clock 7 Status PID31 31 Peripheral Clock 31 Status
CKGR_UCKRUTMI Clock Register
Address 0x400E061C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does UPLLCOUNT 23:20 UTMI PLL Start-up Time UPLLEN 16 UTMI PLL Enable
CKGR_MORMain Oscillator Register
Address 0x400E0620
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does XT32KFME 26 32.768 kHz Crystal Oscillator Frequency Monitoring Enable CFDEN 25 Clock Failure Detector Enable MOSCSEL 24 Main Clock Oscillator Selection KEY 23:16 Write Access Password55 Writing any other value in this field aborts the write operation.Always reads as 0. MOSCXTST 15:8 Main Crystal Oscillator Startup Time MOSCRCF 6:4 Main RC Oscillator Frequency Selection0 The RC oscillator frequency is at 4 MHz1 The RC oscillator frequency is at 8 MHz2 The RC oscillator frequency is at 12 MHz MOSCRCEN 3 Main RC Oscillator Enable WAITMODE 2 Wait Mode Command (Write-only) MOSCXTBY 1 Main Crystal Oscillator Bypass MOSCXTEN 0 Main Crystal Oscillator Enable
CKGR_MCFRMain Clock Frequency Register
Address 0x400E0624
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does CCSS 24 Counter Clock Source Selection RCMEAS 20 RC Oscillator Frequency Measure (write-only) MAINFRDY 16 Main Clock Frequency Measure Ready MAINF 15:0 Main Clock Frequency
CKGR_PLLARPLLA Register
Address 0x400E0628
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does ONE 29 Must Be Set to 1 MULA 26:16 PLLA Multiplier PLLACOUNT 13:8 PLLA Counter DIVA 7:0 PLLA Front End Divider0 Divider output is 0 and PLLA is disabled.1 Divider is bypassed (divide by 1) and PLLA is enabled.
PMC_MCKRMaster Clock Register
Address 0x400E0630
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does UPLLDIV2 13 UPLL Divider by 2 MDIV 9:8 Master Clock Division0 Master Clock is Prescaler Output Clock divided by 1.1 Master Clock is Prescaler Output Clock divided by 2.2 Master Clock is Prescaler Output Clock divided by 4.3 Master Clock is Prescaler Output Clock divided by 3. PRES 6:4 Processor Clock Prescaler0 Selected clock1 Selected clock divided by 22 Selected clock divided by 43 Selected clock divided by 84 Selected clock divided by 165 Selected clock divided by 326 Selected clock divided by 647 Selected clock divided by 3 CSS 1:0 Master Clock Source Selection0 Slow Clock is selected1 Main Clock is selected2 PLLA Clock is selected3 Divided UPLL Clock is selected
PMC_USBUSB Clock Register
Address 0x400E0638
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does USBDIV 11:8 Divider for USB_48M USBS 0 USB Input Clock Selection
PMC_PCK0Programmable Clock Register
Address 0x400E0640
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PRES 11:4 Programmable Clock Prescaler CSS 2:0 Programmable Clock Source Selection0 SLCK is selected1 MAINCK is selected2 PLLACK is selected3 UPLLCKDIV is selected4 MCK is selected
PMC_PCK1Programmable Clock Register
Address 0x400E0644
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PRES 11:4 Programmable Clock Prescaler CSS 2:0 Programmable Clock Source Selection0 SLCK is selected1 MAINCK is selected2 PLLACK is selected3 UPLLCKDIV is selected4 MCK is selected
PMC_PCK2Programmable Clock Register
Address 0x400E0648
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PRES 11:4 Programmable Clock Prescaler CSS 2:0 Programmable Clock Source Selection0 SLCK is selected1 MAINCK is selected2 PLLACK is selected3 UPLLCKDIV is selected4 MCK is selected
PMC_PCK3Programmable Clock Register
Address 0x400E064C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PRES 11:4 Programmable Clock Prescaler CSS 2:0 Programmable Clock Source Selection0 SLCK is selected1 MAINCK is selected2 PLLACK is selected3 UPLLCKDIV is selected4 MCK is selected
PMC_PCK4Programmable Clock Register
Address 0x400E0650
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PRES 11:4 Programmable Clock Prescaler CSS 2:0 Programmable Clock Source Selection0 SLCK is selected1 MAINCK is selected2 PLLACK is selected3 UPLLCKDIV is selected4 MCK is selected
PMC_PCK5Programmable Clock Register
Address 0x400E0654
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PRES 11:4 Programmable Clock Prescaler CSS 2:0 Programmable Clock Source Selection0 SLCK is selected1 MAINCK is selected2 PLLACK is selected3 UPLLCKDIV is selected4 MCK is selected
PMC_PCK6Programmable Clock Register
Address 0x400E0658
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PRES 11:4 Programmable Clock Prescaler CSS 2:0 Programmable Clock Source Selection0 SLCK is selected1 MAINCK is selected2 PLLACK is selected3 UPLLCKDIV is selected4 MCK is selected
PMC_PCK7Programmable Clock Register
Address 0x400E065C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PRES 11:4 Programmable Clock Prescaler CSS 2:0 Programmable Clock Source Selection0 SLCK is selected1 MAINCK is selected2 PLLACK is selected3 UPLLCKDIV is selected4 MCK is selected
PMC_IERInterrupt Enable Register
Address 0x400E0660
Reset 0x00000000
Access write only
Size 32-bit 16 fields
Field Bits What it does XT32KERR 21 32.768 kHz Crystal Oscillator Error Interrupt Enable CFDEV 18 Clock Failure Detector Event Interrupt Enable MOSCRCS 17 Main RC Oscillator Status Interrupt Enable MOSCSELS 16 Main Clock Source Oscillator Selection Status Interrupt Enable PCKRDY7 15 Programmable Clock Ready 7 Interrupt Enable PCKRDY6 14 Programmable Clock Ready 6 Interrupt Enable PCKRDY5 13 Programmable Clock Ready 5 Interrupt Enable PCKRDY4 12 Programmable Clock Ready 4 Interrupt Enable PCKRDY3 11 Programmable Clock Ready 3 Interrupt Enable PCKRDY2 10 Programmable Clock Ready 2 Interrupt Enable PCKRDY1 9 Programmable Clock Ready 1 Interrupt Enable PCKRDY0 8 Programmable Clock Ready 0 Interrupt Enable LOCKU 6 UTMI PLL Lock Interrupt Enable MCKRDY 3 Master Clock Ready Interrupt Enable LOCKA 1 PLLA Lock Interrupt Enable MOSCXTS 0 Main Crystal Oscillator Status Interrupt Enable
PMC_IDRInterrupt Disable Register
Address 0x400E0664
Reset 0x00000000
Access write only
Size 32-bit 16 fields
Field Bits What it does XT32KERR 21 32.768 kHz Crystal Oscillator Error Interrupt Disable CFDEV 18 Clock Failure Detector Event Interrupt Disable MOSCRCS 17 Main RC Status Interrupt Disable MOSCSELS 16 Main Clock Source Oscillator Selection Status Interrupt Disable PCKRDY7 15 Programmable Clock Ready 7 Interrupt Disable PCKRDY6 14 Programmable Clock Ready 6 Interrupt Disable PCKRDY5 13 Programmable Clock Ready 5 Interrupt Disable PCKRDY4 12 Programmable Clock Ready 4 Interrupt Disable PCKRDY3 11 Programmable Clock Ready 3 Interrupt Disable PCKRDY2 10 Programmable Clock Ready 2 Interrupt Disable PCKRDY1 9 Programmable Clock Ready 1 Interrupt Disable PCKRDY0 8 Programmable Clock Ready 0 Interrupt Disable LOCKU 6 UTMI PLL Lock Interrupt Disable MCKRDY 3 Master Clock Ready Interrupt Disable LOCKA 1 PLLA Lock Interrupt Disable MOSCXTS 0 Main Crystal Oscillator Status Interrupt Disable
PMC_SRStatus Register
Address 0x400E0668
Reset 0x00000000
Access read only
Size 32-bit 19 fields
Field Bits What it does XT32KERR 21 Slow Crystal Oscillator Error FOS 20 Clock Failure Detector Fault Output Status CFDS 19 Clock Failure Detector Status CFDEV 18 Clock Failure Detector Event MOSCRCS 17 Main RC Oscillator Status MOSCSELS 16 Main Clock Source Oscillator Selection Status PCKRDY7 15 Programmable Clock Ready 7 Status PCKRDY6 14 Programmable Clock Ready 6 Status PCKRDY5 13 Programmable Clock Ready 5 Status PCKRDY4 12 Programmable Clock Ready 4 Status PCKRDY3 11 Programmable Clock Ready 3 Status PCKRDY2 10 Programmable Clock Ready 2 Status PCKRDY1 9 Programmable Clock Ready 1 Status PCKRDY0 8 Programmable Clock Ready 0 Status OSCSELS 7 Slow Clock Source Oscillator Selection LOCKU 6 UTMI PLL Lock Status MCKRDY 3 Master Clock Status LOCKA 1 PLLA Lock Status MOSCXTS 0 Main Crystal Oscillator Status
PMC_IMRInterrupt Mask Register
Address 0x400E066C
Reset 0x00000000
Access read only
Size 32-bit 16 fields
Field Bits What it does XT32KERR 21 32.768 kHz Crystal Oscillator Error Interrupt Mask CFDEV 18 Clock Failure Detector Event Interrupt Mask MOSCRCS 17 Main RC Status Interrupt Mask MOSCSELS 16 Main Clock Source Oscillator Selection Status Interrupt Mask PCKRDY7 15 Programmable Clock Ready 7 Interrupt Mask PCKRDY6 14 Programmable Clock Ready 6 Interrupt Mask PCKRDY5 13 Programmable Clock Ready 5 Interrupt Mask PCKRDY4 12 Programmable Clock Ready 4 Interrupt Mask PCKRDY3 11 Programmable Clock Ready 3 Interrupt Mask PCKRDY2 10 Programmable Clock Ready 2 Interrupt Mask PCKRDY1 9 Programmable Clock Ready 1 Interrupt Mask PCKRDY0 8 Programmable Clock Ready 0 Interrupt Mask LOCKU 6 UTMI PLL Lock Interrupt Mask MCKRDY 3 Master Clock Ready Interrupt Mask LOCKA 1 PLLA Lock Interrupt Mask MOSCXTS 0 Main Crystal Oscillator Status Interrupt Mask
PMC_FSMRFast Startup Mode Register
Address 0x400E0670
Reset 0x00000000
Access read/write
Size 32-bit 22 fields
Field Bits What it does FFLPM 23 Force Flash Low-power Mode FLPM 22:21 Flash Low-power Mode0 Flash is in Standby Mode when system enters Wait Mode1 Flash is in Deep-power-down mode when system enters Wait Mode2 Idle mode LPM 20 Low-power Mode USBAL 18 USB Alarm Enable RTCAL 17 RTC Alarm Enable RTTAL 16 RTT Alarm Enable FSTT15 15 Fast Startup Input Enable 15 FSTT14 14 Fast Startup Input Enable 14 FSTT13 13 Fast Startup Input Enable 13 FSTT12 12 Fast Startup Input Enable 12 FSTT11 11 Fast Startup Input Enable 11 FSTT10 10 Fast Startup Input Enable 10 FSTT9 9 Fast Startup Input Enable 9 FSTT8 8 Fast Startup Input Enable 8 FSTT7 7 Fast Startup Input Enable 7 FSTT6 6 Fast Startup Input Enable 6 FSTT5 5 Fast Startup Input Enable 5 FSTT4 4 Fast Startup Input Enable 4 FSTT3 3 Fast Startup Input Enable 3 FSTT2 2 Fast Startup Input Enable 2 FSTT1 1 Fast Startup Input Enable 1 FSTT0 0 Fast Startup Input Enable 0
PMC_FSPRFast Startup Polarity Register
Address 0x400E0674
Reset 0x00000000
Access read/write
Size 32-bit 16 fields
Field Bits What it does FSTP15 15 Fast Startup Input Polarity 15 FSTP14 14 Fast Startup Input Polarity 14 FSTP13 13 Fast Startup Input Polarity 13 FSTP12 12 Fast Startup Input Polarity 12 FSTP11 11 Fast Startup Input Polarity 11 FSTP10 10 Fast Startup Input Polarity 10 FSTP9 9 Fast Startup Input Polarity 9 FSTP8 8 Fast Startup Input Polarity 8 FSTP7 7 Fast Startup Input Polarity 7 FSTP6 6 Fast Startup Input Polarity 6 FSTP5 5 Fast Startup Input Polarity 5 FSTP4 4 Fast Startup Input Polarity 4 FSTP3 3 Fast Startup Input Polarity 3 FSTP2 2 Fast Startup Input Polarity 2 FSTP1 1 Fast Startup Input Polarity 1 FSTP0 0 Fast Startup Input Polarity 0
PMC_FOCRFault Output Clear Register
Address 0x400E0678
Reset 0x00000000
Access write only
Size 32-bit 1 field
Field Bits What it does FOCLR 0 Fault Output Clear
PMC_WPMRWrite Protection Mode Register
Address 0x400E06E4
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does WPEN 0 Write Protection Enable WPKEY 31:8 Write Protection Key5262659 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
PMC_WPSRWrite Protection Status Register
Address 0x400E06E8
Reset 0x00000000
Access read only
Size 32-bit 2 fields
Field Bits What it does WPVSRC 23:8 Write Protection Violation Source WPVS 0 Write Protection Violation Status
PMC_PCER1Peripheral Clock Enable Register 1
Address 0x400E0700
Reset 0x00000000
Access write only
Size 32-bit 25 fields
Field Bits What it does PID60 28 Peripheral Clock 60 Enable PID59 27 Peripheral Clock 59 Enable PID58 26 Peripheral Clock 58 Enable PID57 25 Peripheral Clock 57 Enable PID56 24 Peripheral Clock 56 Enable PID53 21 Peripheral Clock 53 Enable PID52 20 Peripheral Clock 52 Enable PID51 19 Peripheral Clock 51 Enable PID50 18 Peripheral Clock 50 Enable PID49 17 Peripheral Clock 49 Enable PID48 16 Peripheral Clock 48 Enable PID47 15 Peripheral Clock 47 Enable PID46 14 Peripheral Clock 46 Enable PID45 13 Peripheral Clock 45 Enable PID44 12 Peripheral Clock 44 Enable PID43 11 Peripheral Clock 43 Enable PID42 10 Peripheral Clock 42 Enable PID41 9 Peripheral Clock 41 Enable PID40 8 Peripheral Clock 40 Enable PID39 7 Peripheral Clock 39 Enable PID37 5 Peripheral Clock 37 Enable PID35 3 Peripheral Clock 35 Enable PID34 2 Peripheral Clock 34 Enable PID33 1 Peripheral Clock 33 Enable PID32 0 Peripheral Clock 32 Enable
PMC_PCDR1Peripheral Clock Disable Register 1
Address 0x400E0704
Reset 0x00000000
Access write only
Size 32-bit 25 fields
Field Bits What it does PID60 28 Peripheral Clock 60 Disable PID59 27 Peripheral Clock 59 Disable PID58 26 Peripheral Clock 58 Disable PID57 25 Peripheral Clock 57 Disable PID56 24 Peripheral Clock 56 Disable PID53 21 Peripheral Clock 53 Disable PID52 20 Peripheral Clock 52 Disable PID51 19 Peripheral Clock 51 Disable PID50 18 Peripheral Clock 50 Disable PID49 17 Peripheral Clock 49 Disable PID48 16 Peripheral Clock 48 Disable PID47 15 Peripheral Clock 47 Disable PID46 14 Peripheral Clock 46 Disable PID45 13 Peripheral Clock 45 Disable PID44 12 Peripheral Clock 44 Disable PID43 11 Peripheral Clock 43 Disable PID42 10 Peripheral Clock 42 Disable PID41 9 Peripheral Clock 41 Disable PID40 8 Peripheral Clock 40 Disable PID39 7 Peripheral Clock 39 Disable PID37 5 Peripheral Clock 37 Disable PID35 3 Peripheral Clock 35 Disable PID34 2 Peripheral Clock 34 Disable PID33 1 Peripheral Clock 33 Disable PID32 0 Peripheral Clock 32 Disable
PMC_PCSR1Peripheral Clock Status Register 1
Address 0x400E0708
Reset 0x00000000
Access read only
Size 32-bit 25 fields
Field Bits What it does PID60 28 Peripheral Clock 60 Status PID59 27 Peripheral Clock 59 Status PID58 26 Peripheral Clock 58 Status PID57 25 Peripheral Clock 57 Status PID56 24 Peripheral Clock 56 Status PID53 21 Peripheral Clock 53 Status PID52 20 Peripheral Clock 52 Status PID51 19 Peripheral Clock 51 Status PID50 18 Peripheral Clock 50 Status PID49 17 Peripheral Clock 49 Status PID48 16 Peripheral Clock 48 Status PID47 15 Peripheral Clock 47 Status PID46 14 Peripheral Clock 46 Status PID45 13 Peripheral Clock 45 Status PID44 12 Peripheral Clock 44 Status PID43 11 Peripheral Clock 43 Status PID42 10 Peripheral Clock 42 Status PID41 9 Peripheral Clock 41 Status PID40 8 Peripheral Clock 40 Status PID39 7 Peripheral Clock 39 Status PID37 5 Peripheral Clock 37 Status PID35 3 Peripheral Clock 35 Status PID34 2 Peripheral Clock 34 Status PID33 1 Peripheral Clock 33 Status PID32 0 Peripheral Clock 32 Status
PMC_PCRPeripheral Control Register
Address 0x400E070C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does GCLKEN 29 Generic Clock Enable EN 28 Enable GCLKDIV 27:20 Generic Clock Division Ratio CMD 12 Command GCLKCSS 10:8 Generic Clock Source Selection0 Slow clock is selected1 Main clock is selected2 PLLACK is selected3 UPLL Clock is selected4 Master Clock is selected PID 6:0 Peripheral ID
PMC_OCROscillator Calibration Register
Address 0x400E0710
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does SEL12 23 Selection of Main RC Oscillator Calibration Bits for 12 MHz CAL12 22:16 Main RC Oscillator Calibration Bits for 12 MHz SEL8 15 Selection of Main RC Oscillator Calibration Bits for 8 MHz CAL8 14:8 Main RC Oscillator Calibration Bits for 8 MHz SEL4 7 Selection of Main RC Oscillator Calibration Bits for 4 MHz CAL4 6:0 Main RC Oscillator Calibration Bits for 4 MHz
PMC_SLPWK_ER0SleepWalking Enable Register 0
Address 0x400E0714
Reset 0x00000000
Access write only
Size 32-bit 25 fields
Field Bits What it does PID30 30 Peripheral 30 SleepWalking Enable PID29 29 Peripheral 29 SleepWalking Enable PID28 28 Peripheral 28 SleepWalking Enable PID27 27 Peripheral 27 SleepWalking Enable PID26 26 Peripheral 26 SleepWalking Enable PID25 25 Peripheral 25 SleepWalking Enable PID24 24 Peripheral 24 SleepWalking Enable PID23 23 Peripheral 23 SleepWalking Enable PID22 22 Peripheral 22 SleepWalking Enable PID21 21 Peripheral 21 SleepWalking Enable PID20 20 Peripheral 20 SleepWalking Enable PID19 19 Peripheral 19 SleepWalking Enable PID18 18 Peripheral 18 SleepWalking Enable PID17 17 Peripheral 17 SleepWalking Enable PID16 16 Peripheral 16 SleepWalking Enable PID15 15 Peripheral 15 SleepWalking Enable PID14 14 Peripheral 14 SleepWalking Enable PID13 13 Peripheral 13 SleepWalking Enable PID12 12 Peripheral 12 SleepWalking Enable PID11 11 Peripheral 11 SleepWalking Enable PID10 10 Peripheral 10 SleepWalking Enable PID9 9 Peripheral 9 SleepWalking Enable PID8 8 Peripheral 8 SleepWalking Enable PID7 7 Peripheral 7 SleepWalking Enable PID31 31 Peripheral 31 SleepWalking Enable
PMC_SLPWK_DR0SleepWalking Disable Register 0
Address 0x400E0718
Reset 0x00000000
Access write only
Size 32-bit 25 fields
Field Bits What it does PID30 30 Peripheral 30 SleepWalking Disable PID29 29 Peripheral 29 SleepWalking Disable PID28 28 Peripheral 28 SleepWalking Disable PID27 27 Peripheral 27 SleepWalking Disable PID26 26 Peripheral 26 SleepWalking Disable PID25 25 Peripheral 25 SleepWalking Disable PID24 24 Peripheral 24 SleepWalking Disable PID23 23 Peripheral 23 SleepWalking Disable PID22 22 Peripheral 22 SleepWalking Disable PID21 21 Peripheral 21 SleepWalking Disable PID20 20 Peripheral 20 SleepWalking Disable PID19 19 Peripheral 19 SleepWalking Disable PID18 18 Peripheral 18 SleepWalking Disable PID17 17 Peripheral 17 SleepWalking Disable PID16 16 Peripheral 16 SleepWalking Disable PID15 15 Peripheral 15 SleepWalking Disable PID14 14 Peripheral 14 SleepWalking Disable PID13 13 Peripheral 13 SleepWalking Disable PID12 12 Peripheral 12 SleepWalking Disable PID11 11 Peripheral 11 SleepWalking Disable PID10 10 Peripheral 10 SleepWalking Disable PID9 9 Peripheral 9 SleepWalking Disable PID8 8 Peripheral 8 SleepWalking Disable PID7 7 Peripheral 7 SleepWalking Disable PID31 31 Peripheral 31 SleepWalking Disable
PMC_SLPWK_SR0SleepWalking Status Register 0
Address 0x400E071C
Reset 0x00000000
Access read only
Size 32-bit 25 fields
Field Bits What it does PID30 30 Peripheral 30 SleepWalking Status PID29 29 Peripheral 29 SleepWalking Status PID28 28 Peripheral 28 SleepWalking Status PID27 27 Peripheral 27 SleepWalking Status PID26 26 Peripheral 26 SleepWalking Status PID25 25 Peripheral 25 SleepWalking Status PID24 24 Peripheral 24 SleepWalking Status PID23 23 Peripheral 23 SleepWalking Status PID22 22 Peripheral 22 SleepWalking Status PID21 21 Peripheral 21 SleepWalking Status PID20 20 Peripheral 20 SleepWalking Status PID19 19 Peripheral 19 SleepWalking Status PID18 18 Peripheral 18 SleepWalking Status PID17 17 Peripheral 17 SleepWalking Status PID16 16 Peripheral 16 SleepWalking Status PID15 15 Peripheral 15 SleepWalking Status PID14 14 Peripheral 14 SleepWalking Status PID13 13 Peripheral 13 SleepWalking Status PID12 12 Peripheral 12 SleepWalking Status PID11 11 Peripheral 11 SleepWalking Status PID10 10 Peripheral 10 SleepWalking Status PID9 9 Peripheral 9 SleepWalking Status PID8 8 Peripheral 8 SleepWalking Status PID7 7 Peripheral 7 SleepWalking Status PID31 31 Peripheral 31 SleepWalking Status
PMC_SLPWK_ASR0SleepWalking Activity Status Register 0
Address 0x400E0720
Reset 0x00000000
Access read only
Size 32-bit 25 fields
Field Bits What it does PID30 30 Peripheral 30 Activity Status PID29 29 Peripheral 29 Activity Status PID28 28 Peripheral 28 Activity Status PID27 27 Peripheral 27 Activity Status PID26 26 Peripheral 26 Activity Status PID25 25 Peripheral 25 Activity Status PID24 24 Peripheral 24 Activity Status PID23 23 Peripheral 23 Activity Status PID22 22 Peripheral 22 Activity Status PID21 21 Peripheral 21 Activity Status PID20 20 Peripheral 20 Activity Status PID19 19 Peripheral 19 Activity Status PID18 18 Peripheral 18 Activity Status PID17 17 Peripheral 17 Activity Status PID16 16 Peripheral 16 Activity Status PID15 15 Peripheral 15 Activity Status PID14 14 Peripheral 14 Activity Status PID13 13 Peripheral 13 Activity Status PID12 12 Peripheral 12 Activity Status PID11 11 Peripheral 11 Activity Status PID10 10 Peripheral 10 Activity Status PID9 9 Peripheral 9 Activity Status PID8 8 Peripheral 8 Activity Status PID7 7 Peripheral 7 Activity Status PID31 31 Peripheral 31 Activity Status
PMC_PMMRPLL Maximum Multiplier Value Register
Address 0x400E0730
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does PLLA_MMAX 10:0 PLLA Maximum Allowed Multiplier Value
PMC_SLPWK_ER1SleepWalking Enable Register 1
Address 0x400E0734
Reset 0x00000000
Access write only
Size 32-bit 25 fields
Field Bits What it does PID60 28 Peripheral 60 SleepWalking Enable PID59 27 Peripheral 59 SleepWalking Enable PID58 26 Peripheral 58 SleepWalking Enable PID57 25 Peripheral 57 SleepWalking Enable PID56 24 Peripheral 56 SleepWalking Enable PID53 21 Peripheral 53 SleepWalking Enable PID52 20 Peripheral 52 SleepWalking Enable PID51 19 Peripheral 51 SleepWalking Enable PID50 18 Peripheral 50 SleepWalking Enable PID49 17 Peripheral 49 SleepWalking Enable PID48 16 Peripheral 48 SleepWalking Enable PID47 15 Peripheral 47 SleepWalking Enable PID46 14 Peripheral 46 SleepWalking Enable PID45 13 Peripheral 45 SleepWalking Enable PID44 12 Peripheral 44 SleepWalking Enable PID43 11 Peripheral 43 SleepWalking Enable PID42 10 Peripheral 42 SleepWalking Enable PID41 9 Peripheral 41 SleepWalking Enable PID40 8 Peripheral 40 SleepWalking Enable PID39 7 Peripheral 39 SleepWalking Enable PID37 5 Peripheral 37 SleepWalking Enable PID35 3 Peripheral 35 SleepWalking Enable PID34 2 Peripheral 34 SleepWalking Enable PID33 1 Peripheral 33 SleepWalking Enable PID32 0 Peripheral 32 SleepWalking Enable
PMC_SLPWK_DR1SleepWalking Disable Register 1
Address 0x400E0738
Reset 0x00000000
Access write only
Size 32-bit 25 fields
Field Bits What it does PID60 28 Peripheral 60 SleepWalking Disable PID59 27 Peripheral 59 SleepWalking Disable PID58 26 Peripheral 58 SleepWalking Disable PID57 25 Peripheral 57 SleepWalking Disable PID56 24 Peripheral 56 SleepWalking Disable PID53 21 Peripheral 53 SleepWalking Disable PID52 20 Peripheral 52 SleepWalking Disable PID51 19 Peripheral 51 SleepWalking Disable PID50 18 Peripheral 50 SleepWalking Disable PID49 17 Peripheral 49 SleepWalking Disable PID48 16 Peripheral 48 SleepWalking Disable PID47 15 Peripheral 47 SleepWalking Disable PID46 14 Peripheral 46 SleepWalking Disable PID45 13 Peripheral 45 SleepWalking Disable PID44 12 Peripheral 44 SleepWalking Disable PID43 11 Peripheral 43 SleepWalking Disable PID42 10 Peripheral 42 SleepWalking Disable PID41 9 Peripheral 41 SleepWalking Disable PID40 8 Peripheral 40 SleepWalking Disable PID39 7 Peripheral 39 SleepWalking Disable PID37 5 Peripheral 37 SleepWalking Disable PID35 3 Peripheral 35 SleepWalking Disable PID34 2 Peripheral 34 SleepWalking Disable PID33 1 Peripheral 33 SleepWalking Disable PID32 0 Peripheral 32 SleepWalking Disable
PMC_SLPWK_SR1SleepWalking Status Register 1
Address 0x400E073C
Reset 0x00000000
Access read only
Size 32-bit 25 fields
Field Bits What it does PID60 28 Peripheral 60 SleepWalking Status PID59 27 Peripheral 59 SleepWalking Status PID58 26 Peripheral 58 SleepWalking Status PID57 25 Peripheral 57 SleepWalking Status PID56 24 Peripheral 56 SleepWalking Status PID53 21 Peripheral 53 SleepWalking Status PID52 20 Peripheral 52 SleepWalking Status PID51 19 Peripheral 51 SleepWalking Status PID50 18 Peripheral 50 SleepWalking Status PID49 17 Peripheral 49 SleepWalking Status PID48 16 Peripheral 48 SleepWalking Status PID47 15 Peripheral 47 SleepWalking Status PID46 14 Peripheral 46 SleepWalking Status PID45 13 Peripheral 45 SleepWalking Status PID44 12 Peripheral 44 SleepWalking Status PID43 11 Peripheral 43 SleepWalking Status PID42 10 Peripheral 42 SleepWalking Status PID41 9 Peripheral 41 SleepWalking Status PID40 8 Peripheral 40 SleepWalking Status PID39 7 Peripheral 39 SleepWalking Status PID37 5 Peripheral 37 SleepWalking Status PID35 3 Peripheral 35 SleepWalking Status PID34 2 Peripheral 34 SleepWalking Status PID33 1 Peripheral 33 SleepWalking Status PID32 0 Peripheral 32 SleepWalking Status
PMC_SLPWK_ASR1SleepWalking Activity Status Register 1
Address 0x400E0740
Reset 0x00000000
Access read only
Size 32-bit 25 fields
Field Bits What it does PID60 28 Peripheral 60 Activity Status PID59 27 Peripheral 59 Activity Status PID58 26 Peripheral 58 Activity Status PID57 25 Peripheral 57 Activity Status PID56 24 Peripheral 56 Activity Status PID53 21 Peripheral 53 Activity Status PID52 20 Peripheral 52 Activity Status PID51 19 Peripheral 51 Activity Status PID50 18 Peripheral 50 Activity Status PID49 17 Peripheral 49 Activity Status PID48 16 Peripheral 48 Activity Status PID47 15 Peripheral 47 Activity Status PID46 14 Peripheral 46 Activity Status PID45 13 Peripheral 45 Activity Status PID44 12 Peripheral 44 Activity Status PID43 11 Peripheral 43 Activity Status PID42 10 Peripheral 42 Activity Status PID41 9 Peripheral 41 Activity Status PID40 8 Peripheral 40 Activity Status PID39 7 Peripheral 39 Activity Status PID37 5 Peripheral 37 Activity Status PID35 3 Peripheral 35 Activity Status PID34 2 Peripheral 34 Activity Status PID33 1 Peripheral 33 Activity Status PID32 0 Peripheral 32 Activity Status
PMC_SLPWK_AIPRSleepWalking Activity In Progress Register
Address 0x400E0744
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does AIP 0 Activity In Progress