The 11 registers of MCRAMC (Multi-Channel RAM Controller), from 0x44822000, with their reset value and every field. The PIC32CZ8110CA80100 has 5717 registers in 62 peripherals, one page each.
MCRAMC Multi-Channel RAM Controller
MCRAMC_CTRLAControl Enable A Register
Address
0x44822000
Reset
0x00000002
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ENABLE
1
ECC Decoder Enable
0 ECC decoding is disabled.
1 ECC decoding is enabled.
SWRST
0
Software Reset
0 No effect.
1 Reset the MCRAMC. A software-triggered hardware reset of the MCRAMC user interface is performed.
MCRAMC_SYNCBUSYSync Busy Register
Address
0x44822004
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
ENABLE
2
ECC Decoder Enable busy bit
FLTEN
1
Fault Injection Enabled busy bit
SWRST
0
Software reset busy bit
MCRAMC_INTENCLRInterrupt Enable Clear Register
Address
0x44822008
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DERREN
1
Double Bit Error Interrupt Enable, Clear
SERREN
0
Single Bit Error Interrupt Enable, Clear
MCRAMC_INTENSETInterrupt Enable Set Register
Address
0x4482200C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DERREN
1
Double Bit Error Interrupt Enable, Set
SERREN
0
Single Bit Error Interrupt Enable, Set
MCRAMC_INTSTAInterrupt Status Register
Address
0x44822010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DERR
1
Double Bit Error
SERR
0
Single Bit Error
MCRAMC_FLTCTRLFault Injection Control Register
Address
0x44822014
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
FLTMD
13:12
Fault Injection Mode
FLTEN
1
Fault Injection Enabled
0 Disables fault injection.
1 Enables fault injection at FLTADR address offset as selected by FLTMD and FLTxPTR.