PIC32CZ8110CA80144 ADC0 registers The 73 registers of ADC0 (ADC Controller), from 0x46820000, with their reset value and every field. The PIC32CZ8110CA80144 has 5959 registers in 66 peripherals, one page each.
ADC0 ADC Controller CTRLACONTROL A REGISTER
Address 0x46820000
Reset 0x00000080
Access read/write
Size 32-bit 6 fields
Field Bits What it does ONDEMAND 7 On Demand Control RUNSTDBY 6 Run in Standby AIPMPEN 4 Charge Pump Enable ANAEN 2 Analog Enable ENABLE 1 ENABLE BIT SWRST 0 SOFTWARE RESET BIT
CTRLBCONTROL B REGISTER
Address 0x46820004
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does SWCNVEN 15 Software Conversion Enable TRGSUSP 10 Trigger Suspend LSWTRG 9 Level Global Trigger GSWTRG 8 Global Software Trigger SAMP 7 Channel Sample RQCNVRT 6 Request Channel Convert ADCORSEL 5:4 Software Trigger Core Select ADCHSEL 3:0 Software Trigger Channel Select
CTRLCControl C Register
Address 0x46820008
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does COREINTERLEAVED 30:28 Number of Core to Interleave Triggers0 Interleaving Off1 Interleaving Cores 1 and 22 Interleaving Cores 1, 2 and 33 Interleaving Cores 0, 1, 2 and 34 Interleaving Cores 0 and 15 Interleaving Cores 0, 1 and 2 CNT 15:0 Clock Divider for Synchronous Trigger
CTRLDControl D Register
Address 0x46820010
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does VREFSEL 30:28 Voltage Reference Select0 AVDD and AVSS1 External VREFH and AVSS WKUPEXP 27:24 Wakeup cycles ANLEN 23:20 Analog Channel Enable CHNEN 19:16 Digital Channel Enable CTLCKDIV 13:8 Control Clock Divider
CONFIG0.CORCTRLSARCORE Control
Address 0x46820020
Reset 0x00000C00
Access read/write
Size 32-bit 8 fields
Field Bits What it does ADCDIV 30:24 Division Ratio for SARCORE clock SCNRTDS 22 SCAN Re-trigger Disable STRGLVL 21 Scan Trigger Level Sensitivity STRGSRC 19:16 SCAN trigger source selection0 No Trigger (NOP)1 Global Software Trigger2 Global Level Software Trigger4 STRIG Synchronous Trigger5 ADC Trigger Event User 06 ADC Trigger Event User 17 ADC Trigger Event User 28 ADC Trigger Event User 39 ADC Trigger Event User 410 ADC Trigger Event User 511 ADC Trigger Event User 612 ADC Trigger Event User 713 ADC Trigger Event User 814 ADC Trigger Event User 915 ADC Trigger Event User 10 EIRQOVR 15 Interrupt Type Select EIS 14:12 Early Interrupt Select SELRES 11:10 Selects Resolution0 6 bits1 8 bits2 10 bits3 12 bits (default) SAMC 9:0 Sample Count
CONFIG0.CHNCFG1Channel Configuration 1 (LVL/CMPEN)
Address 0x46820024
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CHNCMPEN 15:0 Channel Comparator Enable LVL 31:16 Channel Level
CONFIG0.CHNCFG2Channel Configuration 2(FRACT/CSS)
Address 0x46820028
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSS 15:0 Channel SCAN Select FRACT 31:16 Channel Fractional
CONFIG0.CHNCFG3Channel Configuration3 (SIGN/DIFF)
Address 0x4682002C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DIFF 15:0 Differential Mode SIGN 31:16 SIGN setting
CONFIG0.CHNCFG4Channel Configuration 4 (TRGSRC)
Address 0x46820030
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
CONFIG0.CHNCFG5Channel Configuration 5 (TRGSRC)
Address 0x46820034
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
CONFIG0.CALCTRLSARCORE Calibration Value
Address 0x46820038
Reset 0x00000000
Access read/write
Size 32-bit 17 fields
Field Bits What it does icmbf 29:28 Bias Current Common Mode Buffer icmp_2 27:26 Bias Current Stage 2 icmp_1 25:24 Bias Current Stage 1 iadc_2 23:22 Current Consumption 2 iadc_1 21:20 Current Consumption 1 tclk_div 15:11 Test Clock Divider t1_dly 10:9 Regen Latch Delay sel_del 8 Scan Mode comp_out dbg_sel 7 Debug Bus Select en_rdac 6 Disable Power Cycling dis_laz 5 Disable auto-zeroing dis_saz 4 Disable auto-zeroing dis_faz 3 Disable auto-zeroing en_dither 2 Enable Dither en_cmbf 0 Enable Common Mode Buffer CALBITS 31:0 Calibration Values en_ext_bias 31 Dsiable Internal Bias Circuit
CONFIG0.EVCTRLEvent Control
Address 0x4682003C
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does RESRDYEO 4 Result Ready Event Out STARTINV 3 Start Conversion Invert STARTEI 0 Start Event conversion input enable
CONFIG1.CORCTRLSARCORE Control
Address 0x46820040
Reset 0x00000C00
Access read/write
Size 32-bit 8 fields
Field Bits What it does ADCDIV 30:24 Division Ratio for SARCORE clock SCNRTDS 22 SCAN Re-trigger Disable STRGLVL 21 Scan Trigger Level Sensitivity STRGSRC 19:16 SCAN trigger source selection0 No Trigger (NOP)1 Global Software Trigger2 Global Level Software Trigger4 STRIG Synchronous Trigger5 ADC Trigger Event User 06 ADC Trigger Event User 17 ADC Trigger Event User 28 ADC Trigger Event User 39 ADC Trigger Event User 410 ADC Trigger Event User 511 ADC Trigger Event User 612 ADC Trigger Event User 713 ADC Trigger Event User 814 ADC Trigger Event User 915 ADC Trigger Event User 10 EIRQOVR 15 Interrupt Type Select EIS 14:12 Early Interrupt Select SELRES 11:10 Selects Resolution0 6 bits1 8 bits2 10 bits3 12 bits (default) SAMC 9:0 Sample Count
CONFIG1.CHNCFG1Channel Configuration 1 (LVL/CMPEN)
Address 0x46820044
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CHNCMPEN 15:0 Channel Comparator Enable LVL 31:16 Channel Level
CONFIG1.CHNCFG2Channel Configuration 2(FRACT/CSS)
Address 0x46820048
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSS 15:0 Channel SCAN Select FRACT 31:16 Channel Fractional
CONFIG1.CHNCFG3Channel Configuration3 (SIGN/DIFF)
Address 0x4682004C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DIFF 15:0 Differential Mode SIGN 31:16 SIGN setting
CONFIG1.CHNCFG4Channel Configuration 4 (TRGSRC)
Address 0x46820050
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
CONFIG1.CHNCFG5Channel Configuration 5 (TRGSRC)
Address 0x46820054
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
CONFIG1.CALCTRLSARCORE Calibration Value
Address 0x46820058
Reset 0x00000000
Access read/write
Size 32-bit 17 fields
Field Bits What it does icmbf 29:28 Bias Current Common Mode Buffer icmp_2 27:26 Bias Current Stage 2 icmp_1 25:24 Bias Current Stage 1 iadc_2 23:22 Current Consumption 2 iadc_1 21:20 Current Consumption 1 tclk_div 15:11 Test Clock Divider t1_dly 10:9 Regen Latch Delay sel_del 8 Scan Mode comp_out dbg_sel 7 Debug Bus Select en_rdac 6 Disable Power Cycling dis_laz 5 Disable auto-zeroing dis_saz 4 Disable auto-zeroing dis_faz 3 Disable auto-zeroing en_dither 2 Enable Dither en_cmbf 0 Enable Common Mode Buffer CALBITS 31:0 Calibration Values en_ext_bias 31 Dsiable Internal Bias Circuit
CONFIG1.EVCTRLEvent Control
Address 0x4682005C
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does RESRDYEO 4 Result Ready Event Out STARTINV 3 Start Conversion Invert STARTEI 0 Start Event conversion input enable
CONFIG2.CORCTRLSARCORE Control
Address 0x46820060
Reset 0x00000C00
Access read/write
Size 32-bit 8 fields
Field Bits What it does ADCDIV 30:24 Division Ratio for SARCORE clock SCNRTDS 22 SCAN Re-trigger Disable STRGLVL 21 Scan Trigger Level Sensitivity STRGSRC 19:16 SCAN trigger source selection0 No Trigger (NOP)1 Global Software Trigger2 Global Level Software Trigger4 STRIG Synchronous Trigger5 ADC Trigger Event User 06 ADC Trigger Event User 17 ADC Trigger Event User 28 ADC Trigger Event User 39 ADC Trigger Event User 410 ADC Trigger Event User 511 ADC Trigger Event User 612 ADC Trigger Event User 713 ADC Trigger Event User 814 ADC Trigger Event User 915 ADC Trigger Event User 10 EIRQOVR 15 Interrupt Type Select EIS 14:12 Early Interrupt Select SELRES 11:10 Selects Resolution0 6 bits1 8 bits2 10 bits3 12 bits (default) SAMC 9:0 Sample Count
CONFIG2.CHNCFG1Channel Configuration 1 (LVL/CMPEN)
Address 0x46820064
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CHNCMPEN 15:0 Channel Comparator Enable LVL 31:16 Channel Level
CONFIG2.CHNCFG2Channel Configuration 2(FRACT/CSS)
Address 0x46820068
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSS 15:0 Channel SCAN Select FRACT 31:16 Channel Fractional
CONFIG2.CHNCFG3Channel Configuration3 (SIGN/DIFF)
Address 0x4682006C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DIFF 15:0 Differential Mode SIGN 31:16 SIGN setting
CONFIG2.CHNCFG4Channel Configuration 4 (TRGSRC)
Address 0x46820070
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
CONFIG2.CHNCFG5Channel Configuration 5 (TRGSRC)
Address 0x46820074
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
CONFIG2.CALCTRLSARCORE Calibration Value
Address 0x46820078
Reset 0x00000000
Access read/write
Size 32-bit 17 fields
Field Bits What it does icmbf 29:28 Bias Current Common Mode Buffer icmp_2 27:26 Bias Current Stage 2 icmp_1 25:24 Bias Current Stage 1 iadc_2 23:22 Current Consumption 2 iadc_1 21:20 Current Consumption 1 tclk_div 15:11 Test Clock Divider t1_dly 10:9 Regen Latch Delay sel_del 8 Scan Mode comp_out dbg_sel 7 Debug Bus Select en_rdac 6 Disable Power Cycling dis_laz 5 Disable auto-zeroing dis_saz 4 Disable auto-zeroing dis_faz 3 Disable auto-zeroing en_dither 2 Enable Dither en_cmbf 0 Enable Common Mode Buffer CALBITS 31:0 Calibration Values en_ext_bias 31 Dsiable Internal Bias Circuit
CONFIG2.EVCTRLEvent Control
Address 0x4682007C
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does RESRDYEO 4 Result Ready Event Out STARTINV 3 Start Conversion Invert STARTEI 0 Start Event conversion input enable
CONFIG3.CORCTRLSARCORE Control
Address 0x46820080
Reset 0x00000C00
Access read/write
Size 32-bit 8 fields
Field Bits What it does ADCDIV 30:24 Division Ratio for SARCORE clock SCNRTDS 22 SCAN Re-trigger Disable STRGLVL 21 Scan Trigger Level Sensitivity STRGSRC 19:16 SCAN trigger source selection0 No Trigger (NOP)1 Global Software Trigger2 Global Level Software Trigger4 STRIG Synchronous Trigger5 ADC Trigger Event User 06 ADC Trigger Event User 17 ADC Trigger Event User 28 ADC Trigger Event User 39 ADC Trigger Event User 410 ADC Trigger Event User 511 ADC Trigger Event User 612 ADC Trigger Event User 713 ADC Trigger Event User 814 ADC Trigger Event User 915 ADC Trigger Event User 10 EIRQOVR 15 Interrupt Type Select EIS 14:12 Early Interrupt Select SELRES 11:10 Selects Resolution0 6 bits1 8 bits2 10 bits3 12 bits (default) SAMC 9:0 Sample Count
CONFIG3.CHNCFG1Channel Configuration 1 (LVL/CMPEN)
Address 0x46820084
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CHNCMPEN 15:0 Channel Comparator Enable LVL 31:16 Channel Level
CONFIG3.CHNCFG2Channel Configuration 2(FRACT/CSS)
Address 0x46820088
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSS 15:0 Channel SCAN Select FRACT 31:16 Channel Fractional
CONFIG3.CHNCFG3Channel Configuration3 (SIGN/DIFF)
Address 0x4682008C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does DIFF 15:0 Differential Mode SIGN 31:16 SIGN setting
CONFIG3.CHNCFG4Channel Configuration 4 (TRGSRC)
Address 0x46820090
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
CONFIG3.CHNCFG5Channel Configuration 5 (TRGSRC)
Address 0x46820094
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
CONFIG3.CALCTRLSARCORE Calibration Value
Address 0x46820098
Reset 0x00000000
Access read/write
Size 32-bit 17 fields
Field Bits What it does icmbf 29:28 Bias Current Common Mode Buffer icmp_2 27:26 Bias Current Stage 2 icmp_1 25:24 Bias Current Stage 1 iadc_2 23:22 Current Consumption 2 iadc_1 21:20 Current Consumption 1 tclk_div 15:11 Test Clock Divider t1_dly 10:9 Regen Latch Delay sel_del 8 Scan Mode comp_out dbg_sel 7 Debug Bus Select en_rdac 6 Disable Power Cycling dis_laz 5 Disable auto-zeroing dis_saz 4 Disable auto-zeroing dis_faz 3 Disable auto-zeroing en_dither 2 Enable Dither en_cmbf 0 Enable Common Mode Buffer CALBITS 31:0 Calibration Values en_ext_bias 31 Dsiable Internal Bias Circuit
CONFIG3.EVCTRLEvent Control
Address 0x4682009C
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does RESRDYEO 4 Result Ready Event Out STARTINV 3 Start Conversion Invert STARTEI 0 Start Event conversion input enable
CMPCTRL0Comparator Control
Address 0x468200B0
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does IEHIHI 29 Enable VAL >= CMPHI IEHILO 28 Enable VAL < CMPHI ADCMPHI 27:16 High Limit of Digital Comparator IEBTWN 15 Enable CMPLO <= VAL < CMPHI IELOHI 14 Enable VAL >= CMPLO IELOLO 13 Enable VAL < CMPLO CMPEN 12 Comparator Enable ADCMPLO 11:0 Low Limit of Digital Comparator
CMPCTRL1Comparator Control
Address 0x468200B4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does IEHIHI 29 Enable VAL >= CMPHI IEHILO 28 Enable VAL < CMPHI ADCMPHI 27:16 High Limit of Digital Comparator IEBTWN 15 Enable CMPLO <= VAL < CMPHI IELOHI 14 Enable VAL >= CMPLO IELOLO 13 Enable VAL < CMPLO CMPEN 12 Comparator Enable ADCMPLO 11:0 Low Limit of Digital Comparator
CMPCTRL2Comparator Control
Address 0x468200B8
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does IEHIHI 29 Enable VAL >= CMPHI IEHILO 28 Enable VAL < CMPHI ADCMPHI 27:16 High Limit of Digital Comparator IEBTWN 15 Enable CMPLO <= VAL < CMPHI IELOHI 14 Enable VAL >= CMPLO IELOLO 13 Enable VAL < CMPLO CMPEN 12 Comparator Enable ADCMPLO 11:0 Low Limit of Digital Comparator
CMPCTRL3Comparator Control
Address 0x468200BC
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does IEHIHI 29 Enable VAL >= CMPHI IEHILO 28 Enable VAL < CMPHI ADCMPHI 27:16 High Limit of Digital Comparator IEBTWN 15 Enable CMPLO <= VAL < CMPHI IELOHI 14 Enable VAL >= CMPLO IELOLO 13 Enable VAL < CMPLO CMPEN 12 Comparator Enable ADCMPLO 11:0 Low Limit of Digital Comparator
FLTCTRL0Filter Control
Address 0x468200C0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does FLTCHNID 13:10 Channel ID FLTEN 8 Filter Enable DATA16EN 4 16bit Averaging Mode FMODE 3 Filter Mode OVRSAM 2:0 Oversampling Ratio0 (If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged1 (If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged2 (If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged3 (If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged4 (If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged5 (If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged6 (If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged7 (If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged
FLTCTRL1Filter Control
Address 0x468200C4
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does FLTCHNID 13:10 Channel ID FLTEN 8 Filter Enable DATA16EN 4 16bit Averaging Mode FMODE 3 Filter Mode OVRSAM 2:0 Oversampling Ratio0 (If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged1 (If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged2 (If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged3 (If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged4 (If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged5 (If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged6 (If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged7 (If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged
FLTCTRL2Filter Control
Address 0x468200C8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does FLTCHNID 13:10 Channel ID FLTEN 8 Filter Enable DATA16EN 4 16bit Averaging Mode FMODE 3 Filter Mode OVRSAM 2:0 Oversampling Ratio0 (If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged1 (If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged2 (If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged3 (If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged4 (If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged5 (If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged6 (If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged7 (If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged
FLTCTRL3Filter Control
Address 0x468200CC
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does FLTCHNID 13:10 Channel ID FLTEN 8 Filter Enable DATA16EN 4 16bit Averaging Mode FMODE 3 Filter Mode OVRSAM 2:0 Oversampling Ratio0 (If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged1 (If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged2 (If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged3 (If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged4 (If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged5 (If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged6 (If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged7 (If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged
CORCHDATAIDChannel Ready DATA ID
Address 0x468200D0
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CORDYID 5:4 Core Read ID CHRDYID 3:0 Channel Read ID
CHRDYDATChannel Ready Data Register
Address 0x468200D4
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does FRACT 27 Fractional Setting SIGN 26 Sign Setting DIFF 25 Differential Setting LVL 24 Level Setting CHRDYDAT 15:0 Channel Output Data
PFFDATAAPB FIFO Output Data
Address 0x468200D8
Reset 0x00000000
Access read only
Size 32-bit 6 fields
Field Bits What it does PFFFRACT 23 Fractional Setting from APB FIFO PFFSIGN 22 Channel Sign from the APB FIFO PFFCORID 21:20 Core ID from APB FIFO PFFCHNID 19:16 Channel ID from APB FIFO PFFDATA 15:0 SARCORE Conversion data from the APB FIFO PFFCNT 31:24 Current Data Entries in APB FIFO
DMABASEDMA Sample Base Address
Address 0x468200DC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DMABASE 31:0 DMA Sample Value Base Address
DMACTRLDMA Control Register
Address 0x468200E0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does DMABL 10:8 DMA System RAM Buffer Length DMACR 7:4 DMA CORE Enables DMAEN 1 DMA Enable
PFFCTRLAPB FIFO Control Register
Address 0x468200E4
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does PFFRDYDM 16 DMA APB FIFO Data Ready0 Selects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC1 Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC PFFCR 7:4 APB CORE FIFO Enable PFFEN 1 APB FIFO Enable
SYNCBUSYCORE SYNC Busy Status Register
Address 0x468200E8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does SWRST 24 Software Reset Sync Busy CTRLB 2 CTRLB sync busy ENABLE 0 Enable bit Sync Busy
TESTREGTest Control Register
Address 0x468200EC
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does ADCORSEL 29:28 Core Select ADCHSEL 27:24 Channel Select EN_ATEST 19:16 Analog Test Circuitry Enables TESTEN 0 Test Mode Enable
DMAINTENCLRDMA Interrupt Enable Clear
Address 0x468200F0
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does SOVFL 16 Synchonizer Overflow RBF 7:4 Ram Buffer B Full RAF 3:0 Ram Buffer A Full
DMAINTSETDMA Interrupt Enable Set
Address 0x468200F4
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does SOVFL 16 Synchonizer Overflow RBF 7:4 Ram Buffer B Full RAF 3:0 Ram Buffer A Full
DMAINTFLAGDMA Interrupt Flag and Status
Address 0x468200F8
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does SOVFL 16 Synchronizer overflow RBF 7:4 Ram Buffer B Full RAF 3:0 Ram Buffer A Full
CTLINTENSETCORE Controller Interrupt Enable Set
Address 0x468200FC
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does PFFHFUL 11 APB FIFO Half Full PFFRDY 10 APB FIFO Ready PFFOVF 9 APB FIFO Overflow PFFUNF 8 APB FIFO Underflow VREFRDY 7 VREF Ready VREFUPD 6 VREF update CRRDY 3:0 Core Ready
CTLINTENCLRCORE Controller Interrupt Enable Clear
Address 0x46820100
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does PFFHFUL 11 APB FIFO Half Full PFFRDY 10 APB FIFO Ready PFFOVF 9 APB FIFO overflow PFFUNF 8 APB FIFO underflow VREFRDY 7 VREF Ready VREFUPD 6 VREF Update CRRDY 3:0 Core Ready Disable
CTLINTFLAGCORE Controller Interrupt Flags
Address 0x46820104
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does PFFHFUL 11 APB FIFO Half Full PFFRDY 10 APB FIFO Ready PFFOVF 9 APB FIFO overflow PFFUNF 8 APB FIFO underflow VREFRDY 7 VREF Ready VREFUPD 6 VREF update CRRDY 3:0 Core Ready
INTENCLR0Interrupt Enable Clear
Address 0x46820120
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does CHRDY 27:12 Channel Ready Disable EOSRDY 11 Endo of Scan Disable CHNERRC 10 Channel Overwrite Error Disable FLTRDY 9 Filter Ready Disable CHRDYC 8 Core Current Channel Disable SOVFL 7 Synchonizer Overflow Disable CMPHIT 4 Compare Hit Disable
INTENSET0Interrupt Enable Set
Address 0x46820124
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does EOSRDY 11 End of Scan Enable CHNERRC 10 Channel Overwrite Enable FLTRDY 9 Filter Ready Enable CHRDYC 8 Current Channel Ready Enable SOVFL 7 Synchronizer Overflow Enable CMPHIT 4 Compare Hit Enable CHRDY 31:16 Channel Ready Enable
INTFLAG0Interrupt Flags
Address 0x46820128
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does CRDYID 15:12 Channel Ready ID EOSRDY 11 End of Scan Ready CHNERRC 10 Channel Overwrite Error FLTRDY 9 Filter Ready CHRDYC 8 Current Channel Ready SOVFL 7 Synchronizer Overflow CMPHIT 4 Compare Hit CMPINTID 3:0 Compare Channel ID CHRDY 31:16 Channel Ready
INTENCLR1Interrupt Enable Clear
Address 0x46820130
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does CHRDY 27:12 Channel Ready Disable EOSRDY 11 Endo of Scan Disable CHNERRC 10 Channel Overwrite Error Disable FLTRDY 9 Filter Ready Disable CHRDYC 8 Core Current Channel Disable SOVFL 7 Synchonizer Overflow Disable CMPHIT 4 Compare Hit Disable
INTENSET1Interrupt Enable Set
Address 0x46820134
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does EOSRDY 11 End of Scan Enable CHNERRC 10 Channel Overwrite Enable FLTRDY 9 Filter Ready Enable CHRDYC 8 Current Channel Ready Enable SOVFL 7 Synchronizer Overflow Enable CMPHIT 4 Compare Hit Enable CHRDY 31:16 Channel Ready Enable
INTFLAG1Interrupt Flags
Address 0x46820138
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does CRDYID 15:12 Channel Ready ID EOSRDY 11 End of Scan Ready CHNERRC 10 Channel Overwrite Error FLTRDY 9 Filter Ready CHRDYC 8 Current Channel Ready SOVFL 7 Synchronizer Overflow CMPHIT 4 Compare Hit CMPINTID 3:0 Compare Channel ID CHRDY 31:16 Channel Ready
INTENCLR2Interrupt Enable Clear
Address 0x46820140
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does CHRDY 27:12 Channel Ready Disable EOSRDY 11 Endo of Scan Disable CHNERRC 10 Channel Overwrite Error Disable FLTRDY 9 Filter Ready Disable CHRDYC 8 Core Current Channel Disable SOVFL 7 Synchonizer Overflow Disable CMPHIT 4 Compare Hit Disable
INTENSET2Interrupt Enable Set
Address 0x46820144
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does EOSRDY 11 End of Scan Enable CHNERRC 10 Channel Overwrite Enable FLTRDY 9 Filter Ready Enable CHRDYC 8 Current Channel Ready Enable SOVFL 7 Synchronizer Overflow Enable CMPHIT 4 Compare Hit Enable CHRDY 31:16 Channel Ready Enable
INTFLAG2Interrupt Flags
Address 0x46820148
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does CRDYID 15:12 Channel Ready ID EOSRDY 11 End of Scan Ready CHNERRC 10 Channel Overwrite Error FLTRDY 9 Filter Ready CHRDYC 8 Current Channel Ready SOVFL 7 Synchronizer Overflow CMPHIT 4 Compare Hit CMPINTID 3:0 Compare Channel ID CHRDY 31:16 Channel Ready
INTENCLR3Interrupt Enable Clear
Address 0x46820150
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does CHRDY 27:12 Channel Ready Disable EOSRDY 11 Endo of Scan Disable CHNERRC 10 Channel Overwrite Error Disable FLTRDY 9 Filter Ready Disable CHRDYC 8 Core Current Channel Disable SOVFL 7 Synchonizer Overflow Disable CMPHIT 4 Compare Hit Disable
INTENSET3Interrupt Enable Set
Address 0x46820154
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does EOSRDY 11 End of Scan Enable CHNERRC 10 Channel Overwrite Enable FLTRDY 9 Filter Ready Enable CHRDYC 8 Current Channel Ready Enable SOVFL 7 Synchronizer Overflow Enable CMPHIT 4 Compare Hit Enable CHRDY 31:16 Channel Ready Enable
INTFLAG3Interrupt Flags
Address 0x46820158
Reset 0x00000000
Access read/write
Size 32-bit 9 fields
Field Bits What it does CRDYID 15:12 Channel Ready ID EOSRDY 11 End of Scan Ready CHNERRC 10 Channel Overwrite Error FLTRDY 9 Filter Ready CHRDYC 8 Current Channel Ready SOVFL 7 Synchronizer Overflow CMPHIT 4 Compare Hit CMPINTID 3:0 Compare Channel ID CHRDY 31:16 Channel Ready
DIGTSTOUTTest Debug Register
Address 0x46820160
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does ADCDIGTST 31:0 Digital Debug Test port Register
TSTIDOUTTest Degug2 Register
Address 0x46820164
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does TSTCORID 0 Core Digital Test Out Read ID
DBGCTRLDebug Control Register
Address 0x46820168
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DBGRUN 0 Debug Running State
BETA