PIC32CZ8110CA90144 SPI_IXS0 registers

The 15 registers of SPI_IXS0 (Audio SPI with 8 channels compatibilty), from 0x46030000, with their reset value and every field. The PIC32CZ8110CA90144 has 5988 registers in 67 peripherals, one page each.

SPI_IXS0 Audio SPI with 8 channels compatibilty

CTRLASPI Control Enable Register

Address
0x46030000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
RUNSTDBY6RUN STANDBY Mode Enable bit
ENABLE1SPI Enable (ON) bit
SWRST0SPI Software Reset

SELCTRLSPI Control Options Select Register

Address
0x46030004
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
DATFILL24DATFILL undefined bits 1 or 0
TURSAMP23Transmit Under-run last sample sent
DATFMTLR16Packed data format -- left or right justified
IGNTUR14Ignore Transmit Underrun (for Audio Data Transmissions)
STXISEL13:12SPI Transmit Service Request Interrupt Select
  • 0 TXB And SR Empty
  • 1 TXB Empty
  • 2 TXB Half Empty
  • 3 TXB Not Full
CPOL11Clock Polarity Select bit
CPHA10SPI Clock Edge Select bit
IGNROV6Ignore Receive Overflow (for Audio Data Transmissions)
SRXISEL5:4SPI Receive Service Request Interrupt Select
  • 0 RXB Empty
  • 1 RXB Not Empty
  • 2 RXB Half Full
  • 3 RXB Full
CLKINDLY1:0Serial Clock Input Delay for SDI sampling
  • 0 0 Tap Delays
  • 1 1 Tap Delay
  • 2 2 Tap Delay
  • 3 3 Tap Delay
MODEEN31:30MACRO MODE ENABLED
  • 0 Default Mode
  • 1 Audio Mode
  • 2 Framed Mode
  • 3 Broadcast Mode

SPICTRLSPI Control Register

Address
0x46030008
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
SMP10SPI Data Input Sample Phase bit
SPISGNEXT9Sign Extend Read Data from the RX FIFO
MSSEN6Master/Slave Mode Select Enable bit
MSTEN5Master Mode Enable bit
DISSDO4Disable SDO bit
DISSDI3Disable SDI bit
MODE1:0Serial Word Length bits for AUDEN=0, not used when AUDEN=1
  • 0 8 Bits Mode
  • 1 16 Bits Mode
  • 2 32 Bits Mode

FRAMECTRLSPI Control Frame Register

Address
0x4603000C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
TDMSSZ26:24TDM Number of Bits in a Slot Size
  • 0 Slot Size 8
  • 1 Slot Size 12
  • 2 Slot Size 16
  • 3 Slot Size 20
  • 4 Slot Size 24
  • 5 Slot Size 28
  • 6 Slot Size 32
FRMCNT20:16Frame sync pulse counter
  • 0 Generate a Frame sync pulse on each serial word
  • 1 Number of slots per frame sync pulse is 2
  • 2 Number of slots per frame sync pulse is 3
  • 3 Number of slots per frame sync pulse is 4
  • 4 Number of slots per frame sync pulse is 5
  • 5 Number of slots per frame sync pulse is 6
  • 6 Number of slots per frame sync pulse is 8
  • 7 Number of slots per frame sync pulse is 10
  • 8 Number of slots per frame sync pulse is 12
  • 9 Number of slots per frame sync pulse is 14
  • 10 Number of slots per frame sync pulse is 16
  • 11 Number of slots per frame sync pulse is 18
  • 12 Number of slots per frame sync pulse is 20
  • 13 Number of slots per frame sync pulse is 22
  • 14 Number of slots per frame sync pulse is 24
  • 15 Number of slots per frame sync pulse is 26
  • 16 Number of slots per frame sync pulse is 28
  • 17 Number of slots per frame sync pulse is 30
  • 18 Number of slots per frame sync pulse is 32
FRMSLV14Frame Sync Pulse Direction Control bit
FRMPOL13Frame Sync / Slave Select Polarity bit
FRMCOINC8Frame Sync Pulse Edge Select bit
FRMSYPW3:0Frame sync pulse width in serial words
  • 0 Frame sync pulse is one clock wide
  • 1 Frame sync pulse is one slots wide
  • 2 Frame sync pulse is two slots wide
  • 3 Frame sync pulse is three slots wide
  • 4 Frame sync pulse is four slots wide
  • 5 Frame sync pulse is five slots wide
  • 6 Frame sync pulse is six slots wide
  • 7 Frame sync pulse is seven slots wide
  • 8 Frame sync pulse is eight slots wide
  • 9 Frame sync pulse is sixteen slots wide
  • 10 Frame sync pulse is thirty one slots wide
TDMWSZ31:29TDM Number of Bits in a Word Size
  • 0 Word Size 8
  • 1 Word Size 12
  • 2 Word Size 16
  • 3 Word Size 20
  • 4 Word Size 24
  • 5 Word Size 28
  • 6 Word Size 32

AUDCTRLSPI Control Audio Register

Address
0x46030010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
AUDWDMODE9:8Serial Word Length bits (Ignored when AUDEN=0)
AUDFMT6:4Audio Protocol Format
  • 0 Legacy I2S Mode
  • 1 I2S Raw Audio Format
  • 2 I2S Other AM824 Format
  • 4 I8S Other Format
  • 5 I8S Raw Audio Format
  • 6 I8S Other AM824 Format
AUDMONO3Transmit audio data format
AUDMOD1:0Audio Protocol Mode
  • 0 I2S/I8S Standard Mode
  • 1 I2S/I8S Left Or Right Justified
  • 3 PCM/DSP Mode

TPDCTRLSPI Control Tpd Register

Address
0x46030014
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
SLVNUM10:8Number of the Slave designated: to be used with the PKFMT to determine the slave.
  • 0 SLAVE 0
  • 1 SLAVE 1
  • 2 SLAVE 2
  • 3 SLAVE 3
  • 4 SLAVE 4
PKFMT2:0Master Slave TPD mode.
  • 0 32 bit data in 4x32 packed format
  • 1 32 bit data in 3x32 packed format
  • 2 24 bit data in 4x24 packed format
  • 3 24 bit data in 3x24 packed format
  • 4 16 bit data in 6x16 packed format
  • 5 16 bit data in 4x16 packed format
  • 6 16 bit data in 2x16 packed format

INTENSETSPI Interrupt Enable Set Register

Address
0x46030018
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
SPIROVEN30Enable Interrupt Events via SPIROV
SPITUREN27Enable Interrupt Events via SPITUR
FRMERREN15Enable Interrupt Events via FRMERR
SPITXBEEN4Enablie Interrupt Events via SPITXBE
SPIRXBFEN0Enablie Interrupt Events via SPIRXBF

INTENCLRSPI Interrupt Enable Clear Register

Address
0x4603001C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
SPIROVEN30Enable Interrupt Events via SPIROV
SPITUREN27Enable Interrupt Events via SPITUR
FRMERREN15Enable Interrupt Events via FRMERR
SPITXBEEN4Enablie Interrupt Events via SPITXBE
SPIRXBFEN0Enablie Interrupt Events via SPIRXBF

INTFLAGSPI Interrupt Flag Register

Address
0x46030020
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
SPIROV30Receive Overflow Status bit
SPITUR27Transmit Underrun Status bit
FRMERR15SPI Frame Error Status bit
SPITXBE4SPI Transmit Buffer Empty Status Bit
SPIRXBF0SPI Receive Buffer Full Status Bit

STATUSSPI Status Register

Address
0x46030024
Reset
0x90000000
Access
read only
Size
32-bit
8 fields
FieldBitsWhat it does
SPIRBF29SPI Receive Buffer Full status bit
SPITBE28SPI Transmit Buffer Empty status bit
SPITBF26SPI Transmit Buffer Full Status bit
TXBUFELM24:16Transmit Buffer Element Count bits
SPIBUSY14SPI activity status bit
SRMT13Register (SR) Empty bit
RXBUFELM8:0Receive Buffer Element Count bits
SPIRBE31RX Buffer Empty bit

BUFSPI Buffer Register

Address
0x46030028
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0FIFO Data bits

BRGSPI Baud Rate Register

Address
0x4603002C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BRG12:0Baud Rate Divisor bits

DBGCTRLSPI Debug Control Register

Address
0x46030030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DBGRUN0Debug Running State

SYNCBUSYSPI Sync Busy Register

Address
0x46030034
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
SWRSTBSY0Software reset busy bit --- Synchronizing Busy bit for swrst

EVCTRLSPI Event Control Register

Address
0x46030038
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FPSEEN0Frame Pulse Event Enable Bit