PIC32MK0128MCA028 PWM registers

The 55 registers of PWM (PWM), from 0xBF82A000, with their reset value and every field. The PIC32MK0128MCA028 has 767 registers in 65 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

PWM PWM

PTCONPWM Primary Time Base Control Register

Address
0xBF82A000
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
PTEN15PWM Module Enable bit
  • 0 PWM module is disabled
  • 1 PWM module is enabled
PTSIDL13PWM Time Base Stop in Idle Mode bit
  • 0 PWM time base runs in CPU Idle mode
  • 1 PWM time base halts in CPU Idle mode
SESTAT12Special Event Interrupt Status bit
  • 0 Special Event Interrupt is not pending
  • 1 Special Event Interrupt is pending
SEIEN11Special Event Interrupt Enable bit
  • 0 Special Event Interrupt is disabled
  • 1 Special Event Interrupt is enabled
PWMRDY10PWM Module Status bit
  • 0 PWM module is not ready
  • 1 PWM module is ready and operation has begun
PCLKDIV6:4Primary PWM Input Clock Prescaler bits
  • 0 Divide by 1
  • 1 Divide by 2
  • 2 Divide by 4
  • 3 Divide by 8
  • 4 Divide by 16
  • 5 Divide by 32
  • 6 Divide by 64
  • 7 Divide by 128
SEVTPS3:0PWM Special Event Trigger Output Postscaler Select bits
  • 0 1:1 postscaler generates Special Event trigger at every compare match event
  • 1 1:2 postscaler generates Special Event trigger at every second compare match event
  • 2 1:3 postscaler generates Special Event trigger at every 3rd compare match event
  • 3 1:4 postscaler generates Special Event trigger at every 4th compare match event
  • 4 1:5 postscaler generates Special Event trigger at every 5th compare match event
  • 5 1:6 postscaler generates Special Event trigger at every 6th compare match event
  • 6 1:7 postscaler generates Special Event trigger at every 7th compare match event
  • 7 1:8 postscaler generates Special Event trigger at every 8th compare match event
  • 8 1:9 postscaler generates Special Event trigger at every 9th compare match event
  • 9 1:10 postscaler generates Special Event trigger at every 10th compare match event
  • 10 1:11 postscaler generates Special Event trigger at every 11th compare match event
  • 11 1:12 postscaler generates Special Event trigger at every 12th compare match event
  • 12 1:13 postscaler generates Special Event trigger at every 13th compare match event
  • 13 1:14 postscaler generates Special Event trigger at every 14th compare match event
  • 14 1:15 postscaler generates Special Event trigger at every 15th compare match event
  • 15 1:16 postscaler generates Special Event trigger at every 16th compare match event

PTPERPrimary Master Time Base Period Register

Address
0xBF82A010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PTPER15:0Primary Master Time Base Period Value bits
  • 8 Minimum value

SEVTCMPPWM Primary Special Event Compare Register

Address
0xBF82A020
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SEVTCMP15:0Special Event Compare Count Value bits
  • 0 trigger at period boundary

STCONSecondary Master Time Base Control Register

Address
0xBF82A040
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
SSESTAT12Secondary Special Event Interrupt Status bit
  • 0 Secondary Special Event Interrupt is not pending
  • 1 Secondary Special Event Interrupt is pending
SSEIEN11Secondary Special Event Interrupt Enable bit
  • 0 Secondary Special Event Interrupt is disabled
  • 1 Secondary Special Event Interrupt is enabled
SCLKDIV6:4Secondary PWM Input Clock Prescaler
  • 0 Divide by 1
  • 1 Divide by 2
  • 2 Divide by 4
  • 3 Divide by 8
  • 4 Divide by 16
  • 5 Divide by 32
  • 6 Divide by 64
  • 7 Divide by 128
SEVTPS3:0PWM Secondary Special Event Trigger Output Postscaler Select bits
  • 0 1:1 Postscale
  • 1 1:2 Postscale
  • 2 1:3 Postscale
  • 3 1:4 Postscale
  • 4 1:5 Postscale
  • 5 1:6 Postscale
  • 6 1:7 Postscale
  • 7 1:8 Postscale
  • 8 1:9 Postscale
  • 9 1:10 Postscale
  • 10 1:11 Postscale
  • 11 1:12 Postscale
  • 12 1:13 Postscale
  • 13 1:14 Postscale
  • 14 1:15 Postscale
  • 15 1:16 Postscale

SSEVTCMPPWM Secondary Special Event Compare Register

Address
0xBF82A060
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SSEVTCMP15:0Secondary Special Event Compare Value bits
  • 0 Trigger at period boundary

CHOPPWM Chop Clock Generator Register

Address
0xBF82A080
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
CHPCLKEN15Enable Chop Clock Generator bit
  • 0 Chop clock generator is disabled
  • 1 Chop clock generator is enabled
CHOPCLK9:0Chop Clock Divider bits
  • 0 Minimum value

PWMKEYPWM Unlock Register

Address
0xBF82A090
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PWMKEY15:0

PWMCON1PWM Control Register x (x = 1 through 12)

Address
0xBF82A0C0
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CLIF30Current-Limit Status bit
  • 0 Current limit has not occurred
  • 1 Current limit has occurred
TRGIF29Trigger Interrupt Status bit
  • 0 Trigger interrupt is not pending
  • 1 Trigger interrupt is pending
PWMLIF28PWML Interrupt Status bit
  • 0 PWM Interrupt has not occurred
  • 1 PWM Timer equal to 0x4 interrupt has occurred
PWMHIF27PWMH Interrupt Status bit
  • 0 PWM period match interrupt has not occurred
  • 1 PWM period match interrupt has occurred
FLTIEN23Fault Interrupt Enable bit
  • 0 Fault interrupt is disabled
  • 1 Fault interrupt is enabled. If FLTIF is 1 an interrupt event will be generated
CLIEN22Current-Limit Interrupt Enable bit
  • 0 Current-limit interrupt is disabled
  • 1 Current-limit interrupt is enabled. If CLIF is 1 an interrupt event will be generated
TRGIEN21Primary Trigger Interrupt Enable bit
  • 0 A primary trigger event interrupts request is disabled
  • 1 A primary trigger event generates an interrupt request
PWMLIEN20PWM Low Phase Interrupt Enable bit
  • 0 PWM Period event interrupt request is disabled
  • 1 When the PWM Timer is equal to 0x4, the PWMLIF flag is 1 and generates an interrupt request
PWMHIEN19PWM High Phase Interrupt Enable bit
  • 0 PWM Period event interrupt request is disabled
  • 1 When the PWM Period matches the value in the PWM timer
FLTSTAT15Fault Interrupt Status bit (This bit is cleared by setting FLTIEN to 0)
  • 0 No fault interrupt is pending
  • 1 Fault interrupt is pending
CLTSTAT14Current-Limit Interrupt Status bit (This bit is cleared by setting CLIEN to 0)
  • 0 No current-limit interrupt is pending
  • 1 Current-limit interrupt is pending
ECAM11:10Edge/Center-Aligned Mode Enable bits
  • 0 Edge-Aligned mode (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
  • 1 Symmetric Center-Aligned mode (PWM(min) Duty Cycle Resolution = (2/FSYSCLK))
  • 2 Asymmetric Center-Aligned mode double update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
  • 3 Asymmetric Center-Aligned mode with simultaneous update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
ITB9Independent Time Base Mode bit
  • 0 PTPER/STPER register provides timing for this PWM generator based on the MTBS bit
  • 1 PHASEx registers provide time base period for this PWM generator
DTC7:6Dead Time Control bits
  • 0 Positive dead time actively applied for all output modes
  • 1 Negative dead time actively applied for Complementary Output mode(5)
  • 2 Dead time function is disabled
  • 3 Dead Time Compensation mode enabled
DTCP5Dead Time Compensation Polarity bit
  • 0 (If DTCMPx pin is 0)PWMxH is shortened, and PWMxL is lengthened / (If DTCMPx pin is 1)PWMxL is shortened, and PWMxH is lengthened
  • 1 (If DTCMPx pin is 0)PWMxL is shortened, and PWMxH is lengthened / (If DTCMPx pin is 1)PWMxH is shortened, and PWMxL is lengthened
PTDIR4PWM Timer Direction bit
  • 0 PWM timer is incrementing
  • 1 PWM timer is decrementing
MTBS3Master Time Base Select bit
  • 0 Primary master time base is the clock source for the MCPWM module
  • 1 Secondary master time base is the clock source for the MCPWM module
XPRES1External PWM Reset Control bit
  • 0 External pins do not affect PWM time base
  • 1 Current-limit source resets primary local time base for this PWM generator if it is in Independent Time Base mode and the PWM module enters the deassertion portion of the duty cycle
FLTIF31Fault Interrupt Flag bit
  • 0 Fault interrupt has not occurred
  • 1 Fault interrupt has occurred

IOCON1PWMx I/O Control Register x (x = 1 through 12)

Address
0xBF82A0D0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
CLSRC29:26Current-Limit Control Signal Source select bit for PWM Generator x
  • 0 FLT1
  • 1 FLT2
  • 2 FLT3
  • 3 FLT4
  • 4 FLT5
  • 5 FLT6
  • 6 FLT7
  • 7 FLT8
  • 8 Comparator 1
  • 9 Comparator 2
  • 10 Comparator 3
  • 11 Comparator 4
  • 12 Comparator 5
  • 15 FLT15
CLPOL25Current-Limit Polarity bits for PWM Generator x
  • 0 The selected current-limit source is active-high
  • 1 The selected current-limit source is active-low
CLMOD24Current-Limit Mode Enable bit for PWM Generator x
  • 0 Current-limit function is disabled
  • 1 Current-limit function is enabled
FLTSRC22:19Fault Control Signal Source Select bits for PWM Generator x
  • 0 FLT1
  • 1 FLT2
  • 2 FLT3
  • 3 FLT4
  • 4 FLT5
  • 5 FLT6
  • 6 FLT7
  • 7 FLT8
  • 8 Comparator 1
  • 9 Comparator 2
  • 10 Comparator 3
  • 11 Comparator 4
  • 12 Comparator 5
  • 15 FLT15
FLTPOL18Fault Polarity bits for PWM Generator x
  • 0 The selected fault source is active-high
  • 1 The selected fault source is active-low
FLTMOD17:16Fault Mode bits for PWM Generator x
  • 0 Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (Latched condition)
  • 1 Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle by cycle)
  • 3 Fault input is disabled
PENH15PWMxH Output Pin Ownership bit
  • 0 GPIO module controls PWMxH pin
  • 1 PWM module controls PWMxH pin
PENL14PWMxL Output Pin Ownership bit
  • 0 GPIO module controls PWMxL pin
  • 1 PWM module controls PWMxL pin
POLH13PWMxH Output Pin Polarity bit
  • 0 PWMxH pin is active-high
  • 1 PWMxH pin is active-low
POLL12PWMxL Output Pin Polarity bit
  • 0 PWMxL pin is active-high
  • 1 PWMxL pin is active-low
PMOD11:10PWM x I/O Pin Mode bits
  • 0 PWM I/O pin pair is in Complementary Output mode
  • 1 PWM I/O pin pair is in Redundant Output mode
  • 2 PWM I/O pin pair is in Push-Pull Output mode
  • 3 PWMxL output is held at logic 0 (adjusted by the POLL bit)
OVRENH9Override Enable for PWMxH Pin bit
  • 0 PWM generator provides data for PWMxH pin
  • 1 OVRDAT provides data for output on PWMxH pin
OVRENL8Override Enable for PWMxL Pin bit
  • 0 PWM generator provides data for PWMxL pin
  • 1 OVRDAT provides data for output on PWMxL pin
OVRDAT7:6
FLTDAT5:4
CLDAT3:2
SWAP1SWAP PWMxH and PWMxL Pins bit
  • 0 PWMxH and PWMxL output signals pins are mapped to their respective pins
  • 1 PWMxH output signal is connected to PWMxL pin; PWMxL output signal is connected to PWMxH pin
OSYNC0Output Override Synchronization bit
  • 0 Output overrides through the OVRDAT bits occur on next CPU clock boundary
  • 1 Output overrides through the OVRDAT bits are synchronized to the PWM time base

PDC1

Address
0xBF82A0E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PDC15:0

SDC1

Address
0xBF82A0F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SDC15:0

PHASE1

Address
0xBF82A100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PHASE15:0

DTR1

Address
0xBF82A110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DTR15:0

ALTDTR1

Address
0xBF82A120
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ALTDTR15:0

TRIG1

Address
0xBF82A140
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TRGCMP15:0

STRIG1

Address
0xBF82A160
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
STRGCMP15:0

LEBCON1Leading-Edge Blanking Control Register x (x = 1 through 12)

Address
0xBF82A180
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
PHR15PWMxH Rising Edge Trigger Enable bit
  • 0 Rising edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Rising edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
PHF14PWMxH Falling Edge Trigger Enable bit
  • 0 Falling edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Falling edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
PLR13PWMxL Rising Edge Trigger Enable bit
  • 0 Rising edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Rising edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
PLF12PWMxL Falling Edge Trigger Enable bit
  • 0 Falling edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Falling edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
FLTLEBEN11Fault Input Leading-Edge Blanking Enable bit
  • 0 Leading-Edge Blanking is not applied to selected fault input
  • 1 Leading-Edge Blanking is applied to selected fault input
CLLEBEN10Current-Limit Leading-Edge Blanking Enable bit
  • 0 Leading-Edge Blanking is not applied to selected current-limit input
  • 1 Leading-Edge Blanking is applied to selected current-limit input

LEBDLY1

Address
0xBF82A190
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
LEB11:0

AUXCON1PWM Auxiliary Control Register x (x = 1 through 12)

Address
0xBF82A1A0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
CHOPSEL5:2PWM Chop Clock Source Select bits
  • 0 Chop clock generator selected as CHOP clock source
  • 1 PWM1H selected as CHOP clock source
  • 2 PWM2H selected as CHOP clock source
  • 3 PWM3H selected as CHOP clock source
  • 4 PWM4H selected as CHOP clock source
  • 5 PWM5H selected as CHOP clock source
  • 6 PWM6H selected as CHOP clock source
  • 7 PWM7H selected as CHOP clock source
  • 8 PWM8H selected as CHOP clock source
  • 9 PWM9H selected as CHOP clock source
  • 10 PWM10H selected as CHOP clock source
  • 11 PWM11H selected as CHOP clock source
  • 12 PWM12H selected as CHOP clock source
CHOPHEN1PWMxH Output Chopping Enable bit
  • 0 PWMxH chopping function is disabled
  • 1 PWMxH chopping function is enabled
CHOPLEN0PWMxL Output Chopping Enable bit
  • 0 PWMxL chopping function is disabled
  • 1 PWMxL chopping function is enabled

PWMCON2PWM Control Register x (x = 1 through 12)

Address
0xBF82A1C0
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CLIF30Current-Limit Status bit
  • 0 Current limit has not occurred
  • 1 Current limit has occurred
TRGIF29Trigger Interrupt Status bit
  • 0 Trigger interrupt is not pending
  • 1 Trigger interrupt is pending
PWMLIF28PWML Interrupt Status bit
  • 0 PWM Interrupt has not occurred
  • 1 PWM Timer equal to 0x4 interrupt has occurred
PWMHIF27PWMH Interrupt Status bit
  • 0 PWM period match interrupt has not occurred
  • 1 PWM period match interrupt has occurred
FLTIEN23Fault Interrupt Enable bit
  • 0 Fault interrupt is disabled
  • 1 Fault interrupt is enabled. If FLTIF is 1 an interrupt event will be generated
CLIEN22Current-Limit Interrupt Enable bit
  • 0 Current-limit interrupt is disabled
  • 1 Current-limit interrupt is enabled. If CLIF is 1 an interrupt event will be generated
TRGIEN21Primary Trigger Interrupt Enable bit
  • 0 A primary trigger event interrupts request is disabled
  • 1 A primary trigger event generates an interrupt request
PWMLIEN20PWM Low Phase Interrupt Enable bit
  • 0 PWM Period event interrupt request is disabled
  • 1 When the PWM Timer is equal to 0x4, the PWMLIF flag is 1 and generates an interrupt request
PWMHIEN19PWM High Phase Interrupt Enable bit
  • 0 PWM Period event interrupt request is disabled
  • 1 When the PWM Period matches the value in the PWM timer
FLTSTAT15Fault Interrupt Status bit (This bit is cleared by setting FLTIEN to 0)
  • 0 No fault interrupt is pending
  • 1 Fault interrupt is pending
CLTSTAT14Current-Limit Interrupt Status bit (This bit is cleared by setting CLIEN to 0)
  • 0 No current-limit interrupt is pending
  • 1 Current-limit interrupt is pending
ECAM11:10Edge/Center-Aligned Mode Enable bits
  • 0 Edge-Aligned mode (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
  • 1 Symmetric Center-Aligned mode (PWM(min) Duty Cycle Resolution = (2/FSYSCLK))
  • 2 Asymmetric Center-Aligned mode double update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
  • 3 Asymmetric Center-Aligned mode with simultaneous update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
ITB9Independent Time Base Mode bit
  • 0 PTPER/STPER register provides timing for this PWM generator based on the MTBS bit
  • 1 PHASEx registers provide time base period for this PWM generator
DTC7:6Dead Time Control bits
  • 0 Positive dead time actively applied for all output modes
  • 1 Negative dead time actively applied for Complementary Output mode(5)
  • 2 Dead time function is disabled
  • 3 Dead Time Compensation mode enabled
DTCP5Dead Time Compensation Polarity bit
  • 0 (If DTCMPx pin is 0)PWMxH is shortened, and PWMxL is lengthened / (If DTCMPx pin is 1)PWMxL is shortened, and PWMxH is lengthened
  • 1 (If DTCMPx pin is 0)PWMxL is shortened, and PWMxH is lengthened / (If DTCMPx pin is 1)PWMxH is shortened, and PWMxL is lengthened
PTDIR4PWM Timer Direction bit
  • 0 PWM timer is incrementing
  • 1 PWM timer is decrementing
MTBS3Master Time Base Select bit
  • 0 Primary master time base is the clock source for the MCPWM module
  • 1 Secondary master time base is the clock source for the MCPWM module
XPRES1External PWM Reset Control bit
  • 0 External pins do not affect PWM time base
  • 1 Current-limit source resets primary local time base for this PWM generator if it is in Independent Time Base mode and the PWM module enters the deassertion portion of the duty cycle
FLTIF31Fault Interrupt Flag bit
  • 0 Fault interrupt has not occurred
  • 1 Fault interrupt has occurred

IOCON2PWMx I/O Control Register x (x = 1 through 12)

Address
0xBF82A1D0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
CLSRC29:26Current-Limit Control Signal Source select bit for PWM Generator x
  • 0 FLT1
  • 1 FLT2
  • 2 FLT3
  • 3 FLT4
  • 4 FLT5
  • 5 FLT6
  • 6 FLT7
  • 7 FLT8
  • 8 Comparator 1
  • 9 Comparator 2
  • 10 Comparator 3
  • 11 Comparator 4
  • 12 Comparator 5
  • 15 FLT15
CLPOL25Current-Limit Polarity bits for PWM Generator x
  • 0 The selected current-limit source is active-high
  • 1 The selected current-limit source is active-low
CLMOD24Current-Limit Mode Enable bit for PWM Generator x
  • 0 Current-limit function is disabled
  • 1 Current-limit function is enabled
FLTSRC22:19Fault Control Signal Source Select bits for PWM Generator x
  • 0 FLT1
  • 1 FLT2
  • 2 FLT3
  • 3 FLT4
  • 4 FLT5
  • 5 FLT6
  • 6 FLT7
  • 7 FLT8
  • 8 Comparator 1
  • 9 Comparator 2
  • 10 Comparator 3
  • 11 Comparator 4
  • 12 Comparator 5
  • 15 FLT15
FLTPOL18Fault Polarity bits for PWM Generator x
  • 0 The selected fault source is active-high
  • 1 The selected fault source is active-low
FLTMOD17:16Fault Mode bits for PWM Generator x
  • 0 Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (Latched condition)
  • 1 Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle by cycle)
  • 3 Fault input is disabled
PENH15PWMxH Output Pin Ownership bit
  • 0 GPIO module controls PWMxH pin
  • 1 PWM module controls PWMxH pin
PENL14PWMxL Output Pin Ownership bit
  • 0 GPIO module controls PWMxL pin
  • 1 PWM module controls PWMxL pin
POLH13PWMxH Output Pin Polarity bit
  • 0 PWMxH pin is active-high
  • 1 PWMxH pin is active-low
POLL12PWMxL Output Pin Polarity bit
  • 0 PWMxL pin is active-high
  • 1 PWMxL pin is active-low
PMOD11:10PWM x I/O Pin Mode bits
  • 0 PWM I/O pin pair is in Complementary Output mode
  • 1 PWM I/O pin pair is in Redundant Output mode
  • 2 PWM I/O pin pair is in Push-Pull Output mode
  • 3 PWMxL output is held at logic 0 (adjusted by the POLL bit)
OVRENH9Override Enable for PWMxH Pin bit
  • 0 PWM generator provides data for PWMxH pin
  • 1 OVRDAT provides data for output on PWMxH pin
OVRENL8Override Enable for PWMxL Pin bit
  • 0 PWM generator provides data for PWMxL pin
  • 1 OVRDAT provides data for output on PWMxL pin
OVRDAT7:6
FLTDAT5:4
CLDAT3:2
SWAP1SWAP PWMxH and PWMxL Pins bit
  • 0 PWMxH and PWMxL output signals pins are mapped to their respective pins
  • 1 PWMxH output signal is connected to PWMxL pin; PWMxL output signal is connected to PWMxH pin
OSYNC0Output Override Synchronization bit
  • 0 Output overrides through the OVRDAT bits occur on next CPU clock boundary
  • 1 Output overrides through the OVRDAT bits are synchronized to the PWM time base

PDC2

Address
0xBF82A1E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PDC15:0

SDC2

Address
0xBF82A1F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SDC15:0

PHASE2

Address
0xBF82A200
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PHASE15:0

DTR2

Address
0xBF82A210
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DTR15:0

ALTDTR2

Address
0xBF82A220
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ALTDTR15:0

TRIG2

Address
0xBF82A240
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TRGCMP15:0

STRIG2

Address
0xBF82A260
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
STRGCMP15:0

LEBCON2Leading-Edge Blanking Control Register x (x = 1 through 12)

Address
0xBF82A280
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
PHR15PWMxH Rising Edge Trigger Enable bit
  • 0 Rising edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Rising edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
PHF14PWMxH Falling Edge Trigger Enable bit
  • 0 Falling edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Falling edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
PLR13PWMxL Rising Edge Trigger Enable bit
  • 0 Rising edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Rising edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
PLF12PWMxL Falling Edge Trigger Enable bit
  • 0 Falling edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Falling edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
FLTLEBEN11Fault Input Leading-Edge Blanking Enable bit
  • 0 Leading-Edge Blanking is not applied to selected fault input
  • 1 Leading-Edge Blanking is applied to selected fault input
CLLEBEN10Current-Limit Leading-Edge Blanking Enable bit
  • 0 Leading-Edge Blanking is not applied to selected current-limit input
  • 1 Leading-Edge Blanking is applied to selected current-limit input

LEBDLY2

Address
0xBF82A290
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
LEB11:0

AUXCON2PWM Auxiliary Control Register x (x = 1 through 12)

Address
0xBF82A2A0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
CHOPSEL5:2PWM Chop Clock Source Select bits
  • 0 Chop clock generator selected as CHOP clock source
  • 1 PWM1H selected as CHOP clock source
  • 2 PWM2H selected as CHOP clock source
  • 3 PWM3H selected as CHOP clock source
  • 4 PWM4H selected as CHOP clock source
  • 5 PWM5H selected as CHOP clock source
  • 6 PWM6H selected as CHOP clock source
  • 7 PWM7H selected as CHOP clock source
  • 8 PWM8H selected as CHOP clock source
  • 9 PWM9H selected as CHOP clock source
  • 10 PWM10H selected as CHOP clock source
  • 11 PWM11H selected as CHOP clock source
  • 12 PWM12H selected as CHOP clock source
CHOPHEN1PWMxH Output Chopping Enable bit
  • 0 PWMxH chopping function is disabled
  • 1 PWMxH chopping function is enabled
CHOPLEN0PWMxL Output Chopping Enable bit
  • 0 PWMxL chopping function is disabled
  • 1 PWMxL chopping function is enabled

PWMCON3PWM Control Register x (x = 1 through 12)

Address
0xBF82A2C0
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CLIF30Current-Limit Status bit
  • 0 Current limit has not occurred
  • 1 Current limit has occurred
TRGIF29Trigger Interrupt Status bit
  • 0 Trigger interrupt is not pending
  • 1 Trigger interrupt is pending
PWMLIF28PWML Interrupt Status bit
  • 0 PWM Interrupt has not occurred
  • 1 PWM Timer equal to 0x4 interrupt has occurred
PWMHIF27PWMH Interrupt Status bit
  • 0 PWM period match interrupt has not occurred
  • 1 PWM period match interrupt has occurred
FLTIEN23Fault Interrupt Enable bit
  • 0 Fault interrupt is disabled
  • 1 Fault interrupt is enabled. If FLTIF is 1 an interrupt event will be generated
CLIEN22Current-Limit Interrupt Enable bit
  • 0 Current-limit interrupt is disabled
  • 1 Current-limit interrupt is enabled. If CLIF is 1 an interrupt event will be generated
TRGIEN21Primary Trigger Interrupt Enable bit
  • 0 A primary trigger event interrupts request is disabled
  • 1 A primary trigger event generates an interrupt request
PWMLIEN20PWM Low Phase Interrupt Enable bit
  • 0 PWM Period event interrupt request is disabled
  • 1 When the PWM Timer is equal to 0x4, the PWMLIF flag is 1 and generates an interrupt request
PWMHIEN19PWM High Phase Interrupt Enable bit
  • 0 PWM Period event interrupt request is disabled
  • 1 When the PWM Period matches the value in the PWM timer
FLTSTAT15Fault Interrupt Status bit (This bit is cleared by setting FLTIEN to 0)
  • 0 No fault interrupt is pending
  • 1 Fault interrupt is pending
CLTSTAT14Current-Limit Interrupt Status bit (This bit is cleared by setting CLIEN to 0)
  • 0 No current-limit interrupt is pending
  • 1 Current-limit interrupt is pending
ECAM11:10Edge/Center-Aligned Mode Enable bits
  • 0 Edge-Aligned mode (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
  • 1 Symmetric Center-Aligned mode (PWM(min) Duty Cycle Resolution = (2/FSYSCLK))
  • 2 Asymmetric Center-Aligned mode double update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
  • 3 Asymmetric Center-Aligned mode with simultaneous update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
ITB9Independent Time Base Mode bit
  • 0 PTPER/STPER register provides timing for this PWM generator based on the MTBS bit
  • 1 PHASEx registers provide time base period for this PWM generator
DTC7:6Dead Time Control bits
  • 0 Positive dead time actively applied for all output modes
  • 1 Negative dead time actively applied for Complementary Output mode(5)
  • 2 Dead time function is disabled
  • 3 Dead Time Compensation mode enabled
DTCP5Dead Time Compensation Polarity bit
  • 0 (If DTCMPx pin is 0)PWMxH is shortened, and PWMxL is lengthened / (If DTCMPx pin is 1)PWMxL is shortened, and PWMxH is lengthened
  • 1 (If DTCMPx pin is 0)PWMxL is shortened, and PWMxH is lengthened / (If DTCMPx pin is 1)PWMxH is shortened, and PWMxL is lengthened
PTDIR4PWM Timer Direction bit
  • 0 PWM timer is incrementing
  • 1 PWM timer is decrementing
MTBS3Master Time Base Select bit
  • 0 Primary master time base is the clock source for the MCPWM module
  • 1 Secondary master time base is the clock source for the MCPWM module
XPRES1External PWM Reset Control bit
  • 0 External pins do not affect PWM time base
  • 1 Current-limit source resets primary local time base for this PWM generator if it is in Independent Time Base mode and the PWM module enters the deassertion portion of the duty cycle
FLTIF31Fault Interrupt Flag bit
  • 0 Fault interrupt has not occurred
  • 1 Fault interrupt has occurred

IOCON3PWMx I/O Control Register x (x = 1 through 12)

Address
0xBF82A2D0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
CLSRC29:26Current-Limit Control Signal Source select bit for PWM Generator x
  • 0 FLT1
  • 1 FLT2
  • 2 FLT3
  • 3 FLT4
  • 4 FLT5
  • 5 FLT6
  • 6 FLT7
  • 7 FLT8
  • 8 Comparator 1
  • 9 Comparator 2
  • 10 Comparator 3
  • 11 Comparator 4
  • 12 Comparator 5
  • 15 FLT15
CLPOL25Current-Limit Polarity bits for PWM Generator x
  • 0 The selected current-limit source is active-high
  • 1 The selected current-limit source is active-low
CLMOD24Current-Limit Mode Enable bit for PWM Generator x
  • 0 Current-limit function is disabled
  • 1 Current-limit function is enabled
FLTSRC22:19Fault Control Signal Source Select bits for PWM Generator x
  • 0 FLT1
  • 1 FLT2
  • 2 FLT3
  • 3 FLT4
  • 4 FLT5
  • 5 FLT6
  • 6 FLT7
  • 7 FLT8
  • 8 Comparator 1
  • 9 Comparator 2
  • 10 Comparator 3
  • 11 Comparator 4
  • 12 Comparator 5
  • 15 FLT15
FLTPOL18Fault Polarity bits for PWM Generator x
  • 0 The selected fault source is active-high
  • 1 The selected fault source is active-low
FLTMOD17:16Fault Mode bits for PWM Generator x
  • 0 Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (Latched condition)
  • 1 Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle by cycle)
  • 3 Fault input is disabled
PENH15PWMxH Output Pin Ownership bit
  • 0 GPIO module controls PWMxH pin
  • 1 PWM module controls PWMxH pin
PENL14PWMxL Output Pin Ownership bit
  • 0 GPIO module controls PWMxL pin
  • 1 PWM module controls PWMxL pin
POLH13PWMxH Output Pin Polarity bit
  • 0 PWMxH pin is active-high
  • 1 PWMxH pin is active-low
POLL12PWMxL Output Pin Polarity bit
  • 0 PWMxL pin is active-high
  • 1 PWMxL pin is active-low
PMOD11:10PWM x I/O Pin Mode bits
  • 0 PWM I/O pin pair is in Complementary Output mode
  • 1 PWM I/O pin pair is in Redundant Output mode
  • 2 PWM I/O pin pair is in Push-Pull Output mode
  • 3 PWMxL output is held at logic 0 (adjusted by the POLL bit)
OVRENH9Override Enable for PWMxH Pin bit
  • 0 PWM generator provides data for PWMxH pin
  • 1 OVRDAT provides data for output on PWMxH pin
OVRENL8Override Enable for PWMxL Pin bit
  • 0 PWM generator provides data for PWMxL pin
  • 1 OVRDAT provides data for output on PWMxL pin
OVRDAT7:6
FLTDAT5:4
CLDAT3:2
SWAP1SWAP PWMxH and PWMxL Pins bit
  • 0 PWMxH and PWMxL output signals pins are mapped to their respective pins
  • 1 PWMxH output signal is connected to PWMxL pin; PWMxL output signal is connected to PWMxH pin
OSYNC0Output Override Synchronization bit
  • 0 Output overrides through the OVRDAT bits occur on next CPU clock boundary
  • 1 Output overrides through the OVRDAT bits are synchronized to the PWM time base

PDC3

Address
0xBF82A2E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PDC15:0

SDC3

Address
0xBF82A2F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SDC15:0

PHASE3

Address
0xBF82A300
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PHASE15:0

DTR3

Address
0xBF82A310
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DTR15:0

ALTDTR3

Address
0xBF82A320
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ALTDTR15:0

TRIG3

Address
0xBF82A340
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TRGCMP15:0

STRIG3

Address
0xBF82A360
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
STRGCMP15:0

LEBCON3Leading-Edge Blanking Control Register x (x = 1 through 12)

Address
0xBF82A380
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
PHR15PWMxH Rising Edge Trigger Enable bit
  • 0 Rising edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Rising edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
PHF14PWMxH Falling Edge Trigger Enable bit
  • 0 Falling edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Falling edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
PLR13PWMxL Rising Edge Trigger Enable bit
  • 0 Rising edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Rising edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
PLF12PWMxL Falling Edge Trigger Enable bit
  • 0 Falling edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Falling edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
FLTLEBEN11Fault Input Leading-Edge Blanking Enable bit
  • 0 Leading-Edge Blanking is not applied to selected fault input
  • 1 Leading-Edge Blanking is applied to selected fault input
CLLEBEN10Current-Limit Leading-Edge Blanking Enable bit
  • 0 Leading-Edge Blanking is not applied to selected current-limit input
  • 1 Leading-Edge Blanking is applied to selected current-limit input

LEBDLY3

Address
0xBF82A390
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
LEB11:0

AUXCON3PWM Auxiliary Control Register x (x = 1 through 12)

Address
0xBF82A3A0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
CHOPSEL5:2PWM Chop Clock Source Select bits
  • 0 Chop clock generator selected as CHOP clock source
  • 1 PWM1H selected as CHOP clock source
  • 2 PWM2H selected as CHOP clock source
  • 3 PWM3H selected as CHOP clock source
  • 4 PWM4H selected as CHOP clock source
  • 5 PWM5H selected as CHOP clock source
  • 6 PWM6H selected as CHOP clock source
  • 7 PWM7H selected as CHOP clock source
  • 8 PWM8H selected as CHOP clock source
  • 9 PWM9H selected as CHOP clock source
  • 10 PWM10H selected as CHOP clock source
  • 11 PWM11H selected as CHOP clock source
  • 12 PWM12H selected as CHOP clock source
CHOPHEN1PWMxH Output Chopping Enable bit
  • 0 PWMxH chopping function is disabled
  • 1 PWMxH chopping function is enabled
CHOPLEN0PWMxL Output Chopping Enable bit
  • 0 PWMxL chopping function is disabled
  • 1 PWMxL chopping function is enabled

PWMCON4PWM Control Register x (x = 1 through 12)

Address
0xBF82A3C0
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CLIF30Current-Limit Status bit
  • 0 Current limit has not occurred
  • 1 Current limit has occurred
TRGIF29Trigger Interrupt Status bit
  • 0 Trigger interrupt is not pending
  • 1 Trigger interrupt is pending
PWMLIF28PWML Interrupt Status bit
  • 0 PWM Interrupt has not occurred
  • 1 PWM Timer equal to 0x4 interrupt has occurred
PWMHIF27PWMH Interrupt Status bit
  • 0 PWM period match interrupt has not occurred
  • 1 PWM period match interrupt has occurred
FLTIEN23Fault Interrupt Enable bit
  • 0 Fault interrupt is disabled
  • 1 Fault interrupt is enabled. If FLTIF is 1 an interrupt event will be generated
CLIEN22Current-Limit Interrupt Enable bit
  • 0 Current-limit interrupt is disabled
  • 1 Current-limit interrupt is enabled. If CLIF is 1 an interrupt event will be generated
TRGIEN21Primary Trigger Interrupt Enable bit
  • 0 A primary trigger event interrupts request is disabled
  • 1 A primary trigger event generates an interrupt request
PWMLIEN20PWM Low Phase Interrupt Enable bit
  • 0 PWM Period event interrupt request is disabled
  • 1 When the PWM Timer is equal to 0x4, the PWMLIF flag is 1 and generates an interrupt request
PWMHIEN19PWM High Phase Interrupt Enable bit
  • 0 PWM Period event interrupt request is disabled
  • 1 When the PWM Period matches the value in the PWM timer
FLTSTAT15Fault Interrupt Status bit (This bit is cleared by setting FLTIEN to 0)
  • 0 No fault interrupt is pending
  • 1 Fault interrupt is pending
CLTSTAT14Current-Limit Interrupt Status bit (This bit is cleared by setting CLIEN to 0)
  • 0 No current-limit interrupt is pending
  • 1 Current-limit interrupt is pending
ECAM11:10Edge/Center-Aligned Mode Enable bits
  • 0 Edge-Aligned mode (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
  • 1 Symmetric Center-Aligned mode (PWM(min) Duty Cycle Resolution = (2/FSYSCLK))
  • 2 Asymmetric Center-Aligned mode double update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
  • 3 Asymmetric Center-Aligned mode with simultaneous update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
ITB9Independent Time Base Mode bit
  • 0 PTPER/STPER register provides timing for this PWM generator based on the MTBS bit
  • 1 PHASEx registers provide time base period for this PWM generator
DTC7:6Dead Time Control bits
  • 0 Positive dead time actively applied for all output modes
  • 1 Negative dead time actively applied for Complementary Output mode(5)
  • 2 Dead time function is disabled
  • 3 Dead Time Compensation mode enabled
DTCP5Dead Time Compensation Polarity bit
  • 0 (If DTCMPx pin is 0)PWMxH is shortened, and PWMxL is lengthened / (If DTCMPx pin is 1)PWMxL is shortened, and PWMxH is lengthened
  • 1 (If DTCMPx pin is 0)PWMxL is shortened, and PWMxH is lengthened / (If DTCMPx pin is 1)PWMxH is shortened, and PWMxL is lengthened
PTDIR4PWM Timer Direction bit
  • 0 PWM timer is incrementing
  • 1 PWM timer is decrementing
MTBS3Master Time Base Select bit
  • 0 Primary master time base is the clock source for the MCPWM module
  • 1 Secondary master time base is the clock source for the MCPWM module
XPRES1External PWM Reset Control bit
  • 0 External pins do not affect PWM time base
  • 1 Current-limit source resets primary local time base for this PWM generator if it is in Independent Time Base mode and the PWM module enters the deassertion portion of the duty cycle
FLTIF31Fault Interrupt Flag bit
  • 0 Fault interrupt has not occurred
  • 1 Fault interrupt has occurred

IOCON4PWMx I/O Control Register x (x = 1 through 12)

Address
0xBF82A3D0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
CLSRC29:26Current-Limit Control Signal Source select bit for PWM Generator x
  • 0 FLT1
  • 1 FLT2
  • 2 FLT3
  • 3 FLT4
  • 4 FLT5
  • 5 FLT6
  • 6 FLT7
  • 7 FLT8
  • 8 Comparator 1
  • 9 Comparator 2
  • 10 Comparator 3
  • 11 Comparator 4
  • 12 Comparator 5
  • 15 FLT15
CLPOL25Current-Limit Polarity bits for PWM Generator x
  • 0 The selected current-limit source is active-high
  • 1 The selected current-limit source is active-low
CLMOD24Current-Limit Mode Enable bit for PWM Generator x
  • 0 Current-limit function is disabled
  • 1 Current-limit function is enabled
FLTSRC22:19Fault Control Signal Source Select bits for PWM Generator x
  • 0 FLT1
  • 1 FLT2
  • 2 FLT3
  • 3 FLT4
  • 4 FLT5
  • 5 FLT6
  • 6 FLT7
  • 7 FLT8
  • 8 Comparator 1
  • 9 Comparator 2
  • 10 Comparator 3
  • 11 Comparator 4
  • 12 Comparator 5
  • 15 FLT15
FLTPOL18Fault Polarity bits for PWM Generator x
  • 0 The selected fault source is active-high
  • 1 The selected fault source is active-low
FLTMOD17:16Fault Mode bits for PWM Generator x
  • 0 Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (Latched condition)
  • 1 Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle by cycle)
  • 3 Fault input is disabled
PENH15PWMxH Output Pin Ownership bit
  • 0 GPIO module controls PWMxH pin
  • 1 PWM module controls PWMxH pin
PENL14PWMxL Output Pin Ownership bit
  • 0 GPIO module controls PWMxL pin
  • 1 PWM module controls PWMxL pin
POLH13PWMxH Output Pin Polarity bit
  • 0 PWMxH pin is active-high
  • 1 PWMxH pin is active-low
POLL12PWMxL Output Pin Polarity bit
  • 0 PWMxL pin is active-high
  • 1 PWMxL pin is active-low
PMOD11:10PWM x I/O Pin Mode bits
  • 0 PWM I/O pin pair is in Complementary Output mode
  • 1 PWM I/O pin pair is in Redundant Output mode
  • 2 PWM I/O pin pair is in Push-Pull Output mode
  • 3 PWMxL output is held at logic 0 (adjusted by the POLL bit)
OVRENH9Override Enable for PWMxH Pin bit
  • 0 PWM generator provides data for PWMxH pin
  • 1 OVRDAT provides data for output on PWMxH pin
OVRENL8Override Enable for PWMxL Pin bit
  • 0 PWM generator provides data for PWMxL pin
  • 1 OVRDAT provides data for output on PWMxL pin
OVRDAT7:6
FLTDAT5:4
CLDAT3:2
SWAP1SWAP PWMxH and PWMxL Pins bit
  • 0 PWMxH and PWMxL output signals pins are mapped to their respective pins
  • 1 PWMxH output signal is connected to PWMxL pin; PWMxL output signal is connected to PWMxH pin
OSYNC0Output Override Synchronization bit
  • 0 Output overrides through the OVRDAT bits occur on next CPU clock boundary
  • 1 Output overrides through the OVRDAT bits are synchronized to the PWM time base

PDC4

Address
0xBF82A3E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PDC15:0

SDC4

Address
0xBF82A3F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SDC15:0

PHASE4

Address
0xBF82A400
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PHASE15:0

DTR4

Address
0xBF82A410
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DTR15:0

ALTDTR4

Address
0xBF82A420
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ALTDTR15:0

TRIG4

Address
0xBF82A440
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TRGCMP15:0

STRIG4

Address
0xBF82A460
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
STRGCMP15:0

LEBCON4Leading-Edge Blanking Control Register x (x = 1 through 12)

Address
0xBF82A480
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
PHR15PWMxH Rising Edge Trigger Enable bit
  • 0 Rising edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Rising edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
PHF14PWMxH Falling Edge Trigger Enable bit
  • 0 Falling edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Falling edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
PLR13PWMxL Rising Edge Trigger Enable bit
  • 0 Rising edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Rising edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
PLF12PWMxL Falling Edge Trigger Enable bit
  • 0 Falling edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
  • 1 Falling edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
FLTLEBEN11Fault Input Leading-Edge Blanking Enable bit
  • 0 Leading-Edge Blanking is not applied to selected fault input
  • 1 Leading-Edge Blanking is applied to selected fault input
CLLEBEN10Current-Limit Leading-Edge Blanking Enable bit
  • 0 Leading-Edge Blanking is not applied to selected current-limit input
  • 1 Leading-Edge Blanking is applied to selected current-limit input

LEBDLY4

Address
0xBF82A490
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
LEB11:0

AUXCON4PWM Auxiliary Control Register x (x = 1 through 12)

Address
0xBF82A4A0
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
CHOPSEL5:2PWM Chop Clock Source Select bits
  • 0 Chop clock generator selected as CHOP clock source
  • 1 PWM1H selected as CHOP clock source
  • 2 PWM2H selected as CHOP clock source
  • 3 PWM3H selected as CHOP clock source
  • 4 PWM4H selected as CHOP clock source
  • 5 PWM5H selected as CHOP clock source
  • 6 PWM6H selected as CHOP clock source
  • 7 PWM7H selected as CHOP clock source
  • 8 PWM8H selected as CHOP clock source
  • 9 PWM9H selected as CHOP clock source
  • 10 PWM10H selected as CHOP clock source
  • 11 PWM11H selected as CHOP clock source
  • 12 PWM12H selected as CHOP clock source
CHOPHEN1PWMxH Output Chopping Enable bit
  • 0 PWMxH chopping function is disabled
  • 1 PWMxH chopping function is enabled
CHOPLEN0PWMxL Output Chopping Enable bit
  • 0 PWMxL chopping function is disabled
  • 1 PWMxL chopping function is enabled