The 6 registers of RTCC (Real-time clock and calendar), from 0xBF8C0000, with their reset value and every field. The PIC32MK0128MCA048 has 785 registers in 65 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
RTCC Real-time clock and calendar
RTCCONReal-Time Clock and Calendar Control Register
Address
0xBF8C0000
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
CAL
25:16
Real-Time Clock Drift Calibration bits
0 No adjustment
1 Minimum positive adjustment
511 Maximum positive adjustment
512 Minimum negative adjustment
1023 Minimum negative adjustment
ON
15
RTCC On bit
0 RTCC module is disabled
1 RTCC module is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue normal operation when CPU enters Idle mode
1 Disables RTCC operation when CPU enters Idle mode
RTCCLKSEL
10:9
RTCC Clock Select bits
0 RTCC uses the internal 32 kHz oscillator (LPRC)
1 RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC)
RTCOUTSEL
8:7
RTCC Output Data Select bits
0 Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered
1 Seconds Clock is presented on the RTCC pin
2 RTCC Clock is presented on the RTCC pin
RTCCLKON
6
RTCC Clock Enable Status bit
0 RTCC Clock is not running
1 RTCC Clock is actively running
RTCWREN
3
Real-Time Clock Value Registers Write Enable bit
0 Real-Time Clock Value registers are locked out from being written to by the user
1 Real-Time Clock Value registers can be written to by the user
RTCSYNC
2
Real-Time Clock Value Registers Read Synchronization bit
0 Real-time clock value registers can be read without concern about a rollover ripple
1 Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid data read). If the register is read twice and results in the same data
HALFSEC
1
Half-Second Status bit
0 First half period of a second
1 Second half period of a second
RTCOE
0
RTCC Output Enable bit
0 RTCC output is not enabled
1 RTCC output is enabled
RTCALRMReal-Time Clock ALARM Control Register
Address
0xBF8C0010
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ALRMEN
15
Alarm Enable bit
0 Alarm is disabled
1 Alarm is enabled
CHIME
14
Chime Enable bit
0 Chime is disabled ARPT stops once it reaches 0x00
1 Chime is enabled ARPT is allowed to rollover from 0x00 to 0xFF
PIV
13
Alarm Pulse Initial Value bit
0 low initial value of the Alarm Pulse (When ALRMEN = 0)
1 high initial value of the Alarm Pulse (When ALRMEN = 0)
ALRMSYNC
12
Alarm Sync bit
0 ARPT and ALRMEN can be read without concerns of rollover because the prescaler is more than 32 real-time clocks away from a half-second rollover
1 ARPT and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing.
AMASK
11:8
Alarm Mask Configuration bits
0 Every half-second
1 Every second
2 Every 10 seconds
3 Every minute
4 Every 10 minutes
5 Every hour
6 Once a day
7 Once a week
8 Once a month
9 Once a year (except when configured for February 29
BETA