PIC32MK0256MCJ048 CLC4 registers

The 3 registers of CLC4 (Configurable logic cell 4), from 0xBF82D800, with their reset value and every field. The PIC32MK0256MCJ048 has 1276 registers in 85 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CLC4 Configurable logic cell 4

CLC4CON

Address
0xBF82D800
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
G4POL19Gate 4 Polarity Control bit
  • 0 The output of Channel 4 logic is not inverted
  • 1 The output of Channel 4 logic is inverted when applied to the logic cell
G3POL18Gate 3 Polarity Control bit
  • 0 The output of Channel 3 logic is not inverted
  • 1 The output of Channel 3 logic is inverted when applied to the logic cell
G2POL17Gate 2 Polarity Control bit
  • 0 The output of Channel 2 logic is not inverted
  • 1 The output of Channel 2 logic is inverted when applied to the logic cell
G1POL16Gate 1 Polarity Control bit
  • 0 The output of Channel 1 logic is not inverted
  • 1 The output of Channel 1 logic is inverted when applied to the logic cell
ON15CLCx Enable bit
  • 0 CLCx is disabled and has logic zero outputs
  • 1 CLCx is enabled and mixing input signals
INTP11CLCx Positive Edge Interrupt Enable bit
  • 0 Interrupt will not be generated
  • 1 Interrupt will be generated when a rising edge occurs on LCOUT
INTN10CLCx Negative Edge Interrupt Enable bit
  • 0 Interrupt will not be generated
  • 1 Interrupt will be generated when a falling edge occurs on LCOUT
LCOE7CLCx Port Enable bit
  • 0 CLCx port pin output is disabled
  • 1 CLCx port pin output is enabled
LCOUT6CLCx Data Output Status bit
  • 0 CLCx output low
  • 1 CLCx output high
LCPOL5CLCx Output Polarity Control bit
  • 0 The output of the module is not inverted
  • 1 The output of the module is inverted
MODE2:0CLCx Mode bits
  • 0 Cell is a AND-OR
  • 1 Cell is an OR-XOR
  • 2 Cell is a 4-input AND
  • 3 Cell is an SR latch
  • 4 Cell is a 1-input D flip-flop with S and R
  • 5 Cell is a 2-input D flip-flop with R
  • 6 Cell is a JK flip-flop with R
  • 7 Cell is a 1-input transparent latch with S and R

CLC4SEL

Address
0xBF82D810
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DS414:12Data Selection MUX 4 Signal Selection bits
  • 0 CLCIND I/O pin
  • 1 CLC4 out
  • 2 ADC5 End of Conversion
  • 3 PWM9H Out
  • 4 RTCC event
  • 5 ICAP8 event
  • 6 OCMP8 event
  • 7 TMR9 compare event
DS310:8Data Selection MUX 3 Signal Selection bits
  • 0 CLCINC I/O pin
  • 1 CLC3 out
  • 2 CMP5 out
  • 3 PWM8H Out
  • 4 ADC4 end of conversion
  • 5 ICAP7 event
  • 6 OCMP7 event
  • 7 TMR8 compare event
DS26:4Data Selection MUX 2 Signal Selection bits
  • 0 CLCIND I/O pin
  • 1 DMA Channel 0 Interrupt
  • 2 CMP4 out
  • 3 PWM7H Out
  • 4 ADC3 End of Conversion
  • 5 ICAP6 event
  • 6 OCMP6 Output
  • 7 TMR7 compare event
DS12:0Data Selection MUX 1 Signal Selection bits
  • 0 CLCINC I/O pin
  • 1 System Clock
  • 2 SOSC Clock
  • 3 LPRC Clock
  • 4 REFO2 Clock Output
  • 5 ICAP5 event
  • 6 OCMP5 Output
  • 7 TMR6 compare event

CLC4GLS

Address
0xBF82D820
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
FieldBitsWhat it does
G4D4N30Gate 4 Data Source 4 Negated Enable bit
  • 0 The Data Source 4 inverted signal is disabled for Gate 4
  • 1 The Data Source 4 inverted signal is enabled for Gate 4
G4D3T29Gate 4 Data Source 3 True Enable bit
  • 0 The Data Source 3 signal is disabled for Gate 4
  • 1 The Data Source 3 signal is enabled for Gate 4
G4D3N28Gate 4 Data Source 3 Negated Enable bit
  • 0 The Data Source 3 inverted signal is disabled for Gate 4
  • 1 The Data Source 3 inverted signal is enabled for Gate 4
G4D2T27Gate 4 Data Source 2 True Enable bit
  • 0 The Data Source 2 signal is disabled for Gate 4
  • 1 The Data Source 2 signal is enabled for Gate 4
G4D2N26Gate 4 Data Source 2 Negated Enable bit
  • 0 The Data Source 2 inverted signal is disabled for Gate 4
  • 1 The Data Source 2 inverted signal is enabled for Gate 4
G4D1T25Gate 4 Data Source 1 True Enable bit
  • 0 The Data Source 1 signal is disabled for Gate 4
  • 1 The Data Source 1 signal is enabled for Gate 4
G4D1N24Gate 4 Data Source 1 Negated Enable bit
  • 0 The Data Source 1 inverted signal is disabled for Gate 4
  • 1 The Data Source 1 inverted signal is enabled for Gate 4
G3D4T23Gate 3 Data Source 4 True Enable bit
  • 0 The Data Source 4 signal is disabled for Gate 3
  • 1 The Data Source 4 signal is enabled for Gate 3
G3D4N22Gate 3 Data Source 4 Negated Enable bit
  • 0 The Data Source 4 inverted signal is disabled for Gate 3
  • 1 The Data Source 4 inverted signal is enabled for Gate 3
G3D3T21Gate 3 Data Source 3 True Enable bit
  • 0 The Data Source 3 signal is disabled for Gate 3
  • 1 The Data Source 3 signal is enabled for Gate 3
G3D3N20Gate 3 Data Source 3 Negated Enable bit
  • 0 The Data Source 3 inverted signal is disabled for Gate 3
  • 1 The Data Source 3 inverted signal is enabled for Gate 3
G3D2T19Gate 3 Data Source 2 True Enable bit
  • 0 The Data Source 2 signal is disabled for Gate 3
  • 1 The Data Source 2 signal is enabled for Gate 3
G3D2N18Gate 3 Data Source 2 Negated Enable bit
  • 0 The Data Source 2 inverted signal is disabled for Gate 3
  • 1 The Data Source 2 inverted signal is enabled for Gate 3
G3D1T17Gate 3 Data Source 1 True Enable bit
  • 0 The Data Source 1 signal is disabled for Gate 3
  • 1 The Data Source 1 signal is enabled for Gate 3
G3D1N16Gate 3 Data Source 1 Negated Enable bit
  • 0 The Data Source 1 inverted signal is disabled for Gate 3
  • 1 The Data Source 1 inverted signal is enabled for Gate 3
G2D4T15Gate 2 Data Source 4 True Enable bit
  • 0 The Data Source 4 signal is disabled for Gate 2
  • 1 The Data Source 4 signal is enabled for Gate 2
G2D4N14Gate 2 Data Source 4 Negated Enable bit
  • 0 The Data Source 4 inverted signal is disabled for Gate 2
  • 1 The Data Source 4 inverted signal is enabled for Gate 2
G2D3T13Gate 2 Data Source 3 True Enable bit
  • 0 The Data Source 3 signal is disabled for Gate 2
  • 1 The Data Source 3 signal is enabled for Gate 2
G2D3N12Gate 2 Data Source 3 Negated Enable bit
  • 0 The Data Source 3 inverted signal is disabled for Gate 2
  • 1 The Data Source 3 inverted signal is enabled for Gate 2
G2D2T11Gate 2 Data Source 2 True Enable bit
  • 0 The Data Source 2 signal is disabled for Gate 2
  • 1 The Data Source 2 signal is enabled for Gate 2
G2D2N10Gate 2 Data Source 2 Negated Enable bit
  • 0 The Data Source 2 inverted signal is disabled for Gate 2
  • 1 The Data Source 2 inverted signal is enabled for Gate 2
G2D1T9Gate 2 Data Source 1 True Enable bit
  • 0 The Data Source 1 signal is disabled for Gate 2
  • 1 The Data Source 1 signal is enabled for Gate 2
G2D1N8Gate 2 Data Source 1 Negated Enable bit
  • 0 The Data Source 1 inverted signal is disabled for Gate 2
  • 1 The Data Source 1 inverted signal is enabled for Gate 2
G1D4T7Gate 1 Data Source 4 True Enable bit
  • 0 The Data Source 4 signal is disabled for Gate 1
  • 1 The Data Source 4 signal is enabled for Gate 1
G1D4N6Gate 1 Data Source 4 Negated Enable bit
  • 0 The Data Source 4 inverted signal is disabled for Gate 1
  • 1 The Data Source 4 inverted signal is enabled for Gate 1
G1D3T5Gate 1 Data Source 3 True Enable bit
  • 0 The Data Source 3 signal is disabled for Gate 1
  • 1 The Data Source 3 signal is enabled for Gate 1
G1D3N4Gate 1 Data Source 3 Negated Enable bit
  • 0 The Data Source 3 inverted signal is disabled for Gate 1
  • 1 The Data Source 3 inverted signal is enabled for Gate 1
G1D2T3Gate 1 Data Source 2 True Enable bit
  • 0 The Data Source 2 signal is disabled for Gate 1
  • 1 The Data Source 2 signal is enabled for Gate 1
G1D2N2Gate 1 Data Source 2 Negated Enable bit
  • 0 The Data Source 2 inverted signal is disabled for Gate 1
  • 1 The Data Source 2 inverted signal is enabled for Gate 1
G1D1T1Gate 1 Data Source 1 True Enable bit
  • 0 The Data Source 1 signal is disabled for Gate 1
  • 1 The Data Source 1 signal is enabled for Gate 1
G1D1N0Gate 1 Data Source 1 Negated Enable bit
  • 0 The Data Source 1 inverted signal is disabled for Gate 1
  • 1 The Data Source 1 inverted signal is enabled for Gate 1
G4D4T31Gate 4 Data Source 4 True Enable bit
  • 0 The Data Source 4 signal is disabled for Gate 4
  • 1 The Data Source 4 signal is enabled for Gate 4