The 7 registers of I2C1 (I²C 1), from 0xBF826000, with their reset value and every field. The PIC32MK0256MCJ048 has 1276 registers in 85 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
I2C1 I²C 1
I2C1CONI2C Control Register
Address
0xBF826000
Reset
0x00000000
Access
read/write
Size
32-bit
22 fields
Field
Bits
What it does
PCIE
22
Stop Condition Interrupt Enable bit
0 Stop detection interrupts are disabled
1 Enable interrupt on detection of Stop condition
SCIE
21
Start Condition Interrupt Enable bit
0 Start detection interrupts are disabled
1 Enable interrupt on detection of Start or Restart conditions
BOEN
20
Buffer Overwrite Enable bit
0 I2CxRCV is only updated when the I2COV bit (I2CxSTAT) is clear
1 I2CxRCV is updated and
SDAHT
19
SDA Hold Time Selection bit
0 Minimum of 100 ns hold time on SDA after the falling edge of SCL
1 Minimum of 300 ns hold time on SDA after the falling edge of SCL
SBCDE
18
Slave Mode Bus Collision Detect Enable bit
0 Slave bus collision interrupts are disabled
1 Enable slave bus collision interrupts
AHEN
17
Address Hold Enable bit
0 Address holding is disabled
1 Following the 8th falling edge of SCL for a matching received address byte; SCKREL bit will be cleared and the SCL will be held low.
DHEN
16
Data Hold Enable bit
0 Data holding is disabled
1 Following the 8th falling edge of SCL for a received data byte; slave hardware clears the SCKREL bit and SCL is held low
ON
15
I2C Enable bit
0 Disables the I2C module; all I2C pins are controlled by PORT functions
1 Enables the I2C module and configures the SDA and SCL pins as serial port pins
SIDL
13
Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
SCLREL
12
SCLx Release Control bit
0 Hold SCLx clock low (clock stretch)
1 Release SCLx clock
STRICT
11
Strict I 2 C Reserved Address Rule Enable bit
0 Strict I2C Reserved Address Rule is not enabled
1 Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space.
A10M
10
DISSLW
9
Disable Slew Rate Control bit
0 Slew rate control is enabled
1 Slew rate control is disabled
SMEN
8
SMBus Input Levels bit
0 Disable SMBus input thresholds
1 Enable I/O pin thresholds compliant with SMBus specification
GCEN
7
General Call Enable bit
0 General call address is disabled
1 Enable interrupt when a general call address is received in the I2CxRSR(module is enabled for reception)
STREN
6
SCLx Clock Stretch Enable bit
0 Disable software or receive clock stretching
1 Enable software or receive clock stretching
ACKDT
5
Acknowledge Data bit
0 Send ACK during Acknowledge
1 Send NACK during Acknowledge
ACKEN
4
Acknowledge Sequence Enable bit
0 Acknowledge sequence not in progress
1 Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence.
RCEN
3
Receive Enable bit
0 Receive sequence not in progress
1 Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
PEN
2
Stop Condition Enable bit
0 Stop condition not in progress
1 Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
RSEN
1
Repeated Start Condition Enable bit
0 Repeated Start condition not in progress
1 Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence.
SEN
0
Start Condition Enable bit
0 Start condition not in progress
1 Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
I2C1STATI2C Status Register
Address
0xBF826010
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
ACKSTAT
15
Acknowledge Status bit
0 ACK received from slave
1 NACK received from slave
TRSTAT
14
Transmit Status bit
0 Master transmit is not in progress
1 Master transmit is in progress (8 bits + ACK)
ACKTIM
13
Acknowledge Time Status bit
0 Not an Acknowledge sequence
1 I2C bus is in an Acknowledge sequence
BCL
10
Master Bus Collision Detect bit
0 No collision
1 A bus collision has been detected during a master operation
GCSTAT
9
General Call Status bit
0 General call address was not received
1 General call address was received
ADD10
8
10-bit Address Status bit
0 10-bit address was not matched
1 10-bit address was matched
IWCOL
7
Write Collision Detect bit
0 No collision
1 An attempt to write the I2CxTRN register failed because the I2C module is busy
I2COV
6
Receive Overflow Flag bit
0 No overflow
1 A byte was received while the I2CxRCV register is still holding the previous byte
D_A
5
Data/Address bit
0 Indicates that the last byte received was device address
1 Indicates that the last byte received was data
P
4
Stop bit
0 Stop bit was not detected last
1 Indicates that a Stop bit has been detected last
S
3
Start bit
0 Start bit was not detected last
1 Indicates that a Start (or Repeated Start) bit has been detected last
R_W
2
Read/Write Information bit
0 Write indicates data transfer is input to slave
1 Read indicates data transfer is output from slave
BETA