PIC32MK0256MCJ064 CAN registers

The 186 registers of CAN (CAN), from 0xBF880000, with their reset value and every field. The PIC32MK0256MCJ064 has 1361 registers in 88 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CAN CAN

CFD1CONCAN Control Register

Address: 0xBF880000
Reset: 0x00000000
Access: read/write
Size: 32-bit

19 fields

Field	Bits	What it does
ABAT	27	Abort All Pending Transmissions bit `0` Module will clear this bit when all transmissions aborted `1` Signal all transmit buffers to abort transmission
REQOP	26:24	Request Operation Mode bits `0` Set Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames `1` Set Disable mode `2` Set Internal Loopback mode `3` Set Listen Only mode `4` Set Configuration mode `5` Set External Loopback mode `6` Set Normal CAN 2.0 mode; error frames on CAN FD frames `7` Set Restricted Operation mode
OPMOD	23:21	Operation Mode Status bits `0` Module is in Normal CAN FD mode; supports mixing of Full CAN FD and Classic CAN 2.0 frames `1` Module is in Disable mode `2` Module is in Internal Loopback mode `3` Module is in Listen Only mode `4` Module is in Configuration mode `5` Module is in External Loopback mode `6` Module is Normal CAN 2.0 mode; error frames on CAN FD frames `7` Module is Restricted Operation mode
TXQEN	20	Enable Transmit Queue bit `0` Dont reserve space in RAM for Transmit Queue `1` Enables Transmit Queue and reserves space in RAM
STEF	19	Store in Transmit Event FIFO bit `0` Dont save transmitted messages in TEF `1` Save transmitted messages in TEF
SERR2LOM	18	Transition to Listen Only Mode on System Error bit `0` Transition to Restricted Operation Mode `1` Transition to Listen Only Mode
ESIGM	17	Transmit ESI in Gateway Mode bit `0` ESI reflects error status of CAN controller `1` ESI is transmitted as recessive when ESI of message is high or CAN controller error passive
RTXAT	16	Restrict Retransmission Attempts bit `0` Unlimited number of retransmission attempts `1` Restricted retransmission attempts
ON	15	Enable bit `0` CAN module is disabled `1` CAN module is enabled
SIDL	13	Stop-in-Idle Control bit `0` Dont stop module operation in Idle mode `1` Stop module operation in Idle mode
BRSDIS	12	Bit Rate Switching Disable bit `0` Bit Rate Switching depends on BRS in the Transmit Message Object `1` Bit Rate Switching is Disabled
BUSY	11	CAN Module is Busy bit `0` The CAN module is inactive `1` The CAN module is active
WFT	10:9	Selectable Wake-up Filter Time bits `0` T00FILTER (Typical 100 ns) `1` T01FILTER (Typical 187 ns) `2` T10FILTER (Typical 375 ns) `3` T11FILTER (Typical 600 ns)
WAKFIL	8	Enable CAN Bus Line Wake-up Filter bit `0` CAN bus line filter is not used for wake-up `1` Use CAN bus line filter for wake-up
CLKSEL0	7	Module Clock Source Select bit `0` SYSCLK is active when the CAN FD module is enabled `1` REFCLK4 is active when the CAN FD module is enabled
PXEDIS	6	Protocol Exception Event Detection Disabled bit `0` If a Protocol Exception is detected `1` Protocol Exception is treated as a Form Error.
ISOCRCEN	5	Enable ISO CRC in CAN FD Frames bit `0` Do not include Stuff Bit Count in CRC Field and use CRC Initialization Vector with all zeros `1` Include Stuff Bit Count in CRC Field and use Non-Zero CRC Initialization Vector
DNCNT	4:0	Device Net Filter Bit Number bits
TXBWS	31:28	Transmit Bandwidth Sharing bits `0` No delay `1` 2 `2` 4 `3` 8 `4` 16 `5` 32 `6` 64 `7` 128 `8` 256 `9` 512 `10` 1024 `11` 2048 `12` 4096

CFD1NBTCFGNominal Bit Time Configuration Register

Address: 0xBF880010
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TSEG1	23:16	Time Segment 1 bits `0` Length is 1 x Tq `255` Length is 256 x Tq
TSEG2	14:8	Time Segment 2 bits `0` Length is 1 x Tq `31` Length is 128 x Tq
SJW	6:0	Synchronization Jump Width bits `0` Length is 1 x Tq `127` Length is 128 x Tq
BRP	31:24	Baud Rate Prescaler bits `0` Tq = 1/Fsys `255` Tq = 256/Fsys

CFD1DBTCFGData Bit Time Configuration Register

Address: 0xBF880020
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TSEG1	20:16	Time Segment 1 bits `0` Length is 1 x Tq `1` Length is 2 x Tq `2` Length is 3 x Tq `3` Length is 4 x Tq `4` Length is 5 x Tq `5` Length is 6 x Tq `6` Length is 7 x Tq `7` Length is 8 x Tq `8` Length is 9 x Tq `9` Length is 10 x Tq `10` Length is 11 x Tq `11` Length is 12 x Tq `12` Length is 13 x Tq `13` Length is 14 x Tq `14` Length is 15 x Tq `15` Length is 16 x Tq `16` Length is 17 x Tq `17` Length is 18 x Tq `18` Length is 19 x Tq `19` Length is 20 x Tq `20` Length is 21 x Tq `21` Length is 22 x Tq `22` Length is 23 x Tq `23` Length is 24 x Tq `24` Length is 25 x Tq `25` Length is 26 x Tq `26` Length is 27 x Tq `27` Length is 28 x Tq `28` Length is 29 x Tq `29` Length is 30 x Tq `30` Length is 31 x Tq `31` Length is 32 x Tq
TSEG2	11:8	Time Segment 2 bits `0` Length is 1 x Tq `1` Length is 2 x Tq `2` Length is 3 x Tq `3` Length is 4 x Tq `4` Length is 5 x Tq `5` Length is 6 x Tq `6` Length is 7 x Tq `7` Length is 8 x Tq `8` Length is 9 x Tq `9` Length is 10 x Tq `10` Length is 11 x Tq `11` Length is 12 x Tq `12` Length is 13 x Tq `13` Length is 14 x Tq `14` Length is 15 x Tq `15` Length is 16 x Tq
SJW	3:0	Synchronization Jump Width bits `0` Length is 1 x Tq `1` Length is 2 x Tq `2` Length is 3 x Tq `3` Length is 4 x Tq `4` Length is 5 x Tq `5` Length is 6 x Tq `6` Length is 7 x Tq `7` Length is 8 x Tq `8` Length is 9 x Tq `9` Length is 10 x Tq `10` Length is 11 x Tq `11` Length is 12 x Tq `12` Length is 13 x Tq `13` Length is 14 x Tq `14` Length is 15 x Tq `15` Length is 16 x Tq
BRP	31:24	Baud Rate Prescaler bits `0` Tq is 1/Fsys `255` Tq is 256/Fsys

CFD1TDCTransmitter Delay Compensation Register

Address: 0xBF880030
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
EDGFLTEN	25	Enable Edge Filtering during Bus Integration state bit `0` Edge Filtering disabled `1` Edge Filtering enabled
SID11EN	24	Enable 12-Bit SID in CAN FD Base Format Messages bit `0` Do not use RRS; SID(10-0) according to ISO11898-1 2015 `1` RRS is used as SID11 in CAN FD base format messages: SID(11-0) = {SID(10-0)
TDCMOD	17:16	Transmitter Delay Compensation Mode bits `0` Disable `1` Manual; Do not measure use TDCV plus TDCO from the register `2` Auto; measure delay and add CFDxDBTCFG.TSEG1; add TDCO
TDCO	14:8	Transmitter Delay Compensation Offset bits `0` 0 x SYSCLK `1` 1 x SYSCLK `2` 2 x SYSCLK `3` 3 x SYSCLK `4` 4 x SYSCLK `5` 5 x SYSCLK `6` 6 x SYSCLK `7` 7 x SYSCLK `8` 8 x SYSCLK `9` 9 x SYSCLK `10` 10 x SYSCLK `11` 11 x SYSCLK `12` 12 x SYSCLK `13` 13 x SYSCLK `14` 14 x SYSCLK `15` 15 x SYSCLK `16` 16 x SYSCLK `17` 17 x SYSCLK `18` 18 x SYSCLK `19` 19 x SYSCLK `20` 20 x SYSCLK `21` 21 x SYSCLK `22` 22 x SYSCLK `23` 23 x SYSCLK `24` 24 x SYSCLK `25` 25 x SYSCLK `26` 26 x SYSCLK `27` 27 x SYSCLK `28` 28 x SYSCLK `29` 29 x SYSCLK `30` 30 x SYSCLK `31` 31 x SYSCLK `32` 32 x SYSCLK `33` 33 x SYSCLK `34` 34 x SYSCLK `35` 35 x SYSCLK `36` 36 x SYSCLK `37` 37 x SYSCLK `38` 38 x SYSCLK `39` 39 x SYSCLK `40` 40 x SYSCLK `41` 41 x SYSCLK `42` 42 x SYSCLK `43` 43 x SYSCLK `44` 44 x SYSCLK `45` 45 x SYSCLK `46` 46 x SYSCLK `47` 47 x SYSCLK `48` 48 x SYSCLK `49` 49 x SYSCLK `50` 50 x SYSCLK `51` 51 x SYSCLK `52` 52 x SYSCLK `53` 53 x SYSCLK `54` 54 x SYSCLK `55` 55 x SYSCLK `56` 56 x SYSCLK `57` 57 x SYSCLK `58` 58 x SYSCLK `59` 59 x SYSCLK `60` 60 x SYSCLK `61` 61 x SYSCLK `62` 62 x SYSCLK `63` 63 x SYSCLK
TDCV	5:0	Transmitter Delay Compensation Value bits; Secondary Sample Point `0` 0 x SYSCLK `1` 1 x SYSCLK `2` 2 x SYSCLK `3` 3 x SYSCLK `4` 4 x SYSCLK `5` 5 x SYSCLK `6` 6 x SYSCLK `7` 7 x SYSCLK `8` 8 x SYSCLK `9` 9 x SYSCLK `10` 10 x SYSCLK `11` 11 x SYSCLK `12` 12 x SYSCLK `13` 13 x SYSCLK `14` 14 x SYSCLK `15` 15 x SYSCLK `16` 16 x SYSCLK `17` 17 x SYSCLK `18` 18 x SYSCLK `19` 19 x SYSCLK `20` 20 x SYSCLK `21` 21 x SYSCLK `22` 22 x SYSCLK `23` 23 x SYSCLK `24` 24 x SYSCLK `25` 25 x SYSCLK `26` 26 x SYSCLK `27` 27 x SYSCLK `28` 28 x SYSCLK `29` 29 x SYSCLK `30` 30 x SYSCLK `31` 31 x SYSCLK `32` 32 x SYSCLK `33` 33 x SYSCLK `34` 34 x SYSCLK `35` 35 x SYSCLK `36` 36 x SYSCLK `37` 37 x SYSCLK `38` 38 x SYSCLK `39` 39 x SYSCLK `40` 40 x SYSCLK `41` 41 x SYSCLK `42` 42 x SYSCLK `43` 43 x SYSCLK `44` 44 x SYSCLK `45` 45 x SYSCLK `46` 46 x SYSCLK `47` 47 x SYSCLK `48` 48 x SYSCLK `49` 49 x SYSCLK `50` 50 x SYSCLK `51` 51 x SYSCLK `52` 52 x SYSCLK `53` 53 x SYSCLK `54` 54 x SYSCLK `55` 55 x SYSCLK `56` 56 x SYSCLK `57` 57 x SYSCLK `58` 58 x SYSCLK `59` 59 x SYSCLK `60` 60 x SYSCLK `61` 61 x SYSCLK `62` 62 x SYSCLK `63` 63 x SYSCLK

CFD1TBCCAN Time Base Counter Register

Address: 0xBF880040
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TBC	31:0	CAN Base Counter bits

CFD1TSCONCAN Time Stamp Control Register

Address: 0xBF880050
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TSRES	18	Time Stamp Resolution bit `0` At sample point of SOF `1` At sample point of the bit following the FDF bit
TSEOF	17	Time Stamp EOF bit `0` Time Stamp at beginning of Frame (classical frame) at sample point of SOF / FD frame: see the TSRES bit `1` Time Stamp when frame is taken valid (11898-1 10.7)
TBCEN	16	Time Base Counter Enable bit `0` Stop and reset TBC `1` Enable TBC
TBCPRE	9:0	CAN Time Base Counter Prescaler bits `0` TBC increments every 1 SYSCLK clock cycle `511` TBC increments every 1024 SYSCLK clock cycles

CFD1VECInterrupt Code Register

Address: 0xBF880060
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
RXCODE	30:24	Receive Interrupt Flag Code bits `0` Reserved. FIFO 0 cant receive. `1` FIFO 1 Interrupt `2` FIFO 2 Interrupt `3` FIFO 3 Interrupt `4` FIFO 4 Interrupt `5` FIFO 5 Interrupt `6` FIFO 6 Interrupt `7` FIFO 7 Interrupt `8` FIFO 8 Interrupt `9` FIFO 9 Interrupt `10` FIFO 10 Interrupt `11` FIFO 11 Interrupt `12` FIFO 12 Interrupt `13` FIFO 13 Interrupt `14` FIFO 14 Interrupt `15` FIFO 15 Interrupt `16` FIFO 16 Interrupt `17` FIFO 17 Interrupt `18` FIFO 18 Interrupt `19` FIFO 19 Interrupt `20` FIFO 20 Interrupt `21` FIFO 21 Interrupt `22` FIFO 22 Interrupt `23` FIFO 23 Interrupt `24` FIFO 24 Interrupt `25` FIFO 25 Interrupt `26` FIFO 26 Interrupt `27` FIFO 27 Interrupt `28` FIFO 28 Interrupt `29` FIFO 29 Interrupt `30` FIFO 30 Interrupt `31` FIFO 31 Interrupt `64` No interrupt
TXCODE	22:16	Transmit Interrupt Flag Code bits `0` FIFO 0 Interrupt `1` FIFO 1 Interrupt `2` FIFO 2 Interrupt `3` FIFO 3 Interrupt `4` FIFO 4 Interrupt `5` FIFO 5 Interrupt `6` FIFO 6 Interrupt `7` FIFO 7 Interrupt `8` FIFO 8 Interrupt `9` FIFO 9 Interrupt `10` FIFO 10 Interrupt `11` FIFO 11 Interrupt `12` FIFO 12 Interrupt `13` FIFO 13 Interrupt `14` FIFO 14 Interrupt `15` FIFO 15 Interrupt `16` FIFO 16 Interrupt `17` FIFO 17 Interrupt `18` FIFO 18 Interrupt `19` FIFO 19 Interrupt `20` FIFO 20 Interrupt `21` FIFO 21 Interrupt `22` FIFO 22 Interrupt `23` FIFO 23 Interrupt `24` FIFO 24 Interrupt `25` FIFO 25 Interrupt `26` FIFO 26 Interrupt `27` FIFO 27 Interrupt `28` FIFO 28 Interrupt `29` FIFO 29 Interrupt `30` FIFO 30 Interrupt `31` FIFO 31 Interrupt `64` No interrupt
FILHIT	12:8	Filter Hit Number bits `0` Filter 0 `1` Filter 1 `2` Filter 2 `3` Filter 3 `4` Filter 4 `5` Filter 5 `6` Filter 6 `7` Filter 7 `8` Filter 8 `9` Filter 9 `10` Filter 10 `11` Filter 11 `12` Filter 12 `13` Filter 13 `14` Filter 14 `15` Filter 15 `16` Filter 16 `17` Filter 17 `18` Filter 18 `19` Filter 19 `20` Filter 20 `21` Filter 21 `22` Filter 22 `23` Filter 23 `24` Filter 24 `25` Filter 25 `26` Filter 26 `27` Filter 27 `28` Filter 28 `29` Filter 29 `30` Filter 30 `31` Filter 31
ICODE	6:0	Interrupt Flag Code bits `0` FIFO 0 interrupt (TFIF0 set) `1` FIFO 1 interrupt (TFIF1 or RFIF1 set) `2` FIFO 2 interrupt (TFIF2 or RFIF2 set) `3` FIFO 3 interrupt (TFIF3 or RFIF3 set) `4` FIFO 4 interrupt (TFIF4 or RFIF4 set) `5` FIFO 5 interrupt (TFIF5 or RFIF5 set) `6` FIFO 6 interrupt (TFIF6 or RFIF6 set) `7` FIFO 7 interrupt (TFIF7 or RFIF7 set) `8` FIFO 8 interrupt (TFIF8 or RFIF8 set) `9` FIFO 9 interrupt (TFIF9 or RFIF9 set) `10` FIFO 10 interrupt (TFIF10 or RFIF10 set) `11` FIFO 11 interrupt (TFIF11 or RFIF11 set) `12` FIFO 12 interrupt (TFIF12 or RFIF12 set) `13` FIFO 13 interrupt (TFIF13 or RFIF13 set) `14` FIFO 14 interrupt (TFIF14 or RFIF14 set) `15` FIFO 15 interrupt (TFIF15 or RFIF15 set) `16` FIFO 16 interrupt (TFIF16 or RFIF16 set) `17` FIFO 17 interrupt (TFIF17 or RFIF17 set) `18` FIFO 18 interrupt (TFIF18 or RFIF18 set) `19` FIFO 19 interrupt (TFIF19 or RFIF19 set) `20` FIFO 20 interrupt (TFIF20 or RFIF20 set) `21` FIFO 21 interrupt (TFIF21 or RFIF21 set) `22` FIFO 22 interrupt (TFIF22 or RFIF22 set) `23` FIFO 23 interrupt (TFIF23 or RFIF23 set) `24` FIFO 24 interrupt (TFIF24 or RFIF24 set) `25` FIFO 25 interrupt (TFIF25 or RFIF25 set) `26` FIFO 26 interrupt (TFIF26 or RFIF26 set) `27` FIFO 27 interrupt (TFIF27 or RFIF27 set) `28` FIFO 28 interrupt (TFIF28 or RFIF28 set) `29` FIFO 29 interrupt (TFIF29 or RFIF29 set) `30` FIFO 30 interrupt (TFIF30 or RFIF30 set) `31` FIFO 31 interrupt (TFIF31 or RFIF31 set) `64` No interrupt `65` Error interrupt (CERRIF/IE) `66` Wake-up interrupt (WAKIF/WAKIE) `67` Receive FIFO overflow interrupt (any bit in CFDxRXOVIF set) `68` Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE) `69` RX/TX MAB overflow/underflow (RX: message received before previous message was saved to memory; TX: cannot feed TX MAB fast enough to transmit consistent data.) (SERRIF/IE) `70` CAN Timer Overflow (CTMRIF/IE) `71` CAN module mode change Occurred (MODIF/IE) `72` Invalid message occurred (IVMIF/IE) `73` Transmit event FIFO interrupt (any bit in the CFDxTEFIF register is set) `74` Transmit attempt interrupt (any bit in the CFDxTXATIF register is set)

CFD1INTInterrupt Register

Address: 0xBF880070
Reset: 0x00000000
Access: read/write
Size: 32-bit

22 fields

Field	Bits	What it does
WAKIE	30	Bus Wake Up Activity Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
CERRIE	29	CAN Bus Error Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
SERRIE	28	System Error Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
RXOVIE	27	Receive Buffer Overflow Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
TXATIE	26	Transmit Attempt Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
TEFIE	20	Transmit Event FIFO Interrupt Enable bit `1` Interrupts are enabled
MODIE	19	Mode Change Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
TBCIE	18	CAN Timer Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
RXIE	17	Receive Object Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
TXIE	16	Transmit Object Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled
IVMIF	15	Invalid Message Interrupt Flag bit `0` No invalid message interrupts are pending `1` An invalid message interrupt is pending
WAKIF	14	Bus Wake Up Activity Interrupt Flag bit `0` No wake-up interrupts are pending `1` A wake-up interrupt is pending
CERRIF	13	CAN Bus Error Interrupt Flag bit `0` No CAN bus error interrupts are pending `1` A CAN bus error interrupt is pending
SERRIF	12	System Error Interrupt Flag bit `0` No system error occurred `1` A system error occurred (collision on dual-port RAM)
RXOVIF	11	Receive Object Overflow Interrupt Flag bit `0` No receive object overflow has occurred `1` Receive object overflow occurred
TXATIF	10	Transmit Attempt Interrupt Flag bit `0` No transmit FIFO interrupts are pending `1` A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set
TEFIF	4	Transmit Event FIFO Interrupt Flag bit `0` No receive buffer overflow has occurred `1` Receive buffer overflow occurred
MODIF	3	CAN Mode Change Interrupt Flag bit `0` No mode change occurred `1` CAN module mode change occurred (OPMOD has changed to reflect the REQOP bits)
TBCIF	2	CAN Timer Overflow Interrupt Flag bit `0` TBC did not overflow `1` TBC has overflowed
RXIF	1	Receive Object Interrupt Flag bit `0` No receive object interrupts pending `1` Receive object interrupt pending
TXIF	0	Transmit Object Interrupt Flag bit `0` No transmit object interrupts pending `1` Transmit object interrupt pending
IVMIE	31	Invalid Message Interrupt Enable bit `0` Interrupts are disabled `1` Interrupts are enabled

CFD1RXIFReceive Interrupt Status Register

Address: 0xBF880080
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RFIF	31:1	Receive FIFO Interrupt Pending bits `0` No enabled receive FIFO interrupts are pending `1` One or more enabled receive FIFO interrupts are pending

CFD1TXIFTransmit Interrupt Status Register

Address: 0xBF880090
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TFIF	31:0	Transmit FIFO/Transmit Queue Interrupt Pending bits `0` No enabled transmit FIFO/Transmit Queue interrupt are pending `1` One or more enabled transmit FIFO/Transmit Queue interrupts are pending

CFD1RXOVIFReceive Overflow Interrupt Status Register

Address: 0xBF8800A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
RFOVIF	31:1	Receive FIFO Overflow Interrupt Pending bits `0` Interrupt not pending `1` Interrupt is pending

CFD1TXATIFTransmit Attempt Interrupt Status Register

Address: 0xBF8800B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TFATIF	31:0	Transmit FIFO/Transmit Queue Attempt Interrupt Pending bits `0` No transmit FIFO interrupts are pending `1` A transmit interrupt is pending in one or more of the designated 32 FIFOs denoted by which of the 32 bits in the CFDxTXATIF register are set

CFD1TXREQTransmit Request Register

Address: 0xBF8800C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TXREQ	31:0	Message Send Request bits

CFD1TRECTransmit/Receive Error Count Register

Address: 0xBF8800D0
Reset: 0x00000000
Access: read only
Size: 32-bit

8 fields

Field	Bits	What it does
TXBO	21	Transmitter in Error State Bus Off bit (TERRCNT greater than 255) `0` Indicates that transmit errors are less than 255 `1` Indicates that the number of transmit errors is greater than 255.
TXBP	20	Transmitter in Error State Bus Passive bit (TERRCNT greater than 127) `0` Indicates that transmit errors are less than or equal to 127 `1` Indicates that the number of transmit errors is greater than 127.
RXBP	19	Receiver in Error State Bus Passive bit (RERRCNT greater than 127) `0` Indicates that transmit errors are less than or equal to 127 `1` Indicates that the number of receive errors is greater than 127.
TXWARN	18	Transmitter in Error State Warning bit (128 greater than TERRCNT greater than 95) `0` Indicates that transmit errors are greater than or equal to 95 `1` Indicates that the number of transmit errors are less than 128
RXWARN	17	Receiver in Error State Warning bit (128 greater than RERRCNT greater than 95) `0` Indicates that receive errors are greater than or equal to 95 `1` Indicates that the number of receives errors is less than 128
EWARN	16	Transmitter or Receiver is in Error State Warning bit `0` No transmit or receive warnings `1` TXWARN or RXWARN is set
TERRCNT	15:8	Transmit Error Counter bits `0` No transmit errors `1` 1 transmit error `254` 254 Transmit errors `255` Greater than or equal to 255 Transmit errors.
RERRCNT	7:0	Receive Error Counter bits `0` No receive errors `1` 1 receive error `254` 254 receive errors `255` Greater than or equal to 255 Receive errors

CFD1BDIAG0Bus Diagnostics Register 0

Address: 0xBF8800E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
DRERRCNT	23:16	Data Bit Rate Receive Error Counter bits
NTERRCNT	15:8	Nominal Bit Rate Transmit Error Counter bits
NRERRCNT	7:0	Nominal Bit Rate Receive Error Counter bits
DTERRCNT	31:24	Data Bit Rate Transmit Error Counter bits

CFD1BDIAG1Bus Diagnostics Register

Address: 0xBF8800F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

14 fields

Field	Bits	What it does
ESI	30	Error State Indicator (ESI) Flag Status bit `0` ESI flag of a received CAN FD message was not set `1` ESI flag of a received CAN FD message was set
DCRCERR	29	Data CRC Error Status bit `0` No received message data CRC error occurred `1` CRC checksum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data
DSTUFERR	28	Data Stuffing Error Status bit `0` No data received message errors `1` More than five equal bits in a sequence have occurred in a portion of a received message where this is not allowed
DFORMERR	27	Data Format Error Status bit `0` No format errors occurred `1` Data fixed format portion of a received frame has the wrong format
DBIT1ERR	25	Data Bit Logical 1 Error Status bit `0` No data logical 1 bit transmission error occurred `1` During the data transmission of a message (with the exception of the arbitration field)
DBIT0ERR	24	Data Bit Logical 0 Error Status bit `0` No data logical 0 bit transmission error occurred `1` During the data transmission of a message the monitored bus value was recessive. During Bus Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored.
NCRCERR	21	Nominal CRC Error Status bit `0` No nominal CRC received message error occurred `1` The CRC checksum of a nominal received message was incorrect.
NSTUFERR	20	Nominal Stuffing Error Status bit `0` No nominal bit stuffing errors have occurred `1` More than five equal bits in a sequence have occurred in a part of a nominal received message where this is not allowed
NFORMERR	19	Nominal Format Error Status bit `0` No nominal format error occurred `1` A fixed format portion of a nominal received frame has the wrong format
NACKERR	18	Not Acknowledged Error Status bit `0` A transmitted message was acknowledged `1` A transmitted message was not acknowledged
NBIT1ERR	17	Nominal Bit Logical 1 Error Status bit `0` No nominal bit logical 1 error occurred `1` During the transmission of a nominal message (with the exception of the arbitration field)
NBIT0ERR	16	Nominal Bit Logical 0 Error Status bit `0` No nominal bit logical 0 error occurred `1` During the transmission of a nominal message
EFMSGCNT	15:0	Error Free Message Counter Status bits `0` 0 error free messages since the last register read `65535` 65536 error free messages since the last register read
DLCMM	31	Data Length Code (DLC) Mismatch Status bit `0` No payload size error occurred `1` Payload size error. During a transmission or reception the Data Length Code exceeds the payload size of the FIFO element defined in the PLSIZE bits (CFDxFIFOCONn).

CFD1TEFCONTransmit Event FIFO Control Register

Address: 0xBF880100
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 message deep `1` FIFO is 2 messages deep `2` FIFO is 3 messages deep `3` FIFO is 4 messages deep `4` FIFO is 5 messages deep `5` FIFO is 6 messages deep `6` FIFO is 7 messages deep `7` FIFO is 8 messages deep `8` FIFO is 9 messages deep `9` FIFO is 10 messages deep `10` FIFO is 11 messages deep `11` FIFO is 12 messages deep `12` FIFO is 13 messages deep `13` FIFO is 14 messages deep `14` FIFO is 15 messages deep `15` FIFO is 16 messages deep `16` FIFO is 17 messages deep `17` FIFO is 18 messages deep `18` FIFO is 19 messages deep `19` FIFO is 20 messages deep `20` FIFO is 21 messages deep `21` FIFO is 22 messages deep `22` FIFO is 23 messages deep `23` FIFO is 24 messages deep `24` FIFO is 25 messages deep `25` FIFO is 26 messages deep `26` FIFO is 27 messages deep `27` FIFO is 28 messages deep `28` FIFO is 29 messages deep `29` FIFO is 30 messages deep `30` FIFO is 31 messages deep `31` FIFO is 32 messages deep
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set
UINC	8	Increment Tail bit
TEFTSEN	5	Transmit Event FIFO Time Stamp Enable bit `0` Do not time stamp elements in TEF `1` Time stamp elements in TEF
TEFOVIE	3	Transmit Event FIFO Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TEFFIE	2	Transmit Event FIFO Full Interrupt Enable bit `0` Interrupt disabled for FIFO full `1` Interrupt enabled for FIFO full
TEFHIE	1	Transmit Event FIFO Half Full Interrupt Enable bit `0` Interrupt disabled for FIFO half full `1` Interrupt enabled for FIFO half full
TEFNEIE	0	Transmit Event FIFO Not Empty Interrupt Enable bit `0` Interrupt disabled for FIFO not empty `1` Interrupt enabled for FIFO not empty

CFD1TEFSTATransmit Event FIFO Status Register

Address: 0xBF880110
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
TEFOVIF	3	Transmit Event FIFO Overflow Interrupt Flag bit `0` No overflow event has occurred `1` Overflow event has occurred
TEFFIF	2	Transmit Event FIFO Full Interrupt Flag bit `0` FIFO is not full `1` FIFO is full
TEFHIF	1	Transmit Event FIFO Half Full Interrupt Flag bit `0` FIFO is less than half full `1` FIFO is greater than or equal to half full
TEFNEIF	0	Transmit Event FIFO Not Empty Interrupt Flag bit `0` FIFO is empty `1` FIFO is not empty (has at least one message)

CFD1TEFUATransmit Event FIFO User Address Register

Address: 0xBF880120
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TEFUA	31:0	Transmit Event FIFO User Address bits

CFD1FIFOBAMessage Memory Base Address Register

Address: 0xBF880130
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOBA	31:0	Message Memory Base Address bits

CFD1TXQCONTransmit Queue Control Register

Address: 0xBF880140
Reset: 0x00000000
Access: read/write
Size: 32-bit

11 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. The user application should poll whether this bit is clear before taking any action.
TXREQ	9	Message Send Request bit `0` Clearing the bit to 0 while set will request a message abort. `1` Requests sending a message; the bit will automatically clear when all the messages queued in the Transmit Queue are successfully sent
UINC	8	Increment Head/Tail bit `0` FIFO head will not increment by a single message `1` FIFO head will increment by a single message
TXEN	7	TX Enable `1` Transmit Message Queue. This bit always reads as 1.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
TXQEIE	2	Transmit Queue Empty Interrupt Enable bit `0` Interrupt disabled for Transmit Queue empty `1` Interrupt enabled for Transmit Queue empty
TXQNIE	0	Transmit Queue Not Full Interrupt Enable bit `0` Interrupt disabled for Transmit Queue not full `1` Interrupt enabled for Transmit Queue not full
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1TXQSTATransmit Queue Status Register

Address: 0xBF880150
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
TXQCI	12:8	Transmit Queue Message Index bits
TXABT	7	Message Aborted Status bit `0` Message completed successfully `1` Message was aborted
TXLARB	6	Message Lost Arbitration Status bit `0` Message did not loose arbitration while being sent `1` Message lost arbitration while being sent
TXERR	5	Error Detected During Transmission bit `0` A bus error did not occur while the message was being sent `1` A bus error occurred while the message was being sent
TXATIF	4	Transmit Attempts Exhausted Interrupt Pending bit `0` Interrupt Not pending `1` Interrupt pending
TXQEIF	2	Transmit Queue Empty Interrupt Flag bit `0` Transmit Queue is not empty `1` Transmit Queue is empty
TXQNIF	0	Transmit Queue Not Full Interrupt Flag bit `0` Transmit Queue is full `1` Transmit Queue is not full

CFD1TXQUATransmit Queue User Address Register

Address: 0xBF880160
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TXQUA	31:0	Transmit Queue User Address bits

CFD1FIFOCON1FIFO Control Registe

Address: 0xBF880170
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA1

Address: 0xBF880180
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA1

Address: 0xBF880190
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON2FIFO Control Register

Address: 0xBF8801A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA2

Address: 0xBF8801B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA2

Address: 0xBF8801C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON3FIFO Control Register

Address: 0xBF8801D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA3

Address: 0xBF8801E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA3

Address: 0xBF8801F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON4FIFO Control Register

Address: 0xBF880200
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA4

Address: 0xBF880210
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA4

Address: 0xBF880220
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON5FIFO Control Register

Address: 0xBF880230
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA5

Address: 0xBF880240
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA5

Address: 0xBF880250
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON6FIFO Control Register

Address: 0xBF880260
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA6

Address: 0xBF880270
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA6

Address: 0xBF880280
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON7FIFO Control Register

Address: 0xBF880290
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA7

Address: 0xBF8802A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA7

Address: 0xBF8802B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON8FIFO Control Register

Address: 0xBF8802C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA8

Address: 0xBF8802D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA8

Address: 0xBF8802E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON9FIFO Control Register

Address: 0xBF8802F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA9

Address: 0xBF880300
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA9

Address: 0xBF880310
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON10FIFO Control Register

Address: 0xBF880320
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA10

Address: 0xBF880330
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA10

Address: 0xBF880340
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON11FIFO Control Registe

Address: 0xBF880350
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA11

Address: 0xBF880360
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA11

Address: 0xBF880370
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON12FIFO Control Register

Address: 0xBF880380
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA12

Address: 0xBF880390
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA12

Address: 0xBF8803A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON13FIFO Control Register

Address: 0xBF8803B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA13

Address: 0xBF8803C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA13

Address: 0xBF8803D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON14FIFO Control Register

Address: 0xBF8803E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA14

Address: 0xBF8803F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA14

Address: 0xBF880400
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON15FIFO Control Register

Address: 0xBF880410
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA15

Address: 0xBF880420
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA15

Address: 0xBF880430
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON16FIFO Control Register

Address: 0xBF880440
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA16

Address: 0xBF880450
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA16

Address: 0xBF880460
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON17FIFO Control Register

Address: 0xBF880470
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA17

Address: 0xBF880480
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA17

Address: 0xBF880490
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON18FIFO Control Register

Address: 0xBF8804A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA18

Address: 0xBF8804B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA18

Address: 0xBF8804C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON19FIFO Control Register

Address: 0xBF8804D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA19

Address: 0xBF8804E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA19

Address: 0xBF8804F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON20FIFO Control Register

Address: 0xBF880500
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA20

Address: 0xBF880510
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA20

Address: 0xBF880520
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON21FIFO Control Registe

Address: 0xBF880530
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA21

Address: 0xBF880540
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA21

Address: 0xBF880550
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON22FIFO Control Register

Address: 0xBF880560
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA22

Address: 0xBF880570
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA22

Address: 0xBF880580
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON23FIFO Control Register

Address: 0xBF880590
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA23

Address: 0xBF8805A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA23

Address: 0xBF8805B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON24FIFO Control Register

Address: 0xBF8805C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA24

Address: 0xBF8805D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA24

Address: 0xBF8805E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON25FIFO Control Register

Address: 0xBF8805F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA25

Address: 0xBF880600
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA25

Address: 0xBF880610
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON26FIFO Control Register

Address: 0xBF880620
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA26

Address: 0xBF880630
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA26

Address: 0xBF880640
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON27FIFO Control Register

Address: 0xBF880650
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA27

Address: 0xBF880660
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA27

Address: 0xBF880670
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON28FIFO Control Register

Address: 0xBF880680
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA28

Address: 0xBF880690
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA28

Address: 0xBF8806A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON29FIFO Control Register

Address: 0xBF8806B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA29

Address: 0xBF8806C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA29

Address: 0xBF8806D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON30FIFO Control Register

Address: 0xBF8806E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA30

Address: 0xBF8806F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA30

Address: 0xBF880700
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FIFOCON31FIFO Control Registe

Address: 0xBF880710
Reset: 0x00000000
Access: read/write
Size: 32-bit

15 fields

Field	Bits	What it does
FSIZE	28:24	FIFO Size bits `0` FIFO is 1 Message deep `1` FIFO is 2 Messages deep `2` FIFO is 3 Messages deep `3` FIFO is 4 Messages deep `4` FIFO is 5 Messages deep `5` FIFO is 6 Messages deep `6` FIFO is 7 Messages deep `7` FIFO is 8 Messages deep `8` FIFO is 9 Messages deep `9` FIFO is 10 Messages deep `10` FIFO is 11 Messages deep `11` FIFO is 12 Messages deep `12` FIFO is 13 Messages deep `13` FIFO is 14 Messages deep `14` FIFO is 15 Messages deep `15` FIFO is 16 Messages deep `16` FIFO is 17 Messages deep `17` FIFO is 18 Messages deep `18` FIFO is 19 Messages deep `19` FIFO is 20 Messages deep `20` FIFO is 21 Messages deep `21` FIFO is 22 Messages deep `22` FIFO is 23 Messages deep `23` FIFO is 24 Messages deep `24` FIFO is 25 Messages deep `25` FIFO is 26 Messages deep `26` FIFO is 27 Messages deep `27` FIFO is 28 Messages deep `28` FIFO is 29 Messages deep `29` FIFO is 30 Messages deep `30` FIFO is 31 Messages deep `31` FIFO is 32 Messages deep
TXAT	22:21	Retransmission Attempts bits `0` Disable retransmission attempts `1` Three retransmission attempts `2` Unlimited number of retransmission attempts `3` Unlimited number of retransmission attempts
TXPRI	20:16	Message Transmit Priority bits (EXPANDED) `0` Lowest Message Priority `1` Message priority 1 `2` Message priority 2 `3` Message priority 3 `4` Message priority 4 `5` Message priority 5 `6` Message priority 6 `7` Message priority 7 `8` Message priority 8 `9` Message priority 9 `10` Message priority 10 `11` Message priority 11 `12` Message priority 12 `13` Message priority 13 `14` Message priority 14 `15` Message priority 15 `16` Message priority 16 `17` Message priority 17 `18` Message priority 18 `19` Message priority 19 `20` Message priority 20 `21` Message priority 21 `22` Message priority 22 `23` Message priority 23 `24` Message priority 24 `25` Message priority 25 `26` Message priority 26 `27` Message priority 27 `28` Message priority 28 `29` Message priority 29 `30` Message priority 30 `31` Highest Message Priority
FRESET	10	FIFO Reset bit `0` No effect `1` FIFO will be reset when bit is set; cleared by hardware when FIFO is reset. User should poll whether this bit is clear before taking any action
TXREQ	9	Message Send Request bit `0` (TXEN is 1) Clearing the bit to 0 while set will request a message abort. / (TXEN is 0) This bit has no effect. `1` (TXEN is 1) Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent / (TXEN is 0) This bit has no effect.
UINC	8	Increment Head / Tail bit `0` (TXEN is 1) The FIFO head will not increment by a single message / (TXEN is 0) The FIFO tail will not increment by a single message `1` (TXEN is 1) The FIFO head will increment by a single message / (TXEN is 0) The FIFO tail will increment by a single message
TXEN	7	TX / RX Buffer Selection bit `0` Receive Message Object `1` Transmit Message Object
RTREN	6	Auto RTR Enable bit `0` When a remote transmit is received `1` When a remote transmit is received
RXTSEN	5	Received Message Time Stamp Enable bit `0` Dont capture time stamp. `1` Capture time stamp in received message object in RAM.
TXATIE	4	Transmit Attempts Exhausted Interrupt Enable bit `0` Disable interrupt `1` Enable interrupt
RXOVIE	3	Overflow Interrupt Enable bit `0` Interrupt disabled for overflow event `1` Interrupt enabled for overflow event
TFERFFIE	2	Transmit/Receive FIFO Empty/Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO empty / (TXEN is 0) Interrupt disabled for FIFO full `1` (TXEN is 1) Interrupt enabled for FIFO empty / (TXEN is 0) Interrupt enabled for FIFO full
TFHRFHIE	1	Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO half empty / (TXEN is 0) Interrupt disabled for FIFO half full `1` (TXEN is 1) Interrupt enabled for FIFO half empty / (TXEN is 0) Interrupt enabled for FIFO half full
TFNRFNIE	0	Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit `0` (TXEN is 1) Interrupt disabled for FIFO not full / (TXEN is 0) Interrupt disabled for FIFO not empty `1` (TXEN is 1) Interrupt enabled for FIFO not full / (TXEN is 0) Interrupt enabled for FIFO not empty
PLSIZE	31:29	Payload Size bits `0` 8 data bytes `1` 12 data bytes `2` 16 data bytes `3` 20 data bytes `4` 24 data bytes `5` 32 data bytes `6` 48 data bytes `7` 64 data bytes

CFD1FIFOSTA31

Address: 0xBF880720
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
FIFOCI	12:8
TXABT	7
TXLARB	6
TXERR	5
TXATIF	4
RXOVIF	3
TFERFFIF	2
TFHRFHIF	1
TFNRFNIF	0

CFD1FIFOUA31

Address: 0xBF880730
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
FIFOUA	31:0	FIFO User Address bits

CFD1FLTCON0Filter Control Register

Address: 0xBF880740
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
F3BP	28:24	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN2	23	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F2BP	20:16	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN1	15	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F1BP	12:8	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN0	7	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F0BP	4:0	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the RX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN3	31	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled

CFD1FLTCON1Filter Control Registe

Address: 0xBF880750
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
F7BP	28:24	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN6	23	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F6BP	20:16	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN5	15	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F5BP	12:8	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN4	7	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F4BP	4:0	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN7	31	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled

CFD1FLTCON2Filter Control Register

Address: 0xBF880760
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
F11BP	28:24	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN10	23	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F10BP	20:16	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN9	15	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F9BP	12:8	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN8	7	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F8BP	4:0	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN11	31	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled

CFD1FLTCON3Filter Control Register

Address: 0xBF880770
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
F15BP	28:24	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN14	23	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F14BP	20:16	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN13	15	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F13BP	12:8	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN12	7	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F12BP	4:0	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN15	31	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled

CFD1FLTCON4Filter Control Register

Address: 0xBF880780
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
F19BP	28:24	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN18	23	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F18BP	20:16	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN17	15	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F17BP	12:8	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN16	7	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F16BP	4:0	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN19	31	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled

CFD1FLTCON5Filter Control Register

Address: 0xBF880790
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
F23BP	28:24	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN22	23	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F22BP	20:16	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN21	15	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F21BP	12:8	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN20	7	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F20BP	4:0	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN23	31	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled

CFD1FLTCON6Filter Control Register

Address: 0xBF8807A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
F27BP	28:24	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN26	23	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F26BP	20:16	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN25	15	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F25BP	12:8	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN24	7	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F24BP	4:0	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN27	31	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled

CFD1FLTCON7Filter Control Register

Address: 0xBF8807B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
F31BP	28:24	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN30	23	Enable Filter nto Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F30BP	20:16	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN29	15	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F29BP	12:8	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN28	7	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled
F28BP	4:0	Pointer to Object when Filter n hits bits `0` Reserved. Object 0 is the TX Queue and cannot receive messages. `1` Message matching filter is stored in Object 1 `2` Message matching filter is stored in Object 2 `3` Message matching filter is stored in Object 3 `4` Message matching filter is stored in Object 4 `5` Message matching filter is stored in Object 5 `6` Message matching filter is stored in Object 6 `7` Message matching filter is stored in Object 7 `8` Message matching filter is stored in Object 8 `9` Message matching filter is stored in Object 9 `10` Message matching filter is stored in Object 10 `11` Message matching filter is stored in Object 11 `12` Message matching filter is stored in Object 12 `13` Message matching filter is stored in Object 13 `14` Message matching filter is stored in Object 14 `15` Message matching filter is stored in Object 15 `16` Message matching filter is stored in Object 16 `17` Message matching filter is stored in Object 17 `18` Message matching filter is stored in Object 18 `19` Message matching filter is stored in Object 19 `20` Message matching filter is stored in Object 20 `21` Message matching filter is stored in Object 21 `22` Message matching filter is stored in Object 22 `23` Message matching filter is stored in Object 23 `24` Message matching filter is stored in Object 24 `25` Message matching filter is stored in Object 25 `26` Message matching filter is stored in Object 26 `27` Message matching filter is stored in Object 27 `28` Message matching filter is stored in Object 28 `29` Message matching filter is stored in Object 29 `30` Message matching filter is stored in Object 30 `31` Message matching filter is stored in Object 31
FLTEN31	31	Enable Filter n to Accept Messages bits `0` Filter is disabled `1` Filter is enabled

CFD1FLTOBJ0

Address: 0xBF8807C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit
EID	28:11
SID	10:0

CFD1MASK0

Address: 0xBF8807D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ1Filter Object Registe

Address: 0xBF8807E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK1Filter Object Registe

Address: 0xBF8807F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ2Filter Object Register

Address: 0xBF880800
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK2

Address: 0xBF880810
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ3Filter Object Register

Address: 0xBF880820
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK3

Address: 0xBF880830
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ4Filter Object Register

Address: 0xBF880840
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK4Filter Object Register

Address: 0xBF880850
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ5Filter Object Register

Address: 0xBF880860
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK5Filter Object Register

Address: 0xBF880870
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ6Filter Object Register

Address: 0xBF880880
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK6Filter Object Register

Address: 0xBF880890
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ7Filter Object Register

Address: 0xBF8808A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK7Filter Object Register

Address: 0xBF8808B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ8Filter Object Register

Address: 0xBF8808C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK8Filter Object Register

Address: 0xBF8808D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ9Filter Object Register

Address: 0xBF8808E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK9Filter Object Register

Address: 0xBF8808F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ10Filter Object Register

Address: 0xBF880900
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK10Filter Object Register

Address: 0xBF880910
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ11Filter Object Registe

Address: 0xBF880920
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK11Filter Object Registe

Address: 0xBF880930
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ12Filter Object Register

Address: 0xBF880940
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK12Filter Object Register

Address: 0xBF880950
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ13Filter Object Register

Address: 0xBF880960
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK13Filter Object Register

Address: 0xBF880970
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ14Filter Object Register

Address: 0xBF880980
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK14Filter Object Register

Address: 0xBF880990
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ15Filter Object Register

Address: 0xBF8809A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK15Filter Object Register

Address: 0xBF8809B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ16Filter Object Register

Address: 0xBF8809C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK16Filter Object Register

Address: 0xBF8809D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ17Filter Object Register

Address: 0xBF8809E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK17Filter Object Register

Address: 0xBF8809F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ18Filter Object Register

Address: 0xBF880A00
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK18Filter Object Register

Address: 0xBF880A10
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ19Filter Object Register

Address: 0xBF880A20
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK19Filter Object Register

Address: 0xBF880A30
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ20Filter Object Register

Address: 0xBF880A40
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK20Filter Object Register

Address: 0xBF880A50
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ22Filter Object Register

Address: 0xBF880A80
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK22Filter Object Register

Address: 0xBF880A90
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ23Filter Object Register

Address: 0xBF880AA0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK23Filter Object Register

Address: 0xBF880AB0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ24Filter Object Register

Address: 0xBF880AC0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK24Filter Object Register

Address: 0xBF880AD0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ25Filter Object Register

Address: 0xBF880AE0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK25Filter Object Register

Address: 0xBF880AF0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ26Filter Object Register

Address: 0xBF880B00
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK26Filter Object Register

Address: 0xBF880B10
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ27Filter Object Register

Address: 0xBF880B20
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK27Filter Object Register

Address: 0xBF880B30
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ28Filter Object Register

Address: 0xBF880B40
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK28Filter Object Register

Address: 0xBF880B50
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ29Filter Object Register

Address: 0xBF880B60
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK29Filter Object Register

Address: 0xBF880B70
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ30Filter Object Register

Address: 0xBF880B80
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK30Filter Object Register

Address: 0xBF880B90
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0

CFD1FLTOBJ31Filter Object Registe

Address: 0xBF880BA0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
EXIDE	30	Extended Identifier Enable bit `0` (If MIDE is 1) Match only messages with standard identifier addresses `1` (If MIDE is 1) Match only messages with extended identifier addresses
SID11	29	Standard Identifier Filter bit `0` Do not use extended standard Identifier bits `1` Extended standard identifier to 12-bit (i.e.
EID	28:11
SID	10:0

CFD1MASK31Filter Object Registe

Address: 0xBF880BB0
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
MIDE	30	Identifier Receive Mode bit `0` Match either standard or extended address message if filters match (i.e. `1` Match only message types (standard or extended address) that correspond to EXIDE bit in filter
MSID11	29	Standard Identifier Mask bit `0` Do not enable extended standard identifier mask (MSID) `1` Enable extended standard identifier mask to 12 bits (MSID
MEID	28:11
MSID	10:0