The 6 registers of CFG (Configuration and pin control), from 0xBF800000, with their reset value and every field. The PIC32MK0512MCM064 has 2203 registers in 115 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
CFG Configuration and pin control
CFGCONConfiguration Control Register
Address
0xBF800000
Reset
0x00000000
Access
read/write
Size
32-bit
17 fields
Field
Bits
What it does
ADCPRI
26
ADC Arbitration Priority to SRAM bit
0 ADC uses Least Recently Serviced Arbitration (same as other initiators)
1 ADC gets High Priority access to SRAM
PWAPIN6
23
PWM Alternate I/O Pin Select
PWMAPIN5
22
PWM Alternate I/O Pin Select
0 PWM5L functionality remains on pins
1 PWM5L functionality is replaced by PWMxH(x+6) functionality
PWMAPIN4
21
PWM Alternate I/O Pin Select
0 PWM4L functionality remains on pins
1 PWM4L functionality is replaced by PWMxH(x+6) functionality
PWMAPIN3
20
PWM Alternate I/O Pin Select
0 PWM3L functionality remains on pins
1 PWM3L functionality is replaced by PWMxH(x+6) functionality
PWMAPIN2
19
PWM Alternate I/O Pin Select
0 PWM2L functionality remains on pins
1 PWM2L functionality is replaced by PWMxH(x+6) functionality
PWMAPIN1
18
PWM Alternate I/O Pin Select
0 PWM1L functionality remains on pins
1 PWM1L functionality is replaced by PWMxH(x+6) functionality
ICACLK
17
Input Capture Alternate Clock Selection bit
0 All Input Capture modules use Timer2/3 as their timebase clock
1 Input Capture modules use an alternative Timer pair as their timebase clock
OCACLK
16
Output Compare Alternate Clock Selection bit
0 All Output Compare modules use Timer2/3 as their timebase clock
1 Output Compare modules use an alternative Timer pair as their timebase clock
IOLOCK
13
Peripheral Pin Select Lock bit
0 Peripheral Pin Select is not locked. Writes to PPS registers are allowed
1 Peripheral Pin Select is locked. Writes to PPS registers are not allowed
PMDLOCK
12
Peripheral Module Disable bit
0 Peripheral module is not locked. Writes to PMD registers are allowed
1 Peripheral module is locked. Writes to PMD registers are not allowed
PGLOCK
11
Permission Group Lock bit
0 Permission Group registers are not locked. Writes to PG registers are allowed
1 Permission Group registers are locked. Writes to PG registers are not allowed
IOANCPEN
7
I/O Analog Charge Pump Enable bit
0 Charge pump is disabled (default)
1 Charge pump is enabled
ECCCON
5:4
Flash ECC Configuration Bits
0 Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
1 Dynamic Flash ECC is enabled (ECCCON bits are locked)
2 ECC and dynamic ECC are disabled (ECCCON bits are locked)
3 ECC and dynamic ECC are disabled (ECCCON bits are writable)
JTAGEN
3
JTAG Port Enable bit
0 Disable the JTAG port
1 Enable the JTAG port
TROEN
2
Trace Output Enable bit
0 Disable trace outputs and stop trace clock
1 Enable trace outputs and start trace clock (trace probe must be present)
TDOEN
0
TDO Enable for 2-Wire JTAG
0 2-wire JTAG protocol does not use TDO
1 2-wire JTAG protocol uses TDO
DEVID
Address
0xBF800020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
DEVID
27:0
VER
31:28
SYSKEY
Address
0xBF800030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SYSKEY
31:0
CFGPGPermission Group Configuration Register
Address
0xBF8000E0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
ADCPG
25:24
ADC Permission bits
0 (If RDPER(0) is 1) read access / (If WRPER(0) is 1) write access
1 (If RDPER(1) is 1) read access / (If WRPER(1) is 1) write access
2 (If RDPER(2) is 1) read access / (If WRPER(2) is 1) write access
3 (If RDPER(3) is 1) read access / (If WRPER(3) is 1) write access
FCPG
23:22
Flash Control Permission Group bits
0 (If RDPER(0) is 1) read access / (If WRPER(0) is 1) write access
1 (If RDPER(1) is 1) read access / (If WRPER(1) is 1) write access
2 (If RDPER(2) is 1) read access / (If WRPER(2) is 1) write access
3 (If RDPER(3) is 1) read access / (If WRPER(3) is 1) write access
CAN1PG
13:12
CAN1 Module Permission Group bits
0 (If RDPER(0) is 1) read access / (If WRPER(0) is 1) write access
1 (If RDPER(1) is 1) read access / (If WRPER(1) is 1) write access
2 (If RDPER(2) is 1) read access / (If WRPER(2) is 1) write access
3 (If RDPER(3) is 1) read access / (If WRPER(3) is 1) write access
DMAPG
5:4
DMA Module Permission Group bits
0 (If RDPER(0) is 1) read access / (If WRPER(0) is 1) write access
1 (If RDPER(1) is 1) read access / (If WRPER(1) is 1) write access
2 (If RDPER(2) is 1) read access / (If WRPER(2) is 1) write access
3 (If RDPER(3) is 1) read access / (If WRPER(3) is 1) write access
CPUPG
1:0
CPU Instruction Space Permission Group bits
0 (If RDPER(0) is 1) read access / (If WRPER(0) is 1) write access
1 (If RDPER(1) is 1) read access / (If WRPER(1) is 1) write access
2 (If RDPER(2) is 1) read access / (If WRPER(2) is 1) write access
3 (If RDPER(3) is 1) read access / (If WRPER(3) is 1) write access
CFGAPP2
Address
0xBF800100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
POSCFAIL
21
Primary Oscillator Unable to Lock Status Read-only bit
0 Crystal or Resonator usage failed
0 Crystal or resonator is locked or is indeterminate. If successfully locked, clock status is determined bythe SPLLRDY (CLKSTAT<7>) status flag.
BETA