The 14 registers of PORTB (I/O port B), from 0xBF860100, with their reset value and every field. The PIC32MK1024GPD064 has 1106 registers in 106 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTB I/O port B
ANSELB
Address
0xBF860100
Reset
0x0000028F
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ANSB9
9
ANSB7
7
ANSB3
3
ANSB2
2
ANSB1
1
ANSB0
0
TRISB
Address
0xBF860110
Reset
0x0000FFFF
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
TRISB15
15
TRISB14
14
TRISB13
13
TRISB12
12
TRISB11
11
TRISB10
10
TRISB9
9
TRISB8
8
TRISB7
7
TRISB6
6
TRISB5
5
TRISB4
4
TRISB3
3
TRISB2
2
TRISB1
1
TRISB0
0
PORTB
Address
0xBF860120
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
RB15
15
RB14
14
RB13
13
RB12
12
RB11
11
RB10
10
RB9
9
RB8
8
RB7
7
RB6
6
RB5
5
RB4
4
RB3
3
RB2
2
RB1
1
RB0
0
LATB
Address
0xBF860130
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
LATB15
15
LATB14
14
LATB13
13
LATB12
12
LATB11
11
LATB10
10
LATB9
9
LATB8
8
LATB7
7
LATB6
6
LATB5
5
LATB4
4
LATB3
3
LATB2
2
LATB1
1
LATB0
0
ODCB
Address
0xBF860140
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ODCB15
15
ODCB14
14
ODCB13
13
ODCB12
12
ODCB11
11
ODCB10
10
ODCB9
9
ODCB8
8
ODCB7
7
ODCB6
6
ODCB5
5
ODCB4
4
ODCB3
3
ODCB2
2
ODCB1
1
ODCB0
0
CNPUB
Address
0xBF860150
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CNPUB15
15
CNPUB14
14
CNPUB13
13
CNPUB12
12
CNPUB11
11
CNPUB10
10
CNPUB9
9
CNPUB8
8
CNPUB7
7
CNPUB6
6
CNPUB5
5
CNPUB4
4
CNPUB3
3
CNPUB2
2
CNPUB1
1
CNPUB0
0
CNPDB
Address
0xBF860160
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CNPDB15
15
CNPDB14
14
CNPDB13
13
CNPDB12
12
CNPDB11
11
CNPDB10
10
CNPDB9
9
CNPDB8
8
CNPDB7
7
CNPDB6
6
CNPDB5
5
CNPDB4
4
CNPDB3
3
CNPDB2
2
CNPDB1
1
CNPDB0
0
CNCONBChange Notice control for PORTx Register
Address
0xBF860170
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).
BETA