The 2 registers of REFO1 (Reference clock output 1), from 0xBF801280, with their reset value and every field. The PIC32MK1024GPD064 has 1106 registers in 106 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
REFO1 Reference clock output 1
REFO1CONReference Oscillator Control Register (x = 1-4)
Address
0xBF801280
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RODIV
30:16
Reference Clock Divider bits
0 REFO is the same frequency as Base Clock (no divider)
1 REFO clock is Base clock frequency divided by 2 (1*2)
2 REFO clock is Base clock frequency divided by 4 (2*2)
3 REFO clock is Base clock frequency divided by 6 (3*2)
32767 REFO clock is Base clock frequency divided by 65534
ON
15
Output Enable bit
0 Reference Oscillator module is disabled
1 Reference Oscillator module is enabled
SIDL
13
Peripheral Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when the device enters Idle mode
OE
12
Reference Clock Output Enable bit
0 Reference clock is not driven out on REFCLKOx pin
1 Reference clock is driven out on REFCLKOx pin
RSLP
11
Reference Oscillator Module Run in Sleep bit
0 Reference Oscillator Module output is disabled in Sleep
1 Reference Oscillator Module output continues to run in Sleep
DIVSWEN
9
Divider Switch Enable bit
0 Divider switch is complete
1 Divider switch is in progress
ACTIVE
8
Reference Clock Request Status bit
0 Reference clock request is not active
1 Reference clock request is active
ROSEL
3:0
Reference Clock Source Select bits
0 System clock SYSCLK
1 Peripheral Clock 1 PBCLK1
2 Primary Oscillator POSC
3 Internal Fast Oscillator FRC
4 Low Power Oscillator LPRC
5 Secondary Oscillator SOSC
6 UPLL
7 System PLL Output SPLL
8 Reference Clock Input REFCLKI
9
10
11
12
13
14
15
REFO1TRIMReference Oscillator Trim Register (x = 1-4)
BETA