PIC32MK1024GPE100 CFG registers

The 5 registers of CFG (Configuration and pin control), from 0xBF800000, with their reset value and every field. The PIC32MK1024GPE100 has 1566 registers in 111 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CFG Configuration and pin control

CFGCONConfiguration Control Register

Address
0xBF800000
Reset
0x00000001
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
ADCPRI26ADC Arbitration Priority to SRAM bit
  • 0 ADC uses Least Recently Serviced Arbitration (same as other initiators)
  • 1 ADC gets High Priority access to SRAM
ICACLK17Input Capture Alternate Clock Selection bit
  • 0 All Input Capture modules use Timer2/3 as their timebase clock
  • 1 Input Capture modules use an alternative Timer pair as their timebase clock
OCACLK16Output Compare Alternate Clock Selection bit
  • 0 All Output Compare modules use Timer2/3 as their timebase clock
  • 1 Output Compare modules use an alternative Timer pair as their timebase clock
IOLOCK13Peripheral Pin Select Lock bit(
  • 0 Peripheral Pin Select is not locked. Writes to PPS registers are allowed
  • 1 Peripheral Pin Select is locked. Writes to PPS registers are not allowed
PMDLOCK12Peripheral Module Disable bit
  • 0 Peripheral module is not locked. Writes to PMD registers are allowed
  • 1 Peripheral module is locked. Writes to PMD registers are not allowed
PGLOCK11Permission Group Lock bit
  • 0 Permission Group registers are not locked. Writes to PG registers are allowed
  • 1 Permission Group registers are locked. Writes to PG registers are not allowed
IOANCPEN7I/O Analog Charge Pump Enable bit
  • 0 Charge pump is disabled (default)
  • 1 Charge pump is enabled
JTAGEN3JTAG Port Enable bit
  • 0 Disable the JTAG port
  • 1 Enable the JTAG port
TROEN2Trace Output Enable bit
  • 0 Disable trace outputs and stop trace clock
  • 1 Enable trace outputs and start trace clock (trace probe must be present)
TDOEN0TDO Enable for 2-Wire JTAG
  • 0 2-wire JTAG protocol does not use TDO
  • 1 2-wire JTAG protocol uses TDO

DEVIDDevice and Revision ID Register

Address
0xBF800020
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DEVID27:0
VER31:28

SYSKEY

Address
0xBF800030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SYSKEY31:0

CFGPGPermission Group Configuration Register

Address
0xBF8000E0
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
ADCPG25:24ADC Permission bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1
FCPG23:22Flash Control Permission Group bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1
CAN4PG19:18
CAN3PG17:16CAN3 Module Permission Group bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1
CAN2PG15:14CAN2 Module Permission Group bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1
CAN1PG13:12CAN1 Module Permission Group bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1
USB2PG11:10USB2 Module Permission Group bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1
USB1PG9:8USB1 Module Permission Group bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1
DMAPG5:4DMA Module Permission Group bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1
CPUPG1:0CPU Permission Group bits
  • 0 Read access if RDPER = 1; write access if WRPER<0> = 1
  • 1 Read access if RDPER = 1; write access if WRPER<1> = 1
  • 2 Read access if RDPER = 1; write access if WRPER<2> = 1
  • 3 Read access if RDPER = 1; write access if WRPER<3> = 1

CFGCON2EE Data and Op amp Configuration Register

Address
0xBF800110
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ENPGA520Enable Op amp 5 to PGA Mode bit
  • 0 Op amp 3-terminal standard operation (default)
  • 1 Op amp enable 1x gain mode
ENPGA318Enable Op amp 3 to PGA Mode bit
  • 0 Op amp 3-terminal standard operation (default)
  • 1 Op amp enable 1x gain mode
ENPGA217Enable Op amp 2 to PGA Mode bit
  • 0 Op amp 3-terminal standard operation (default)
  • 1 Op amp enable 1x gain mode
ENPGA116Enable Op amp 1 to PGA Mode bit
  • 0 Op amp 3-terminal standard operation (default)
  • 1 Op amp enable 1x gain mode
EEWS7:0