PIC32MK1024GPK064 OSC registers

The 13 registers of OSC (Oscillator and clocks), from 0xBF801200, with their reset value and every field. The PIC32MK1024GPK064 has 1153 registers in 106 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

OSC Oscillator and clocks

OSCCONOscillator Control Register

Address
0xBF801200
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
FRCDIV26:24Internal Fast RC Oscillator Clock Divider bits
  • 0 FRC divided by 1 (default setting)
  • 1 FRC divided by 2
  • 2 FRC divided by 4
  • 3 FRC divided by 8
  • 4 FRC divided by 16
  • 5 FRC divided by 32
  • 6 FRC divided by 64
  • 7 FRC divided by 256
DRMEN23Dream Mode Enable bit
  • 0 Dream mode is disabled
  • 1 Dream mode is enabled
SLP2SPD21Sleep Two-speed Start-up Control bit
  • 0 Use the selected clock directly
  • 1 Use FRC as SYSCLK until the selected clock is ready
COSC14:12Current Oscillator Selection bits
  • 0 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV) supports FRN divided by N
  • 1 System PLL (SPLL) input clock and divider set by SPLLCON
  • 2 Primary Oscillator (Posc) (HS or EC)
  • 3 USB PLL (UPLL) input clock and divider are set by UPLLCON
  • 4 Secondary Oscillator (SOSC)
  • 5 Internal Low-Power RC (LPRC) Oscillator
  • 6 Backup Fast RC (BFRC) Oscillator
  • 7 Reserved
NOSC10:8New Oscillator Selection bits
  • 0 Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV) supports FRN divided by N
  • 1 System PLL (SPLL) input clock and divider set by SPLLCON
  • 2 Primary Oscillator (Posc) (HS or EC)
  • 3 USB PLL (UPLL) input clock and divider are set by UPLLCON
  • 4 Secondary Oscillator
  • 5 Internal Low-Power RC (LPRC) Oscillator
  • 6 Backup Fast RC (BFRC) Oscillator
  • 7 Reserved
CLKLOCK7Clock Selection Lock Enable bit
  • 0 Clock and PLL selections are not locked and may be modified
  • 1 Clock and PLL selections are locked
SLPEN4Sleep Mode Enable bit
  • 0 Device will enter Idle mode when a WAIT instruction is executed
  • 1 Device will enter Sleep mode when a WAIT instruction is executed
CF3Clock Fail Detect bit
  • 0 No clock failure has been detected
  • 1 FSCM has detected a clock failure
UFRCEN2USB FRC Sleep Clock Enable bit
  • 0 USB input clock is determined by the UPOSCEN bit (UPLLCON)
  • 1 FRC is the USB input clock for wake from Sleep mode
SOSCEN1Secondary Oscillator (
  • 0 Disable Secondary Oscillator
  • 1 Enable Secondary Oscillator
OSWEN0Oscillator Switch Enable bit
  • 0 Oscillator switch is complete
  • 1 Initiate an oscillator switch to selection specified by NOSC bits

OSCTUNFRC Tuning Register

Address
0xBF801210
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TUN5:0FRC Oscillator Tuning bits
  • 0 -1.500%
  • 32 0.000% (Nominal Center Frequency
  • 63 +1.453%

SPLLCONSystem PLL Control Register

Address
0xBF801220
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
PLLODIV26:24System PLL Output Clock Divider bits
  • 0 Reserved
  • 1 PLL Divide by 2
  • 2 PLL Divide by 4
  • 3 PLL Divide by 8
  • 4 PLL Divide by 16
  • 5 PLL Divide by 32
  • 6 Reserved
  • 7 Reserved
PLLMULT22:16System PLL Multiplier bits
  • 0 Multiply by 1
  • 1 Multiply by 2
  • 2 Multiply by 3
  • 3 Multiply by 4
  • 4 Multiply by 5
  • 5 Multiply by 6
  • 6 Multiply by 7
  • 7 Multiply by 8
  • 8 Multiply by 9
  • 9 Multiply by 10
  • 10 Multiply by 11
  • 11 Multiply by 12
  • 12 Multiply by 13
  • 13 Multiply by 14
  • 14 Multiply by 15
  • 15 Multiply by 16
  • 16 Multiply by 17
  • 17 Multiply by 18
  • 18 Multiply by 19
  • 19 Multiply by 20
  • 20 Multiply by 21
  • 21 Multiply by 22
  • 22 Multiply by 23
  • 23 Multiply by 24
  • 24 Multiply by 25
  • 25 Multiply by 26
  • 26 Multiply by 27
  • 27 Multiply by 28
  • 28 Multiply by 29
  • 29 Multiply by 30
  • 30 Multiply by 31
  • 31 Multiply by 32
  • 32 Multiply by 33
  • 33 Multiply by 34
  • 34 Multiply by 35
  • 35 Multiply by 36
  • 36 Multiply by 37
  • 37 Multiply by 38
  • 38 Multiply by 39
  • 39 Multiply by 40
  • 40 Multiply by 41
  • 41 Multiply by 42
  • 42 Multiply by 43
  • 43 Multiply by 44
  • 44 Multiply by 45
  • 45 Multiply by 46
  • 46 Multiply by 47
  • 47 Multiply by 48
  • 48 Multiply by 49
  • 49 Multiply by 50
  • 50 Multiply by 51
  • 51 Multiply by 52
  • 52 Multiply by 53
  • 53 Multiply by 54
  • 54 Multiply by 55
  • 55 Multiply by 56
  • 56 Multiply by 57
  • 57 Multiply by 58
  • 58 Multiply by 59
  • 59 Multiply by 60
  • 60 Multiply by 61
  • 61 Multiply by 62
  • 62 Multiply by 63
  • 63 Multiply by 64
  • 64 Multiply by 65
  • 65 Multiply by 66
  • 66 Multiply by 67
  • 67 Multiply by 68
  • 68 Multiply by 69
  • 69 Multiply by 70
  • 70 Multiply by 71
  • 71 Multiply by 72
  • 72 Multiply by 73
  • 73 Multiply by 74
  • 74 Multiply by 75
  • 75 Multiply by 76
  • 76 Multiply by 77
  • 77 Multiply by 78
  • 78 Multiply by 79
  • 79 Multiply by 80
  • 80 Multiply by 81
  • 81 Multiply by 82
  • 82 Multiply by 83
  • 83 Multiply by 84
  • 84 Multiply by 85
  • 85 Multiply by 86
  • 86 Multiply by 87
  • 87 Multiply by 88
  • 88 Multiply by 89
  • 89 Multiply by 90
  • 90 Multiply by 91
  • 91 Multiply by 92
  • 92 Multiply by 93
  • 93 Multiply by 94
  • 94 Multiply by 95
  • 95 Multiply by 96
  • 96 Multiply by 97
  • 97 Multiply by 98
  • 98 Multiply by 99
  • 99 Multiply by 100
  • 100 Multiply by 101
  • 101 Multiply by 102
  • 102 Multiply by 103
  • 103 Multiply by 104
  • 104 Multiply by 105
  • 105 Multiply by 106
  • 106 Multiply by 107
  • 107 Multiply by 108
  • 108 Multiply by 109
  • 109 Multiply by 110
  • 110 Multiply by 111
  • 111 Multiply by 112
  • 112 Multiply by 113
  • 113 Multiply by 114
  • 114 Multiply by 115
  • 115 Multiply by 116
  • 116 Multiply by 117
  • 117 Multiply by 118
  • 118 Multiply by 119
  • 119 Multiply by 120
  • 120 Multiply by 121
  • 121 Multiply by 122
  • 122 Multiply by 123
  • 123 Multiply by 124
  • 124 Multiply by 125
  • 125 Multiply by 126
  • 126 Multiply by 127
  • 127 Multiply by 128
PLLIDIV10:8System PLL Input Clock Divider bits
  • 0 Divide by 1
  • 1 Divide by 2
  • 2 Divide by 3
  • 3 Divide by 4
  • 4 Divide by 5
  • 5 Divide by 6
  • 6 Divide by 7
  • 7 Divide by 8
PLLICLK7System PLL Input Clock Source bit
  • 0 Posc is selected as the input to the System PLL
  • 1 FRC is selected as the input to the System PLL
PLLRANGE2:0System PLL Frequency Range Selection bits
  • 0 Bypass
  • 1 5-10 MHz
  • 2 8-16 MHz
  • 3 13-26 MHz
  • 4 21-42 MHz
  • 5 34-64 MHz
  • 6 54-64 MHz
  • 7 Reserved

UPLLCONUSB PLL Control Register

Address
0xBF801230
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
UPOSCEN29Output Enable bit
  • 0 USB input clock is UPLL
  • 1 USB input clock is Posc
PLLODIV26:24System PLL Output Clock Divider bits
  • 0 Reserved
  • 1 PLL Divide by 2
  • 2 PLL Divide by 4
  • 3 PLL Divide by 8
  • 4 PLL Divide by 16
  • 5 PLL Divide by 32
  • 6 Reserved
  • 7 Reserved
PLLMULT22:16System PLL Multiplier Output Clock Divider bits
  • 0 Multiply by 1
  • 1 Multiply by 2
  • 2 Multiply by 3
  • 3 Multiply by 4
  • 4 Multiply by 5
  • 5 Multiply by 6
  • 6 Multiply by 7
  • 7 Multiply by 8
  • 8 Multiply by 9
  • 9 Multiply by 10
  • 10 Multiply by 11
  • 11 Multiply by 12
  • 12 Multiply by 13
  • 13 Multiply by 14
  • 14 Multiply by 15
  • 15 Multiply by 16
  • 16 Multiply by 17
  • 17 Multiply by 18
  • 18 Multiply by 19
  • 19 Multiply by 20
  • 20 Multiply by 21
  • 21 Multiply by 22
  • 22 Multiply by 23
  • 23 Multiply by 24
  • 24 Multiply by 25
  • 25 Multiply by 26
  • 26 Multiply by 27
  • 27 Multiply by 28
  • 28 Multiply by 29
  • 29 Multiply by 30
  • 30 Multiply by 31
  • 31 Multiply by 32
  • 32 Multiply by 33
  • 33 Multiply by 34
  • 34 Multiply by 35
  • 35 Multiply by 36
  • 36 Multiply by 37
  • 37 Multiply by 38
  • 38 Multiply by 39
  • 39 Multiply by 40
  • 40 Multiply by 41
  • 41 Multiply by 42
  • 42 Multiply by 43
  • 43 Multiply by 44
  • 44 Multiply by 45
  • 45 Multiply by 46
  • 46 Multiply by 47
  • 47 Multiply by 48
  • 48 Multiply by 49
  • 49 Multiply by 50
  • 50 Multiply by 51
  • 51 Multiply by 52
  • 52 Multiply by 53
  • 53 Multiply by 54
  • 54 Multiply by 55
  • 55 Multiply by 56
  • 56 Multiply by 57
  • 57 Multiply by 58
  • 58 Multiply by 59
  • 59 Multiply by 60
  • 60 Multiply by 61
  • 61 Multiply by 62
  • 62 Multiply by 63
  • 63 Multiply by 64
  • 64 Multiply by 65
  • 65 Multiply by 66
  • 66 Multiply by 67
  • 67 Multiply by 68
  • 68 Multiply by 69
  • 69 Multiply by 70
  • 70 Multiply by 71
  • 71 Multiply by 72
  • 72 Multiply by 73
  • 73 Multiply by 74
  • 74 Multiply by 75
  • 75 Multiply by 76
  • 76 Multiply by 77
  • 77 Multiply by 78
  • 78 Multiply by 79
  • 79 Multiply by 80
  • 80 Multiply by 81
  • 81 Multiply by 82
  • 82 Multiply by 83
  • 83 Multiply by 84
  • 84 Multiply by 85
  • 85 Multiply by 86
  • 86 Multiply by 87
  • 87 Multiply by 88
  • 88 Multiply by 89
  • 89 Multiply by 90
  • 90 Multiply by 91
  • 91 Multiply by 92
  • 92 Multiply by 93
  • 93 Multiply by 94
  • 94 Multiply by 95
  • 95 Multiply by 96
  • 96 Multiply by 97
  • 97 Multiply by 98
  • 98 Multiply by 99
  • 99 Multiply by 100
  • 100 Multiply by 101
  • 101 Multiply by 102
  • 102 Multiply by 103
  • 103 Multiply by 104
  • 104 Multiply by 105
  • 105 Multiply by 106
  • 106 Multiply by 107
  • 107 Multiply by 108
  • 108 Multiply by 109
  • 109 Multiply by 110
  • 110 Multiply by 111
  • 111 Multiply by 112
  • 112 Multiply by 113
  • 113 Multiply by 114
  • 114 Multiply by 115
  • 115 Multiply by 116
  • 116 Multiply by 117
  • 117 Multiply by 118
  • 118 Multiply by 119
  • 119 Multiply by 120
  • 120 Multiply by 121
  • 121 Multiply by 122
  • 122 Multiply by 123
  • 123 Multiply by 124
  • 124 Multiply by 125
  • 125 Multiply by 126
  • 126 Multiply by 127
  • 127 Multiply by 128
PLLIDIV10:8System PLL Input Clock Divider bits
  • 0 Divide by 1
  • 1 Divide by 2
  • 2 Divide by 3
  • 3 Divide by 4
  • 4 Divide by 5
  • 5 Divide by 6
  • 6 Divide by 7
  • 7 Divide by 8
PLLRANGE2:0System PLL Frequency Range Selection bits
  • 0 Bypass
  • 1 5-10 MHz
  • 2 8-16 MHz
  • 3 13-26 MHz
  • 4 21-42 MHz
  • 5 34-68 MHz
  • 6 54-90 MHz
  • 7 Reserved

PB1DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801300
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x < 6)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4 (default value for x = 6)
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB2DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801310
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x < 6)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4 (default value for x = 6)
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB3DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801320
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x < 6)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4 (default value for x = 6)
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB4DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801330
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x < 6)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4 (default value for x = 6)
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB5DIV

Address
0xBF801340
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15
PBDIVRDY11
PBDIV6:0

PB6DIVPeripheral Bus x Clock Divisor Control Register (x = 1-7)

Address
0xBF801350
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15Peripheral Bus x Output Clock Enable bit
  • 0 Output clock is disabled
  • 1 Output clock is enabled
PBDIVRDY11Peripheral Bus x Clock Divisor Ready bit
  • 0 Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
  • 1 Clock divisor logic is not switching divisors and the PBxDIV bits may be written
PBDIV6:0Peripheral Bus x Clock Divisor Control bits
  • 0 PBCLKx is SYSCLK divided by 1 (default value for x = 7)
  • 1 PBCLKx is SYSCLK divided by 2 (default value for x < 6)
  • 2 PBCLKx is SYSCLK divided by 3
  • 3 PBCLKx is SYSCLK divided by 4 (default value for x = 6)
  • 126 PBCLKx is SYSCLK divided by 127
  • 127 PBCLKx is SYSCLK divided by 128

PB7DIV

Address
0xBF801360
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15
PBDIVRDY11
PBDIV6:0

SLEWCONOscillator Slew Control Register

Address
0xBF801380
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
SYSDIV19:16System Clock Divide Control bits
  • 0 SYSCLK is not divided
  • 1 SYSCLK is divided by 2
  • 2 SYSCLK is divided by 3
  • 3 SYSCLK is divided by 4
  • 4 SYSCLK is divided by 5
  • 5 SYSCLK is divided by 6
  • 6 SYSCLK is divided by 7
  • 7 SYSCLK is divided by 8
  • 8 SYSCLK is divided by 9
  • 9 SYSCLK is divided by 10
  • 10 SYSCLK is divided by 11
  • 11 SYSCLK is divided by 12
  • 12 SYSCLK is divided by 13
  • 13 SYSCLK is divided by 14
  • 14 SYSCLK is divided by 15
  • 15 SYSCLK is divided by 16
SLWDIV10:8Slew Divisor Steps Control bits
  • 0 No divisor is used during slewing
  • 1 Steps are divide by 2, and then no divisor
  • 2 Steps are divide by 4, 2, and then no divisor
  • 3 Steps are divide by 8, 4, 2, and then no divisor
  • 4 Steps are divide by 16, 8, 4, 2, and then no divisor
  • 5 Steps are divide by 32, 16, 8, 4, 2, and then no divisor
  • 6 Steps are divide by 64, 32, 16, 8, 4, 2, and then no divisor
  • 7 Steps are divide by 128, 64, 32, 16, 8, 4, 2, and then no divisor
UPEN2Upward Slew Enable bit
  • 0 Slewing disabled for switching to a higher frequency
  • 1 Slewing enabled for switching to a higher frequency
DNEN1Downward Slew Enable bit
  • 0 Slewing disabled for switching to a lower frequency
  • 1 Slewing enabled for switching to a lower frequency
BUSY0Clock Switching Slewing Active Status bit
  • 0 Clock switch has reached its final value
  • 1 Clock frequency is being actively slewed to the new frequency

CLKSTATOscillator Clock Status Register

Address
0xBF801390
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
FieldBitsWhat it does
UPLLRDY8USB PLL (UPLL) Ready Status bit
  • 0 UPLL is not ready
  • 1 UPLL is ready
SPLLRDY7System PLL Ready Status bit
  • 0 SPLL is not ready
  • 1 SPLL is ready
LPRCRDY5Low-Power RC Oscillator Ready Status bit
  • 0 LPRC is disabled or not operating
  • 1 LPRC is stable and ready
SOSCRDY4Secondary Oscillator Ready Status bit
  • 0 Sosc is disabled or not operating
  • 1 Sosc is stable and ready
POSCRDY2Primary Oscillator Ready Status bit
  • 0 Posc is disabled or not operating
  • 1 Posc is stable and ready
FRCRDY0Fast RC Oscillator Ready Status bit
  • 0 FRC is disabled for not operating
  • 1 FRC is stable and ready