PIC32MK1024MCF064 MCPWM registers

The 51 registers of MCPWM (MCPWM), from 0xBF82A030, with their reset value and every field. The PIC32MK1024MCF064 has 1848 registers in 120 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

MCPWM MCPWM

PMTMRPrimary Master Time Base Timer Register

Address: 0xBF82A030
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
PMTMR	15:0

STPERSecondary Master Time Base Period Register

Address: 0xBF82A050
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
STPER	15:0

SMTMRSecondary Master Time Base Timer Register

Address: 0xBF82A070
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SMTMR	15:0

DTCOMP1Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A130
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON1PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A150
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP1PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A170
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR1PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A1B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP2Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A230
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON2PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A250
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP2PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A270
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR2PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A2B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP3Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A330
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON3PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A350
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP3PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A370
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR3PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A3B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP4Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A430
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON4PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A450
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP4PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A470
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR4PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A4B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP5Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A530
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON5PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A550
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP5PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A570
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR5PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A5B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP6Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A630
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON6PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A650
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP6PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A670
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR6PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A6B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP7Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A730
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON7PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A750
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP7PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A770
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR7PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A7B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP8Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A830
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON8PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A850
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP8PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A870
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR8PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A8B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP9Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82A930
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON9PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82A950
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP9PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82A970
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR9PWM Timer Register x (x = 1 through 12)

Address: 0xBF82A9B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP10Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82AA30
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON10PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82AA50
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP10PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82AA70
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR10PWM Timer Register x (x = 1 through 12)

Address: 0xBF82AAB0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP11Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82AB30
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON11PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82AB50
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP11PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82AB70
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR11PWM Timer Register x (x = 1 through 12)

Address: 0xBF82ABB0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0

DTCOMP12Dead Time Compensation Register x (x = 1 through 12)

Address: 0xBF82AC30
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
COMP	13:0

TRGCON12PWM Trigger Control Register x (x = 1 through 12)

Address: 0xBF82AC50
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
TRGDIV	15:12	Trigger x Output Divider bits `0` Trigger output for every trigger event `1` Trigger output for every 2nd trigger event `2` Trigger output for every 3rd trigger event `3` Trigger output for every 4th trigger event `4` Trigger output for every 5th trigger event `5` Trigger output for every 6th trigger event `6` Trigger output for every 7th trigger event `7` Trigger output for every 8th trigger event `8` Trigger output for every 9th trigger event `9` Trigger output for every 10th trigger event `10` Trigger output for every 11th trigger event `11` Trigger output for every 12th trigger event `12` Trigger output for every 13th trigger event `13` Trigger output for every 14th trigger event `14` Trigger output for every 15th trigger event `15` Trigger output for every 16th trigger event
TRGSEL	11:10	Trigger Cycle Selection for Dual Cycle PWM Cycles `0` When a trigger comparison match event occurs `1` When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM mode (PTDIR is 1) `2` When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM mode (PTDIR is 0) `3` Reserved
STRGSEL	9:8	Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles `0` When a secondary PWM trigger comparison match event occurs `1` When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM mode (PTDIR is 1) `2` When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle PWM mode (PTDIR is 0) `3` Reserved
DTM	7	Dual ADC Trigger Mode `0` Secondary trigger event is not combined with the primary trigger event for purposes of creating a combined ADC trigger `1` Secondary trigger event is combined with the primary trigger event for purposes of creating a combined ADC trigger
STRGIS	6	Secondary Trigger Interrupt Select `0` (When the DTM bit (TRGCONx) is clear (is 0)) TRIGx-based events for interrupts are selected / (When the DTM bit is set (= 1))the logical OR of both STRIGx and TRIGx based triggers for interrupts are selected. `1` Selects the Secondary Trigger Register (STRIGx) based events for interrupts

CAP12PWM Timer Capture Register x (x = 1 through 12)

Address: 0xBF82AC70
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CAP	15:0

PTMR12PWM Timer Register x (x = 1 through 12)

Address: 0xBF82ACB0
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
TMR	15:0