The 14 registers of PORTE (I/O port E), from 0xBF860400, with their reset value and every field. The PIC32MK1024MCF064 has 1848 registers in 120 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PORTE I/O port E
ANSELE
Address
0xBF860400
Reset
0x0000F000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
ANSE15
15
ANSE14
14
ANSE13
13
ANSE12
12
TRISE
Address
0xBF860410
Reset
0x0000F000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
TRISE15
15
TRISE14
14
TRISE13
13
TRISE12
12
PORTE
Address
0xBF860420
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
RE15
15
RE14
14
RE13
13
RE12
12
LATE
Address
0xBF860430
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
LATE15
15
LATE14
14
LATE13
13
LATE12
12
ODCE
Address
0xBF860440
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
ODCE15
15
ODCE14
14
ODCE13
13
ODCE12
12
CNPUE
Address
0xBF860450
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CNPUE15
15
CNPUE14
14
CNPUE13
13
CNPUE12
12
CNPDE
Address
0xBF860460
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
CNPDE15
15
CNPDE14
14
CNPDE13
13
CNPDE12
12
CNCONEChange Notice control for PORTx Register
Address
0xBF860470
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ON
15
Change Notice Control ON bit
0 CN is disabled
1 CN is enabled
EDGEDETECT
11
Change Notification Style bit
0 Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event).
1 Edge Style. Detect edge transitions (CNFx used for CN Event).
BETA