PIC32MK1024MCF064 SPI2 registers

The 5 registers of SPI2 (SPI 2), from 0xBF827200, with their reset value and every field. The PIC32MK1024MCF064 has 1848 registers in 120 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

SPI2 SPI 2

SPI2CONSPI Control Register

Address
0xBF827200
Reset
0x00000000
Access
read/write
Size
32-bit
22 fields
FieldBitsWhat it does
FRMSYNC30Frame Sync Pulse Direction Control on SSx pin bit
  • 0 Frame sync pulse output (Master mode)
  • 1 Frame sync pulse input (Slave mode)
FRMPOL29Frame Sync Polarity bit
  • 0 Frame pulse is active-low
  • 1 Frame pulse is active-high
MSSEN28Master Mode Slave Select Enable bit
  • 0 Slave select SPI support is disabled.
  • 1 Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit.
FRMSYPW27Frame Sync Pulse Width bit
  • 0 Frame sync pulse is one clock wide
  • 1 Frame sync pulse is one character wide
FRMCNT26:24Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in Framed mode.
  • 0 Generate a frame sync pulse on every data character
  • 1 Generate a frame sync pulse on every 2 data characters
  • 2 Generate a frame sync pulse on every 4 data characters
  • 3 Generate a frame sync pulse on every 8 data characters
  • 4 Generate a frame sync pulse on every 16 data characters
  • 5 Generate a frame sync pulse on every 32 data characters
  • 6 Reserved
  • 7 Reserved
MCLKSEL23Master Clock Enable bit
  • 0 PBCLK2 is used by the Baud Rate Generator
  • 1 REFCLKO1 is used by the Baud Rate Generator
SPIFE17Frame Sync Pulse Edge Select bit
  • 0 Frame synchronization pulse precedes the first bit clock
  • 1 Frame synchronization pulse coincides with the first bit clock
ENHBUF16Enhanced Buffer Enable bit
  • 0 Enhanced Buffer mode is disabled
  • 1 Enhanced Buffer mode is enabled
ON15SPI/I 2 S Module On bit
  • 0 SPI/I2S module is disabled
  • 1 SPI/I2S module is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue operation in Idle mode
  • 1 Discontinue operation when CPU enters in Idle mode
DISSDO12Disable SDOx pin bit
  • 0 SDOx pin is controlled by the module
  • 1 SDOx pin is not used by the module. Pin is controlled by associated PORT register
MODE321132/16-Bit Communication Select bits
  • 0 (AUDEN = 1) 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame / (AUDEN = 0)8-bit
  • 1 (AUDEN = 1) 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame / (AUDEN = 0)16-bit
  • 2 (AUDEN = 1) 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame / (AUDEN = 0)32-bit
  • 3 (AUDEN = 1) 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame / (AUDEN = 0)32-bit
MODE1610
SMP9SPI Data Input Sample Phase bit (master mode only)
  • 0 (Master mode) Input data sampled at middle of data output time / (Slave mode) value is ignored
  • 1 (Master mode) Input data sampled at end of data output time / (Slave mode) value is ignored
CKE8SPI Clock Edge Select bit
  • 0 Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
  • 1 Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
SSEN7Slave Select Enable bit
  • 0 SSx pin not used for Slave mode
  • 1 SSx pin used for Slave mode
CKP6Clock Polarity Select bit
  • 0 Idle state for clock is a low level; active state is a high level
  • 1 Idle state for clock is a high level; active state is a low level
MSTEN5Master Mode Enable bit
  • 0 Slave mode
  • 1 Master mode
DISSDI4Disable SDI bit
  • 0 SDI pin is controlled by the SPI module
  • 1 SDI pin is not used by the SPI module (pin is controlled by PORT function)
STXISEL3:2SPI Transmit Buffer Empty Interrupt Mode bits
  • 0 Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete
  • 1 Interrupt is generated when the buffer is completely empty
  • 2 Interrupt is generated when the buffer is empty by one-half or more
  • 3 Interrupt is generated when the buffer is not full (has one or more empty elements)
SRXISEL1:0SPI Receive Buffer Full Interrupt Mode bits
  • 0 Interrupt is generated when the last word in the receive buffer is read (i.e. buffer is empty)
  • 1 Interrupt is generated when the buffer is not empty
  • 2 Interrupt is generated when the buffer is full by one-half or more
  • 3 Interrupt is generated when the buffer is full
FRMEN31Framed SPI Support bit
  • 0 Framed SPI support is disabled
  • 1 Framed SPI support is enabled (SSx pin used as FSYNC input/output)

SPI2STATSPI Status Register

Address
0xBF827210
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
RXBUFELM28:24
TXBUFELM20:16
FRMERR12SPI Frame Error status bit
  • 0 No Frame error detected
  • 1 Frame error detected
SPIBUSY11SPI Activity Status bit
  • 0 SPI peripheral is currently idle
  • 1 SPI peripheral is currently busy with some transactions
SPITUR8Transmit Under Run bit
  • 0 Transmit buffer has no underrun condition
  • 1 Transmit buffer has encountered an underrun condition
SRMT7Shift Register Empty bit
  • 0 When SPI module shift register is not empty
  • 1 When SPI module shift register is empty
SPIROV6Receive Overflow Flag bit
  • 0 No overflow has occurred
  • 1 A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register.
SPIRBE5RX FIFO Empty bit (valid only when ENHBUF = 1)
  • 0 RX FIFO is not empty (CRPTR ? SWPTR)
  • 1 RX FIFO is empty (CRPTR = SWPTR)
SPITBE3SPI Transmit Buffer Empty Status bit
  • 0 Transmit buffer
  • 1 Transmit buffer
SPITBF1SPI Transmit Buffer Full Status bit
  • 0 Transmit buffer is not full
  • 1 Transmit not yet started
SPIRBF0SPI Receive Buffer Full Status bit
  • 0 Receive buffer
  • 1 Receive buffer

SPI2BUF

Address
0xBF827220
Reset
0x00000000
Access
read/write
Size
32-bit

SPI2BRG

Address
0xBF827230
Reset
0x00000000
Access
read/write
Size
32-bit

SPI2CON2SPI Control Register 2

Address
0xBF827240
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
SPISGNEXT15Sign Extend Read Data from the RX FIFO bit
  • 0 Data from RX FIFO is not sign extened
  • 1 Data from RX FIFO is sign extended
FRMERREN12Enable Interrupt Events via FRMERR bit
  • 0 Frame Error does not generate error events
  • 1 Frame Error overflow generates error events
SPIROVEN11Enable Interrupt Events via SPIROV bit
  • 0 Receive overflow does not generate error events
  • 1 Receive overflow generates error events
SPITUREN10Enable Interrupt Events via SPITUR bit
  • 0 Transmit Underrun Does Not Generates Error Events
  • 1 Transmit Underrun Generates Error Events
IGNROV9Ignore Receive Overflow bit
  • 0 A ROV is a critical error which stop SPI operation
  • 1 A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data
IGNTUR8Ignore Transmit Underrun bit
  • 0 A TUR is a critical error which stop SPI operation
  • 1 A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
AUDEN7Enable Audio CODEC Support bit
  • 0 Audio protocol disabled
  • 1 Audio protocol enabled
AUDMONO3Transmit Audio Data Format bit
  • 0 Audio data is stereo
  • 1 Audio data is mono (Each data word is transmitted on both left and right channels)
AUDMOD1:0Audio Protocol Mode bit
  • 0 I2S mode
  • 1 Left Justified mode
  • 2 Right Justified mode
  • 3 PCM/DSP mode