PIC32MK1024MCF100 ADC registers

The 108 registers of ADC (Analog-to-digital converter), from 0xBF887000, with their reset value and every field. The PIC32MK1024MCF100 has 1917 registers in 121 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

ADC Analog-to-digital converter

ADCCON1ADC Control Register 1

Address
0xBF887000
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
TRBERR30Turbo Channel Error Status bit
  • 0 Turbo channel error did not occur
  • 1 An error occurred while setting the Turbo channel and Turbo channel function to be disabled regardless of the TRBEN bit being set to 1.
TRBMST29:27Turbo Master ADCx bits
  • 0 ADC0
  • 1 ADC1
  • 2 ADC2
  • 3 ADC3
  • 4 ADC4
  • 5 ADC5
  • 6 Reserved
  • 7 Reserved
TRBSLV26:24Turbo Slave ADCx bits
  • 0 ADC0
  • 1 ADC1
  • 2 ADC2
  • 3 ADC3
  • 4 ADC4
  • 5 ADC5
  • 6 Reserved
  • 7 Reserved
FRACT23Fractional Data Output Format bit
  • 0 Integer
  • 1 Fractional
SELRES22:21Shared ADC7 Resolution bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits (default)
STRGSRC20:16Scan Trigger Source Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary PWM time base (Motor Control only)
  • 9 Secondary PWM time base (Motor Control only)
  • 10 PWM Generator 1 trigger (Motor Control only)
  • 11 PWM Generator 2 trigger (Motor Control only)
  • 12 PWM Generator 3 trigger (Motor Control only)
  • 13 PWM Generator 4 trigger (Motor Control only)
  • 14 PWM Generator 5 trigger (Motor Control only)
  • 15 PWM Generator 6 trigger (Motor Control only)
  • 16 Output Compare 1 period end
  • 17 Output Compare 2 period end
  • 18 Output Compare 3 period end
  • 19 Output Compare 4 period end
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control only)
  • 25 PWM Generator 2 Current-Limit (Motor Control only)
  • 26 PWM Generator 3 Current-Limit (Motor Control only)
  • 27 PWM Generator 4 Current-Limit (Motor Control only)
  • 28 PWM Generator 5 Current-Limit (Motor Control only)
  • 29 PWM Generator 6 Current-Limit (Motor Control only)
  • 30 Reserved
  • 31 Reserved
ON15ADC Module Enable bit
  • 0 ADC module is disabled
  • 1 ADC module is enabled
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
AICPMPEN12Analog Input Charge Pump Enable bit
  • 0 Analog input charge pump is disabled (default)
  • 1 Analog input charge pump is enabled
CVDEN11Capacitive Voltage Division Enable bit
  • 0 CVD operation is disabled
  • 1 CVD operation is enabled
FSSCLKEN10Fast Synchronous System Clock to ADC Control Clock bit
  • 0 Fast synchronous system clock to ADC control clock is disabled
  • 1 Fast synchronous system clock to ADC control clock is enabled
FSPBCLKEN9Fast Synchronous Peripheral Clock to ADC Control Clock bit
  • 0 Fast synchronous peripheral clock to ADC control clock is disabled
  • 1 Fast synchronous peripheral clock to ADC control clock is enabled
IRQVS6:4Interrupt Vector Shift bits
  • 0 Shift x left 0 bit position
  • 1 Shift x left 1 bit position
  • 2 Shift x left 2 bit position
  • 3 Shift x left 3 bit position
  • 4 Shift x left 4 bit position
  • 5 Shift x left 5 bit position
  • 6 Shift x left 6 bit position
  • 7 Shift x left 7 bit position
STRGLVL3Scan Trigger High Level/Positive Edge Sensitivity bit
  • 0 Scan trigger is positive edge sensitive. Once STRIG mode is selected only a single scan trigger will be generated which will complete the scan of all selected analog inputs. (TRGSRCx in the ADCTRGx register)
  • 1 Scan trigger is high level sensitive. Once STRIG mode is selected the scan trigger will continue for all selected analog inputs
DMABL2:0DMA to System RAM Buffer Length Size bits
  • 0 Allocates 1 location in system memory to each analog input
  • 1 Allocates 2 locations in system memory to each analog input
  • 2 Allocates 4 locations in system memory to each analog input
  • 3 Allocates 8 locations in system memory to each analog input
  • 4 Allocates 16 locations in system memory to each analog input
  • 5 Allocates 32 locations in system memory to each analog input
  • 6 Allocates 64 locations in system memory to each analog input
  • 7 Allocates 128 locations in system memory to each analog input
TRBEN31Turbo Channel Enable bit
  • 0 Disable the Turbo channel
  • 1 Enable the Turbo channel

ADCCON2ADC Control Register 2

Address
0xBF887010
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
REFFLT30Band Gap/ Vref / AVdd BOR Fault Status bit
  • 0 Band gap and Vref voltage are working properly
  • 1 Fault in band gap or the Vref voltage while the ON bit (ADCCON1) was set. Most likely a band gap or Vref fault will be caused by a BOR of the analog Vdd supply.
EOSRDY29End of Scan Interrupt Status bit
  • 0 Scanning has not completed
  • 1 All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in the ADCCSS1 and ADCCSS2 registers) have completed scanning
CVDCPL28:26Capacitor Voltage Divider Setting bits
  • 0 0 * 2.5 pF = 0 pF
  • 1 1 * 2.5 pF = 2.5 pF
  • 2 2 * 2.5 pF = 5 pF
  • 3 3 * 2.5 pF = 7.5 pF
  • 4 4 * 2.5 pF = 10 pF
  • 5 5 * 2.5 pF = 12.5 pF
  • 6 6 * 2.5 pF = 15 pF
  • 7 7 * 2.5 pF = 17.5 pF
SAMC25:16Sample Time for the Shared ADC (ADC7) bits
  • 0 2 Tad
  • 1 3 Tad
  • 1023 1025 Tad
BGVRIEN15Band Gap/ Vref Voltage Ready Interrupt Enable bit
  • 0 No interrupt is generated when the BGVRRDY bit is set
  • 1 Interrupt will be generated when the BGVRDDY bit is set
REFFLTIEN14Band Gap/ Vref Voltage Fault Interrupt Enable bit
  • 0 No interrupt is generated when the REFFLT bit is set
  • 1 Interrupt will be generated when the REFFLT bit is set
EOSIEN13End of Scan Interrupt Enable bit
  • 0 No interrupt is generated when the EOSRDY bit is set
  • 1 Interrupt will be generated when EOSRDY bit is set
ADCEIOVR12Early Interrupt Request Override bit
  • 0 Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1 and ADCEIEN2 registers
  • 1 Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1 and ADCGIRQEN2 registers
ADCEIS10:8Shared ADC Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC module clock prior to end of conversion
  • 1 The data ready interrupt is generated 2 ADC module clocks prior to end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to end of conversion
ADCDIV6:0Shared ADC Clock Divider bits
  • 0 Reserved
  • 1 2 * Tq = Tad
  • 2 4 * Tq = Tad
  • 3 6 * Tq = Tad
  • 127 254 * Tq = Tad
BGVRRDY31Band Gap Voltage/ADC Reference Voltage Status bit
  • 0 Either or both band gap voltage and ADC reference voltages (Vref) are not ready
  • 1 Both band gap voltage and ADC reference voltages (Vref) are ready

ADCCON3ADC Control Register 3

Address
0xBF887020
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
CONCLKDIV29:24Analog-to-Digital Control Clock Divider bits
  • 0 Tclk = Tq
  • 1 2 * Tclk = Tq
  • 2 4 * Tclk = Tq
  • 3 6 * Tclk = Tq
  • 63 126 * Tclk = Tq
DIGEN723Shared ADC (ADC7) Digital Enable bit
  • 0 ADC7 is digital disabled
  • 1 ADC7 is digital enabled
DIGEN521ADC5 Digital Enable bit
  • 0 ADC5 is digital disabled (power-saving mode)
  • 1 ADC5 is digital enabled (required for active operation)
DIGEN420ADC4 Digital Enable bit
  • 0 ADC4 is digital disabled (power-saving mode)
  • 1 ADC4 is digital enabled (required for active operation)
DIGEN319ADC3 Digital Enable bit
  • 0 ADC3 is digital disabled (power-saving mode)
  • 1 ADC3 is digital enabled (required for active operation)
DIGEN218ADC2 Digital Enable bit
  • 0 ADC2 is digital disabled (power-saving mode)
  • 1 ADC2 is digital enabled (required for active operation)
DIGEN117ADC1 Digital Enable bit
  • 0 ADC1 is digital disabled (power-saving mode)
  • 1 ADC1 is digital enabled (required for active operation)
DIGEN016ADC0 Digital Enable bit
  • 0 ADC0 is digital disabled (power-saving mode)
  • 1 ADC0 is digital enabled (required for active operation)
VREFSEL15:13Voltage Reference Input Selection bits
  • 0 AVDD and AVSS
  • 1 External VREFH and AVSS
  • 2 AVDD and External VREFL
  • 3 External VREFH and External VREFL
  • 4 Reserved
  • 5 Reserved
  • 6 Reserved
  • 7 Reserved
TRGSUSP12Trigger Suspend bit
  • 0 Triggers are not blocked
  • 1 Triggers are blocked from starting a new analog-to-digital conversion
UPDIEN11Update Ready Interrupt Enable bit
  • 0 No interrupt is generated
  • 1 Interrupt will be generated when the UPDRDY bit is set by hardware
UPDRDY10ADC Update Ready Status bit
  • 0 ADC SFRs cannot be updated
  • 1 ADC SFRs can be updated
SAMP9Shared ADC7 Analog Input Sampling Enable bit
  • 0 The ADC S&H amplifier is holding
  • 1 The ADC S&H amplifier is sampling
RQCNVRT8Individual ADC Input Conversion Request bit
  • 0 Do not trigger the conversion
  • 1 Trigger the conversion of the selected ADC input as specified by the ADINSEL bits
GLSWTRG7Global Level Software Trigger bit
  • 0 Do not trigger an analog-to-digital conversion
  • 1 Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal
GSWTRG6Global Software Trigger bit
  • 1 Trigger conversion for ADC inputs that have selected the GSWTRG bit as either through the associated TRGSRC bits in the ADCTRGx registers or through the STRGSRC<4:0> bits in the ADCCON1 register the trigger signal
ADINSEL5:0Analog Input Select bits
  • 0 AN0
  • 27 AN27
  • 28 Reserved
  • 32 Reserved
  • 33 AN33
  • 41 AN41
  • 42 Reserved
  • 44 Reserved
  • 45 AN45
  • 49 AN49
  • 50 IVref 1.2V (internal AN50)
  • 51 Reserved
  • 52 Vbat/2 (internal AN52)
  • 53 CTMU Temperature Sensor (internal AN53)
  • 54 Reserved
  • 63 Reserved
ADCSEL31:30Analog-to-Digital Clock Source bits
  • 0 PBCLK5
  • 1 FRC
  • 2 REFCLK3
  • 3 SYSCLK

ADCTRGMODEADC Triggering Mode for Dedicated ADC Register

Address
0xBF887030
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
SH5ALT27:26ADC5 Analog Input Select bit
  • 0 AN5
  • 1 AN2
  • 2 AN6
  • 3 AN25
SH4ALT25:24ADC4 Analog Input Select bit
  • 0 AN4
  • 1 AN1
  • 2 AN9
  • 3 AN0
SH3ALT23:22ADC3 Analog Input Select bit
  • 0 AN3
  • 1 AN0
  • 2 AN8
  • 3 AN26
SH2ALT21:20ADC2 Analog Input Select bit
  • 0 AN2
  • 1 AN5
  • 2 AN6
  • 3 AN25
SH1ALT19:18ADC1 Analog Input Select bit
  • 0 AN1
  • 1 AN4
  • 2 AN7
  • 3 AN0
SH0ALT17:16ADC0 Analog Input Select bit
  • 0 AN0
  • 1 AN3
  • 2 AN5
  • 3 AN24
STRGEN513ADC5 Presynchronized Triggers bit
  • 0 ADC5 does not use presynchronized triggers
  • 1 ADC5 uses presynchronized triggers
STRGEN412ADC4 Presynchronized Triggers bit
  • 0 ADC4 does not use presynchronized triggers
  • 1 ADC4 uses presynchronized triggers
STRGEN311ADC3 Presynchronized Triggers bit
  • 0 ADC3 does not use presynchronized triggers
  • 1 ADC3 uses presynchronized triggers
STRGEN210ADC2 Presynchronized Triggers bit
  • 0 ADC2 does not use presynchronized triggers
  • 1 ADC2 uses presynchronized triggers
STRGEN19ADC1 Presynchronized Triggers bit
  • 0 ADC1 does not use presynchronized triggers
  • 1 ADC1 uses presynchronized triggers
STRGEN08ADC0 Presynchronized Triggers bit
  • 0 ADC0 does not use presynchronized triggers
  • 1 ADC0 uses presynchronized triggers
SSAMPEN55ADC5 Synchronous Sampling bit
  • 0 ADC5 does not use synchronous sampling
  • 1 ADC5 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN44ADC4 Synchronous Sampling bit
  • 0 ADC4 does not use synchronous sampling
  • 1 ADC4 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN33ADC3 Synchronous Sampling bit
  • 0 ADC3 does not use synchronous sampling
  • 1 ADC3 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN22ADC2Synchronous Sampling bit
  • 0 ADC2 does not use synchronous sampling
  • 1 ADC2 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN11ADC1 Synchronous Sampling bit
  • 0 ADC1 does not use synchronous sampling
  • 1 ADC1 uses synchronous sampling for the first sample after being idle or disabled
SSAMPEN00ADC0 Synchronous Sampling bit
  • 0 ADC0 does not use synchronous sampling
  • 1 ADC0 uses synchronous sampling for the first sample after being idle or disabled

ADCIMCON1ADC Input Mode Control Register 1

Address
0xBF887040
Reset
0x00000000
Access
read/write
Size
32-bit
32 fields
FieldBitsWhat it does
SIGN1530AN15 Signed Data Mode bit
  • 0 AN15 is using Unsigned Data mode
  • 1 AN15 is using Signed Data mode
DIFF1429AN14 Mode bit
  • 0 AN14 is using Single-ended mode
  • 1 Selects AN14 differential input pair as AN14+ and AN1-
SIGN1428AN14 Signed Data Mode bit
  • 0 AN14 is using Unsigned Data mode
  • 1 AN14 is using Signed Data mode
DIFF1327AN13 Mode bit
  • 0 AN13 is using Single-ended mode
  • 1 Selects AN13 differential input pair as AN13+ and AN1-
SIGN1326AN13 Signed Data Mode bit
  • 0 AN13 is using Unsigned Data mode
  • 1 AN13 is using Signed Data mode
DIFF1225AN12 Mode bit
  • 0 AN12 is using Single-ended mode
  • 1 Selects AN12 differential input pair as AN12+ and AN1-
SIGN1224AN12 Signed Data Mode bit
  • 0 AN12 is using Unsigned Data mode
  • 1 AN12 is using Signed Data mode
DIFF1123AN11 Mode bit
  • 0 AN11 is using Single-ended mode
  • 1 Selects AN11 differential input pair as AN11+ and AN1-
SIGN1122AN11 Signed Data Mode bit
  • 0 AN11 is using Unsigned Data mode
  • 1 AN11 is using Signed Data mode
DIFF1021AN10 Mode bit
  • 0 AN10 is using Single-ended mode
  • 1 Selects AN10 differential input pair as AN10+ and AN1-
SIGN1020AN10 Signed Data Mode bit
  • 0 AN10 is using Unsigned Data mode
  • 1 AN10 is using Signed Data mode
DIFF919AN9 Mode bit
  • 0 AN9 is using Single-ended mode
  • 1 Selects AN9 differential input pair as AN9+ and AN1-
SIGN918AN9 Signed Data Mode bit
  • 0 AN9 is using Unsigned Data mode
  • 1 AN9 is using Signed Data mode
DIFF817AN 8 Mode bit
  • 0 AN8 is using Single-ended mode
  • 1 Selects AN8 differential input pair as AN8+ and AN1-
SIGN816AN8 Signed Data Mode bit
  • 0 AN8 is using Unsigned Data mode
  • 1 AN8 is using Signed Data mode
DIFF715AN7 Mode bit
  • 0 AN7 is using Single-ended mode
  • 1 Selects AN7 differential input pair as AN7+ and AN1-
SIGN714AN7 Signed Data Mode bit
  • 0 AN7 is using Unsigned Data mode
  • 1 AN7 is using Signed Data mode
DIFF613AN6 Mode bit
  • 0 AN6 is using Single-ended mode
  • 1 Selects AN6 differential input pair as AN6+ and AN1-
SIGN612AN6 Signed Data Mode bit
  • 0 AN6 is using Unsigned Data mode
  • 1 AN6 is using Signed Data mode
DIFF511AN5 Mode bit
  • 0 AN5 is using Single-ended mode
  • 1 Selects AN5 differential input pair as AN5+ and AN11-
SIGN510AN5 Signed Data Mode bit
  • 0 AN5 is using Unsigned Data mode
  • 1 AN5 is using Signed Data mode
DIFF49AN4 Mode bit
  • 0 AN4 is using Single-ended mode
  • 1 Selects AN4 differential input pair as AN4+ and AN10-
SIGN48AN4 Signed Data Mode bit
  • 0 AN4 is using Unsigned Data mode
  • 1 AN4 is using Signed Data mode
DIFF37AN3 Mode bit
  • 0 AN3 is using Single-ended mode
  • 1 Selects AN3 differential input pair as AN3+ and AN27-
SIGN36AN3 Signed Data Mode bit
  • 0 AN3 is using Unsigned Data mode
  • 1 AN3 is using Signed Data mode
DIFF25AN2 Mode bit
  • 0 AN2 is using Single-ended mode
  • 1 Selects AN2 differential input pair as AN2+ and AN8-
SIGN24AN2 Signed Data Mode bit
  • 0 AN2 is using Unsigned Data mode
  • 1 AN2 is using Signed Data mode
DIFF13AN1 Mode bit
  • 0 AN1 is using Single-ended mode
  • 1 Selects AN1 differential input pair as AN1+ and AN7-
SIGN12AN1 Signed Data Mode bit
  • 0 AN1 is using Unsigned Data mode
  • 1 AN1 is using Signed Data mode
DIFF01AN0 Mode bit
  • 0 AN0 is using Single-ended mode
  • 1 Selects AN0 differential input pair as AN0+ and AN6-
SIGN00AN0 Signed Data Mode bit
  • 0 AN0 is using Unsigned Data mode
  • 1 AN0 is using Signed Data mode
DIFF1531AN15 Mode bit
  • 0 AN15 is using Single-ended mode
  • 1 Selects AN15 differential input pair as AN15+ and AN1-

ADCIMCON2ADC Input Mode Control Register 2

Address
0xBF887050
Reset
0x00000000
Access
read/write
Size
32-bit
24 fields
FieldBitsWhat it does
DIFF2723AN27 Mode bit
  • 0 AN27 is using Single-ended mode
  • 1 Selects AN27 differential pair input as AN27+ and AN1-
SIGN2722AN27 Signed Data Mode bit
  • 0 AN27 is using Unsigned Data mode
  • 1 AN27 is using Signed Data mode
DIFF2621AN26 Mode bit
  • 0 AN26 is using Single-ended mode
  • 1 Selects AN26 differential pair input as AN26+ and AN1-
SIGN2620AN26 Signed Data Mode bit
  • 0 AN26 is using Unsigned Data mode
  • 1 AN26 is using Signed Data mode
DIFF2519AN25 Mode bit
  • 0 AN25 is using Single-ended mode
  • 1 Selects AN25 differential pair input as AN25+ and AN1-
SIGN2518AN25 Signed Data Mode bit
  • 0 AN25 is using Unsigned Data mode
  • 1 AN25 is using Signed Data mode
DIFF2417AN24 Mode bit
  • 0 AN24 is using Single-ended mode
  • 1 Selects AN24 differential pair input as AN24+ and AN1-
SIGN2416AN24 Signed Data Mode bit
  • 0 AN24 is using Unsigned Data mode
  • 1 AN24 is using Signed Data mode
DIFF2315AN23 Mode bit
  • 0 AN23 is using Single-ended mode
  • 1 Selects AN23 differential pair input as AN23+ and AN1-
SIGN2314AN23 Signed Data Mode bit
  • 0 AN23 is using Unsigned Data mode
  • 1 AN23 is using Signed Data mode
DIFF2213AN22 Mode bit
  • 0 AN22 is using Single-ended mode
  • 1 Selects AN22 differential pair input as AN22+ and AN1-
SIGN2212AN22 Signed Data Mode bit
  • 0 AN22 is using Unsigned Data mode
  • 1 AN22 is using Signed Data mode
DIFF2111AN21 Mode bit
  • 0 AN21 is using Single-ended mode
  • 1 Selects AN21 differential pair input as AN21+ and AN1-
SIGN2110AN21 Signed Data Mode bit
  • 0 AN21 is using Unsigned Data mode
  • 1 AN21 is using Signed Data mode
DIFF209AN20 Mode bit
  • 0 AN20 is using Single-ended mode
  • 1 Selects AN20 differential pair input as AN20+ and AN1-
SIGN208AN20 Signed Data Mode bit
  • 0 AN20 is using Unsigned Data mode
  • 1 AN20 is using Signed Data mode
DIFF197AN19 Mode bit
  • 0 AN19 is using Single-ended mode
  • 1 Selects AN19 differential pair input as AN19+ and AN1-
SIGN196AN19 Signed Data Mode bit
  • 0 AN19 is using Unsigned Data mode
  • 1 AN19 is using Signed Data mode
DIFF185AN18 Mode bit
  • 0 AN18 is using Single-ended mode
  • 1 Selects AN18 differential pair input as AN18+ and AN1-
SIGN184AN18 Signed Data Mode bit
  • 0 AN18 is using Unsigned Data mode
  • 1 AN18 is using Signed Data mode
DIFF173AN17 Mode bit
  • 0 AN17 is using Single-ended mode
  • 1 Selects AN17 differential pair input as AN17+ and AN1-
SIGN172AN17 Signed Data Mode bit
  • 0 AN17 is using Unsigned Data mode
  • 1 AN17 is using Signed Data mode
DIFF161AN16 Mode bit
  • 0 AN16 is using Single-ended mode
  • 1 Selects AN16 differential pair input as AN16+ and AN1-
SIGN160AN16 Signed Data Mode bit
  • 0 AN16 is using Unsigned Data mode
  • 1 AN16 is using Signed Data mode

ADCIMCON3ADC Input Mode Control Register 3

Address
0xBF887060
Reset
0x00000000
Access
read/write
Size
32-bit
24 fields
FieldBitsWhat it does
SIGN4730AN47 Signed Data Mode bit
  • 0 AN41 is using Unsigned Data mode
  • 1 AN41 is using Signed Data mode
DIFF4629AN46 Mode bit
  • 0 AN41 is using Single-ended mode
  • 1 Selects AN46 differential input pair as AN46+ and AN1-
SIGN4628AN45 Signed Data Mode bit
  • 0 AN46 is using Unsigned Data mode
  • 0 AN45 is using Signed Data mode
  • 0 AN45 is using Unsigned Data mode
  • 1 AN46 is using Signed Data mode
DIFF4527AN45 Mode bit
  • 0 AN45 is using Single-ended mode
  • 1 Selects AN45 differential input pair as AN45+ and AN1-
SIGN4526AN45 Signed Data Mode bit
  • 0 AN45 is using Unsigned Data mode
  • 1 AN45 is using Signed Data mode
DIFF4119AN41 Mode bit
  • 0 AN41 is using Single-ended mode
  • 1 Selects AN41 differential input pair as AN41+ and AN1-
SIGN4118AN41 Signed Data Mode bit
  • 0 AN41 is using Unsigned Data mode
  • 1 AN41 is using Signed Data mode
DIFF4017AN40 Mode bit
  • 0 AN40 is using Single-ended mode
  • 1 Selects AN40 differential input pair as AN40+ and AN1-
SIGN4016AN40 Signed Data Mode bit
  • 0 AN40 is using Unsigned Data mode
  • 1 AN40 is using Signed Data mode
DIFF3915AN39 Mode bit
  • 0 AN39 is using Single-ended mode
  • 1 Selects AN39 differential input pair as AN39+ and AN1-
SIGN3914AN39 Signed Data Mode bit
  • 0 AN39 is using Unsigned Data mode
  • 1 AN39 is using Signed Data mode
DIFF3813AN38 Mode bit
  • 0 AN38 is using Single-ended mode
  • 1 Selects AN38 differential input pair as AN38+ and AN1-
SIGN3812AN38 Signed Data Mode bit
  • 0 AN38 is using Unsigned Data mode
  • 1 AN38 is using Signed Data mode
DIFF3711AN37 Mode bit
  • 0 AN37 is using Single-ended mode
  • 1 Selects AN37 differential input pair as AN37+ and AN1-
SIGN3710AN37 Signed Data Mode bit
  • 0 AN37 is using Unsigned Data mode
  • 1 AN37 is using Signed Data mode
DIFF369AN36 Mode bit
  • 0 AN36 is using Single-ended mode
  • 1 Selects AN36 differential input pair as AN36+ and AN1-
SIGN368AN36 Signed Data Mode bit
  • 0 AN36 is using Unsigned Data mode
  • 1 AN36 is using Signed Data mode
DIFF357AN35 Mode bit
  • 0 AN35 is using Single-ended mode
  • 1 Selects AN35 differential input pair as AN35+ and AN1-
SIGN356AN35 Signed Data Mode bit
  • 0 AN35 is using Unsigned Data mode
  • 1 AN35 is using Signed Data mode
DIFF345AN34 Mode bit
  • 0 AN34 is using Single-ended mode
  • 1 Selects AN34 differential input pair as AN34+ and AN1-
SIGN344AN34 Signed Data Mode bit
  • 0 AN34 is using Unsigned Data mode
  • 1 AN34 is using Signed Data mode
DIFF333AN33 Mode bit
  • 0 AN33 is using Single-ended mode
  • 1 Selects AN33 differential input pair as AN33+ and AN1-
SIGN332AN33 Signed Data Mode bit
  • 0 AN33 is using Unsigned Data mode
  • 1 AN33 is using Signed Data mode
DIFF4731AN47 Mode bit
  • 0 AN47 is using Single-ended mode
  • 1 Selects AN47 differential input pair as AN47+ and AN1-

ADCIMCON4ADC Input Mode Control Register 4

Address
0xBF887070
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
DIFF493AN49 Mode bit
  • 0 AN49 is using Single-ended mode
  • 1 Selects AN49 differential input pair as AN49+ and AN1-
SIGN492AN41 Signed Data Mode bit
  • 0 AN49 is using Unsigned Data mode
  • 1 AN49 is using Signed Data mode
DIFF481AN48 Mode bit
  • 0 AN48 is using Single-ended mode
  • 1 Selects AN40 differential input pair as AN48+ and AN1-
SIGN480AN48 Signed Data Mode bit
  • 0 AN48 is using Unsigned Data mode
  • 1 AN48 is using Signed Data mode

ADCGIRQEN1ADC Global Interrupt Enable Register 1

Address
0xBF887080
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
AGIEN2727ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2626ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2525ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2424ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2323ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2222ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2121ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN2020ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1919ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1818ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1717ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1616ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1515ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1414ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1313ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1212ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1111ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN1010ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN99ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN88ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN77ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN66ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN55ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN44ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN33ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN22ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN11ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN00ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)

ADCGIRQEN2ADC Global Interrupt Enable Register 2

Address
0xBF887090
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
AGIEN5321ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN5220ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN5119ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN5018ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN4917ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN4816ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN4715ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN4614ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN4513ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN419ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN408ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN397ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN386ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN375ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN364ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN353ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN342ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN331ADC Global Interrupt Enable bit
  • 0 Interrupts are disabled
  • 1 Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
AGIEN320

ADCCSS1ADC Common Scan Select Register 1

Address
0xBF8870A0
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
CSS2727Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2626Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2525Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2424Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2323Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2222Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2121Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS2020Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1919Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1818Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1717Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1616Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1515Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1414Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1313Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1212Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1111Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS1010Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS99Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS88Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS77Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS66Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS55Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS44Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS33Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS22Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS11Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS00Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)

ADCCSS2ADC Common Scan Select Register 2

Address
0xBF8870B0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
CSS5321Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS5220Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS5119
CSS5018Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS4917Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS4816Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS4715Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS4614Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS4513Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS419Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS408Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS397Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS386Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS375Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS364Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS353Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS342Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)
CSS331Analog Common Scan Select bits
  • 0 Skip ANx for input scan
  • 1 Select ANx for input scan (i.e.ANx = CSSx and scan is sequential starting with the lowest to highest enabled CSSx analog input pin)

ADCDSTAT1ADC Data Ready Status Register 1

Address
0xBF8870C0
Reset
0x00000000
Access
read only
Size
32-bit
28 fields
FieldBitsWhat it does
ARDY2727Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY2626Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY2525Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY2424Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY2323Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY2222Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY2121Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY2020Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1919Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1818Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1717Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1616Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1515Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1414Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1313Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1212Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1111Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY1010Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY99Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY88Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY77Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY66Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY55Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY44Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY33Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY22Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY11Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY00Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register

ADCDSTAT2ADC Data Ready Status Register 2

Address
0xBF8870D0
Reset
0x00000000
Access
read only
Size
32-bit
18 fields
FieldBitsWhat it does
ARDY5321Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY5220Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY5119Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY5018Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY4917Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY4816Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY4715Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY4614Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY4513Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY419Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY408Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY397Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY386Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY375Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY364Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY353Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY342Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register
ARDY331Conversion Data Ready for Corresponding Analog Input Ready bits
  • 0 This bit is cleared when the associated data register is read
  • 1 This bit is set when converted data is ready in the data register

ADCCMPEN1ADC Digital Comparator 'x' Enable Register ('x' = 1 through 4)

Address
0xBF8870E0
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
CMPE2727
CMPE2626
CMPE2525
CMPE2424
CMPE2323
CMPE2222
CMPE2121
CMPE2020
CMPE1919
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP1ADC Digital Comparator 'x' Limit Value Register ('x' = 1 through 4)

Address
0xBF8870F0
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCCMPEN2ADC Digital Comparator 'x' Enable Register ('x' = 1 through 4)

Address
0xBF887100
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
CMPE2727
CMPE2626
CMPE2525
CMPE2424
CMPE2323
CMPE2222
CMPE2121
CMPE2020
CMPE1919
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP2ADC Digital Comparator 'x' Limit Value Register ('x' = 1 through 4)

Address
0xBF887110
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCCMPEN3ADC Digital Comparator 'x' Enable Register ('x' = 1 through 4)

Address
0xBF887120
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
CMPE2727
CMPE2626
CMPE2525
CMPE2424
CMPE2323
CMPE2222
CMPE2121
CMPE2020
CMPE1919
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP3ADC Digital Comparator 'x' Limit Value Register ('x' = 1 through 4)

Address
0xBF887130
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCCMPEN4ADC Digital Comparator 'x' Enable Register ('x' = 1 through 4)

Address
0xBF887140
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
CMPE2727
CMPE2626
CMPE2525
CMPE2424
CMPE2323
CMPE2222
CMPE2121
CMPE2020
CMPE1919
CMPE1818
CMPE1717
CMPE1616
CMPE1515
CMPE1414
CMPE1313
CMPE1212
CMPE1111
CMPE1010
CMPE99
CMPE88
CMPE77
CMPE66
CMPE55
CMPE44
CMPE33
CMPE22
CMPE11
CMPE00

ADCCMP4ADC Digital Comparator 'x' Limit Value Register ('x' = 1 through 4)

Address
0xBF887150
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DCMPLO15:0
DCMPHI31:16

ADCFLTR1ADC Digital Filter 'x' Register ('x' = 1 through 6)

Address
0xBF8871A0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 4 samples (shift sum 1 bit to right output data is 13 bits)
  • 0 2 samples (2 samples to be averaged)
  • 1 16 samples (shift sum 2 bits to right output data is 14 bits)
  • 1 4 samples (4 samples to be averaged)
  • 2 64 samples (shift sum 3 bits to right output data is 15 bits)
  • 2 8 samples (8 samples to be averaged)
  • 3 256 samples (shift sum 4 bits to right output data is 16 bits)
  • 3 16 samples (16 samples to be averaged)
  • 4 2 samples (shift sum 0 bits to right output data is in 12.1 format)
  • 4 32 samples (32 samples to be averaged)
  • 5 8 samples (shift sum 1 bit to right output data is in 13.1 format)
  • 5 64 samples (64 samples to be averaged)
  • 6 32 samples (shift sum 2 bits to right output data is in 14.1 format)
  • 6 128 samples (128 samples to be averaged)
  • 7 128 samples (shift sum 3 bits to right output data is in 15.1 format)
  • 7 256 samples (256 samples to be averaged)
AFGIEN25Digital Filter 'x' Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter 'x' Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 ADC0 Module
  • 1 ADC1 Module
  • 2 ADC2 Module
  • 3 ADC3 Module
  • 4 ADC4 Module
  • 5 ADC5 Module
  • 19 AN19 input
  • 20 AN20 input
  • 21 AN21 input
  • 22 AN22 input
  • 22 AN6 input
  • 23 AN23 input
  • 24 AN24 input
  • 25 AN25 input
  • 26 AN26 input
  • 27 AN27 input
  • 28 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter 'x' Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCFLTR2ADC Digital Filter 'x' Register ('x' = 1 through 6)

Address
0xBF8871B0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 4 samples (shift sum 1 bit to right output data is 13 bits)
  • 0 2 samples (2 samples to be averaged)
  • 1 16 samples (shift sum 2 bits to right output data is 14 bits)
  • 1 4 samples (4 samples to be averaged)
  • 2 64 samples (shift sum 3 bits to right output data is 15 bits)
  • 2 8 samples (8 samples to be averaged)
  • 3 256 samples (shift sum 4 bits to right output data is 16 bits)
  • 3 16 samples (16 samples to be averaged)
  • 4 2 samples (shift sum 0 bits to right output data is in 12.1 format)
  • 4 32 samples (32 samples to be averaged)
  • 5 8 samples (shift sum 1 bit to right output data is in 13.1 format)
  • 5 64 samples (64 samples to be averaged)
  • 6 32 samples (shift sum 2 bits to right output data is in 14.1 format)
  • 6 128 samples (128 samples to be averaged)
  • 7 128 samples (shift sum 3 bits to right output data is in 15.1 format)
  • 7 256 samples (256 samples to be averaged)
AFGIEN25Digital Filter 'x' Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter 'x' Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 ADC0 Module
  • 1 ADC1 Module
  • 2 ADC2 Module
  • 3 ADC3 Module
  • 4 ADC4 Module
  • 5 ADC5 Module
  • 19 AN19 input
  • 20 AN20 input
  • 21 AN21 input
  • 22 AN22 input
  • 22 AN6 input
  • 23 AN23 input
  • 24 AN24 input
  • 25 AN25 input
  • 26 AN26 input
  • 27 AN27 input
  • 28 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter 'x' Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCFLTR3ADC Digital Filter 'x' Register ('x' = 1 through 6)

Address
0xBF8871C0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 4 samples (shift sum 1 bit to right output data is 13 bits)
  • 0 2 samples (2 samples to be averaged)
  • 1 16 samples (shift sum 2 bits to right output data is 14 bits)
  • 1 4 samples (4 samples to be averaged)
  • 2 64 samples (shift sum 3 bits to right output data is 15 bits)
  • 2 8 samples (8 samples to be averaged)
  • 3 256 samples (shift sum 4 bits to right output data is 16 bits)
  • 3 16 samples (16 samples to be averaged)
  • 4 2 samples (shift sum 0 bits to right output data is in 12.1 format)
  • 4 32 samples (32 samples to be averaged)
  • 5 8 samples (shift sum 1 bit to right output data is in 13.1 format)
  • 5 64 samples (64 samples to be averaged)
  • 6 32 samples (shift sum 2 bits to right output data is in 14.1 format)
  • 6 128 samples (128 samples to be averaged)
  • 7 128 samples (shift sum 3 bits to right output data is in 15.1 format)
  • 7 256 samples (256 samples to be averaged)
AFGIEN25Digital Filter 'x' Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter 'x' Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 ADC0 Module
  • 1 ADC1 Module
  • 2 ADC2 Module
  • 3 ADC3 Module
  • 4 ADC4 Module
  • 5 ADC5 Module
  • 19 AN19 input
  • 20 AN20 input
  • 21 AN21 input
  • 22 AN22 input
  • 22 AN6 input
  • 23 AN23 input
  • 24 AN24 input
  • 25 AN25 input
  • 26 AN26 input
  • 27 AN27 input
  • 28 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter 'x' Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCFLTR4ADC Digital Filter 'x' Register ('x' = 1 through 6)

Address
0xBF8871D0
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DATA16EN30Filter Significant Data Length bit
  • 0 Only the first 12 bits are significant
  • 1 All 16 bits of the filter output data are significant
DFMODE29ADC Filter Mode bit
  • 0 Filter x works in Oversampling Filter mode (default)
  • 1 Filter x works in Averaging mode
OVRSAM28:26Oversampling Filter Ratio bits
  • 0 4 samples (shift sum 1 bit to right output data is 13 bits)
  • 0 2 samples (2 samples to be averaged)
  • 1 16 samples (shift sum 2 bits to right output data is 14 bits)
  • 1 4 samples (4 samples to be averaged)
  • 2 64 samples (shift sum 3 bits to right output data is 15 bits)
  • 2 8 samples (8 samples to be averaged)
  • 3 256 samples (shift sum 4 bits to right output data is 16 bits)
  • 3 16 samples (16 samples to be averaged)
  • 4 2 samples (shift sum 0 bits to right output data is in 12.1 format)
  • 4 32 samples (32 samples to be averaged)
  • 5 8 samples (shift sum 1 bit to right output data is in 13.1 format)
  • 5 64 samples (64 samples to be averaged)
  • 6 32 samples (shift sum 2 bits to right output data is in 14.1 format)
  • 6 128 samples (128 samples to be averaged)
  • 7 128 samples (shift sum 3 bits to right output data is in 15.1 format)
  • 7 256 samples (256 samples to be averaged)
AFGIEN25Digital Filter 'x' Interrupt Enable bit
  • 0 Digital filter is disabled
  • 1 Digital filter interrupt is enabled and is generated by the AFRDY status bit
AFRDY24Digital Filter 'x' Data Ready Status bit
  • 0 Data is not ready
  • 1 Data is ready in the FLTRDATA bits
CHNLID20:16Digital Filter Analog Input Selection bits
  • 0 ADC0 Module
  • 1 ADC1 Module
  • 2 ADC2 Module
  • 3 ADC3 Module
  • 4 ADC4 Module
  • 5 ADC5 Module
  • 19 AN19 input
  • 20 AN20 input
  • 21 AN21 input
  • 22 AN22 input
  • 22 AN6 input
  • 23 AN23 input
  • 24 AN24 input
  • 25 AN25 input
  • 26 AN26 input
  • 27 AN27 input
  • 28 Reserved
  • 31 Reserved
FLTRDATA15:0
AFEN31Digital Filter 'x' Enable bit
  • 0 Digital filter is disabled and the AFRDY status bit is cleared
  • 1 Digital filter is enabled

ADCTRG1ADC Trigger Source 1 Register

Address
0xBF887200
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC328:24Trigger Source for Conversion of ADC3 Module Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC220:16Trigger Source for Conversion of ADC2 Module Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC112:8Trigger Source for Conversion of ADC1 Module Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC04:0Trigger Source for Conversion of ADC0 Module Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved

ADCTRG2ADC Trigger Source 2 Register

Address
0xBF887210
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC728:24Trigger Source for Conversion of Analog Input AN7 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC620:16Trigger Source for Conversion of Analog Input AN6 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC512:8Trigger Source for Conversion of ADC5 Module Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC44:0Trigger Source for Conversion of ADC4 Module Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved

ADCTRG3ADC Trigger Source 3 Register

Address
0xBF887220
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC1128:24Trigger Source for Conversion of Analog Input AN11 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control only)
  • 9 Secondary Special Event trigger (Motor Control only)
  • 10 PWM Generator 1 trigger (Motor Control only)
  • 11 PWM Generator 2 trigger (Motor Control only)
  • 12 PWM Generator 3 trigger (Motor Control only)
  • 13 PWM Generator 4 trigger (Motor Control only)
  • 14 PWM Generator 5 trigger (Motor Control only)
  • 15 PWM Generator 6 trigger (Motor Control only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control only)
  • 25 PWM Generator 2 Current-Limit (Motor Control only)
  • 26 PWM Generator 3 Current-Limit (Motor Control only)
  • 27 PWM Generator 4 Current-Limit (Motor Control only)
  • 28 PWM Generator 5 Current-Limit (Motor Control only)
  • 29 PWM Generator 6 Current-Limit (Motor Control only)
  • 30 Reserved
  • 31 Reserved
TRGSRC1020:16Trigger Source for Conversion of Analog Input AN10 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC912:8Trigger Source for Conversion of Analog Input AN9 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC84:0Trigger Source for Conversion of Analog Input AN8 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved

ADCTRG4ADC Trigger Source 4 Register

Address
0xBF887230
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC1528:24Trigger Source for Conversion of Analog Input AN15 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control only)
  • 9 Secondary Special Event trigger (Motor Control only)
  • 10 PWM Generator 1 trigger (Motor Control only)
  • 11 PWM Generator 2 trigger (Motor Control only)
  • 12 PWM Generator 3 trigger (Motor Control only)
  • 13 PWM Generator 4 trigger (Motor Control only)
  • 14 PWM Generator 5 trigger (Motor Control only)
  • 15 PWM Generator 6 trigger (Motor Control only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control only)
  • 25 PWM Generator 2 Current-Limit (Motor Control only)
  • 26 PWM Generator 3 Current-Limit (Motor Control only)
  • 27 PWM Generator 4 Current-Limit (Motor Control only)
  • 28 PWM Generator 5 Current-Limit (Motor Control only)
  • 29 PWM Generator 6 Current-Limit (Motor Control only)
  • 30 Reserved
  • 31 Reserved
TRGSRC1420:16Trigger Source for Conversion of Analog Input AN14 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC1312:8Trigger Source for Conversion of Analog Input AN13 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC124:0Trigger Source for Conversion of Analog Input AN12 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved

ADCTRG5ADC Trigger Source 5 Register

Address
0xBF887240
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC1928:24Trigger Source for Conversion of Analog Input AN19 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control only)
  • 9 Secondary Special Event trigger (Motor Control only)
  • 10 PWM Generator 1 trigger (Motor Control only)
  • 11 PWM Generator 2 trigger (Motor Control only)
  • 12 PWM Generator 3 trigger (Motor Control only)
  • 13 PWM Generator 4 trigger (Motor Control only)
  • 14 PWM Generator 5 trigger (Motor Control only)
  • 15 PWM Generator 6 trigger (Motor Control only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control only)
  • 25 PWM Generator 2 Current-Limit (Motor Control only)
  • 26 PWM Generator 3 Current-Limit (Motor Control only)
  • 27 PWM Generator 4 Current-Limit (Motor Control only)
  • 28 PWM Generator 5 Current-Limit (Motor Control only)
  • 29 PWM Generator 6 Current-Limit (Motor Control only)
  • 30 Reserved
  • 31 Reserved
TRGSRC1820:16Trigger Source for Conversion of Analog Input AN18 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC1712:8Trigger Source for Conversion of Analog Input AN17 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC164:0Trigger Source for Conversion of Analog Input AN16 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved

ADCTRG6ADC Trigger Source 6 Register

Address
0xBF887250
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC2328:24Trigger Source for Conversion of Analog Input AN23 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control only)
  • 9 Secondary Special Event trigger (Motor Control only)
  • 10 PWM Generator 1 trigger (Motor Control only)
  • 11 PWM Generator 2 trigger (Motor Control only)
  • 12 PWM Generator 3 trigger (Motor Control only)
  • 13 PWM Generator 4 trigger (Motor Control only)
  • 14 PWM Generator 5 trigger (Motor Control only)
  • 15 PWM Generator 6 trigger (Motor Control only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control only)
  • 25 PWM Generator 2 Current-Limit (Motor Control only)
  • 26 PWM Generator 3 Current-Limit (Motor Control only)
  • 27 PWM Generator 4 Current-Limit (Motor Control only)
  • 28 PWM Generator 5 Current-Limit (Motor Control only)
  • 29 PWM Generator 6 Current-Limit (Motor Control only)
  • 30 Reserved
  • 31 Reserved
TRGSRC2220:16Trigger Source for Conversion of Analog Input AN22 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC2112:8Trigger Source for Conversion of Analog Input AN21 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC204:0Trigger Source for Conversion of Analog Input AN20 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved

ADCTRG7ADC Trigger Source 7 Register

Address
0xBF887260
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
TRGSRC2728:24Trigger Source for Conversion of Analog Input AN27 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see the following Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control only)
  • 9 Secondary Special Event trigger (Motor Control only)
  • 10 PWM Generator 1 trigger (Motor Control only)
  • 11 PWM Generator 2 trigger (Motor Control only)
  • 12 PWM Generator 3 trigger (Motor Control only)
  • 13 PWM Generator 4 trigger (Motor Control only)
  • 14 PWM Generator 5 trigger (Motor Control only)
  • 15 PWM Generator 6 trigger (Motor Control only)
  • 16 Output Compare 1 (Rising Edge only)
  • 17 Output Compare 2 (Rising Edge only)
  • 18 Output Compare 3 (Rising Edge only)
  • 19 Output Compare 4 (Rising Edge only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control only)
  • 25 PWM Generator 2 Current-Limit (Motor Control only)
  • 26 PWM Generator 3 Current-Limit (Motor Control only)
  • 27 PWM Generator 4 Current-Limit (Motor Control only)
  • 28 PWM Generator 5 Current-Limit (Motor Control only)
  • 29 PWM Generator 6 Current-Limit (Motor Control only)
  • 30 Reserved
  • 31 Reserved
TRGSRC2620:16Trigger Source for Conversion of Analog Input AN26 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC2512:8Trigger Source for Conversion of Analog Input AN25 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved
TRGSRC244:0Trigger Source for Conversion of Analog Input AN24 Select bits
  • 0 No Trigger
  • 1 Software edge trigger
  • 2 Software level trigger
  • 3 Scan trigger (see Note)
  • 4 INT0
  • 5 General Purpose Timer1
  • 6 General Purpose Timer3
  • 7 General Purpose Timer5
  • 8 Primary Special Event trigger (Motor Control Variants Only)
  • 9 Secondary Special Event trigger (Motor Control Variants Only)
  • 10 PWM Generator 1 trigger (Motor Control Variants Only)
  • 11 PWM Generator 2 trigger (Motor Control Variants Only)
  • 12 PWM Generator 3 trigger (Motor Control Variants Only)
  • 13 PWM Generator 4 trigger (Motor Control Variants Only)
  • 14 PWM Generator 5 trigger (Motor Control Variants Only)
  • 15 PWM Generator 6 trigger (Motor Control Variants Only)
  • 16 Output Compare 1 (Rising Edge Only)
  • 17 Output Compare 2 (Rising Edge Only)
  • 18 Output Compare 3 (Rising Edge Only)
  • 19 Output Compare 4 (Rising Edge Only)
  • 20 CTMU trip
  • 21 Reserved
  • 22 Reserved
  • 23 Reserved
  • 24 PWM Generator 1 Current-Limit (Motor Control Variants Only)
  • 25 PWM Generator 2 Current-Limit (Motor Control Variants Only)
  • 26 PWM Generator 3 Current-Limit (Motor Control Variants Only)
  • 27 PWM Generator 4 Current-Limit (Motor Control Variants Only)
  • 28 PWM Generator 5 Current-Limit (Motor Control Variants Only)
  • 29 PWM Generator 6 Current-Limit (Motor Control Variants Only)
  • 30 Reserved
  • 31 Reserved

ADCCMPCON1ADC Digital Comparator 1 Control Register

Address
0xBF887280
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
AINID13:8Digital Comparator 1 Analog Input Identification bits
  • 0 AN0 is being monitored
  • 33 AN33 is being monitored
  • 41 AN41 is being monitored
  • 42 Reserved
  • 44 Reserved
  • 45 AN45 is being monitored
  • 49 AN49 is being monitored
  • 50 Internal AN50 (IVref 1.2V)
  • 53 Internal AN53 (CTMU temperature sensor)
  • 53 Internal AN52 (Vbat/2)
  • 53 Reserved
  • 54 Reserved
  • 56 Reserved
  • 59 AN27 is being monitored
  • 60 Reserved
  • 63 Reserved
ENDCMP7Digital Comparator 1 Enable bit
  • 0 Digital Comparator 1 is not enabled
  • 1 Digital Comparator 1 is enabled
DCMPGIEN6Digital Comparator 1 Global Interrupt Enable bit
  • 0 A Digital Comparator 1 interrupt is disabled
  • 1 A Digital Comparator 1 interrupt is generated when the DCMPED status bit (ADCCMP0CON) is set
DCMPED5Digital Comparator 1 ??Output True? Event Status bit
  • 0 Digital Comparator 1 output is false (output of comparator is 0)
  • 1 Digital Comparator 1 output true event has occurred (output of Comparator is 1)
IEBTWN4
IEHIHI3High/High Digital Comparator 0 Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator 0 Event when DCMPHI ? DATA<31:0>
IEHILO2High/Low Digital Comparator 0 Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator 0 Event when DATA < DCMPHI<15:0>
IELOHI1Low/High Digital Comparator 0 Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator 0 Event when DCMPLO ? DATA<31:0>
IELOLO0Low/Low Digital Comparator 0 Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator 0 Event when DATA < DCMPLO<15:0>
CVDDATA31:16

ADCCMPCON2ADC Digital Comparator 'x' Control Register ('x' = 2 through 4)

Address
0xBF887290
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
AINID12:8Digital Comparator 'x' Analog Input Identification bits
  • 0 AN0
  • 1 AN1
  • 19 AN19
  • 20 AN20
  • 21 AN21
  • 22 AN22
  • 23 AN23
  • 24 AN24
  • 25 AN25
  • 26 AN26
  • 27 AN27
  • 28 Reserved
  • 31 Reserved
ENDCMP7Digital Comparator 'x' Enable bit
  • 0 Digital Comparator x is not enabled
  • 1 Digital Comparator x is enabled
DCMPGIEN6Digital Comparator 'x' Global Interrupt Enable bit
  • 0 A Digital Comparator x interrupt is disabled
  • 1 A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED5Digital Comparator 'x' "Output True" Event Status bit
  • 0 Digital Comparator x output is false (output of Comparator is 0)
  • 1 Digital Comparator x output true event has occurred (output of Comparator is 1)
IEBTWN4
IEHIHI3High/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPHI bits <= DATA<31:0> bits
IEHILO2High/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPHI<15:0> bits
IELOHI1Low/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPLO bits < DATA<31:0> bits
IELOLO0Low/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPLO<15:0> bits

ADCCMPCON3ADC Digital Comparator 'x' Control Register ('x' = 2 through 4)

Address
0xBF8872A0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
AINID12:8Digital Comparator 'x' Analog Input Identification bits
  • 0 AN0
  • 1 AN1
  • 19 AN19
  • 20 AN20
  • 21 AN21
  • 22 AN22
  • 23 AN23
  • 24 AN24
  • 25 AN25
  • 26 AN26
  • 27 AN27
  • 28 Reserved
  • 31 Reserved
ENDCMP7Digital Comparator 'x' Enable bit
  • 0 Digital Comparator x is not enabled
  • 1 Digital Comparator x is enabled
DCMPGIEN6Digital Comparator 'x' Global Interrupt Enable bit
  • 0 A Digital Comparator x interrupt is disabled
  • 1 A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED5Digital Comparator 'x' "Output True" Event Status bit
  • 0 Digital Comparator x output is false (output of Comparator is 0)
  • 1 Digital Comparator x output true event has occurred (output of Comparator is 1)
IEBTWN4
IEHIHI3High/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPHI bits <= DATA<31:0> bits
IEHILO2High/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPHI<15:0> bits
IELOHI1Low/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPLO bits < DATA<31:0> bits
IELOLO0Low/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPLO<15:0> bits

ADCCMPCON4ADC Digital Comparator 'x' Control Register ('x' = 2 through 4)

Address
0xBF8872B0
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
AINID12:8Digital Comparator 'x' Analog Input Identification bits
  • 0 AN0
  • 1 AN1
  • 19 AN19
  • 20 AN20
  • 21 AN21
  • 22 AN22
  • 23 AN23
  • 24 AN24
  • 25 AN25
  • 26 AN26
  • 27 AN27
  • 28 Reserved
  • 31 Reserved
ENDCMP7Digital Comparator 'x' Enable bit
  • 0 Digital Comparator x is not enabled
  • 1 Digital Comparator x is enabled
DCMPGIEN6Digital Comparator 'x' Global Interrupt Enable bit
  • 0 A Digital Comparator x interrupt is disabled
  • 1 A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
DCMPED5Digital Comparator 'x' "Output True" Event Status bit
  • 0 Digital Comparator x output is false (output of Comparator is 0)
  • 1 Digital Comparator x output true event has occurred (output of Comparator is 1)
IEBTWN4
IEHIHI3High/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPHI bits <= DATA<31:0> bits
IEHILO2High/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPHI<15:0> bits
IELOHI1Low/High Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DCMPLO bits < DATA<31:0> bits
IELOLO0Low/Low Digital Comparator x Event bit
  • 0 Do not generate an event
  • 1 Generate a Digital Comparator x Event when the DATA bits < DCMPLO<15:0> bits

ADCBASEADC Base Register

Address
0xBF887300
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCBASE15:0

ADCDSTATADC DMA Status Register

Address
0xBF887310
Reset
0x00000000
Access
read/write
Size
32-bit
27 fields
FieldBitsWhat it does
RBFIEN529RAM DMA Buffer B Full Interrupt Enable bits for ADC5
  • 0 Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
  • 1 Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN428RAM DMA Buffer B Full Interrupt Enable bits for ADC4
  • 0 Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
  • 1 Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN327RAM DMA Buffer B Full Interrupt Enable bits for ADC3
  • 0 Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
  • 1 Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN226RAM DMA Buffer B Full Interrupt Enable bits for ADC2
  • 0 Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
  • 1 Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN125RAM DMA Buffer B Full Interrupt Enable bits for ADC1
  • 0 Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
  • 1 Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
RBFIEN024RAM DMA Buffer B Full Interrupt Enable bits for ADC0
  • 0 Disable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
  • 1 Enable ping-pong DMA Buffer B interrupt requests for ADC5-ADC0
WOVERR23
RBF521RAM DMA Buffer B Full Status bits for ADC5
  • 0 RAM DMA pin-pong Buffer B is not full
  • 1 RAM DMA ping-pong Buffer B is full
RBF420RAM DMA Buffer B Full Status bits for ADC4
  • 0 RAM DMA pin-pong Buffer B is not full
  • 1 RAM DMA ping-pong Buffer B is full
RBF319RAM DMA Buffer B Full Status bits for ADC3
  • 0 RAM DMA pin-pong Buffer B is not full
  • 1 RAM DMA ping-pong Buffer B is full
RBF218RAM DMA Buffer B Full Status bits for ADC2
  • 0 RAM DMA pin-pong Buffer B is not full
  • 1 RAM DMA ping-pong Buffer B is full
RBF117RAM DMA Buffer B Full Status bits for ADC1
  • 0 RAM DMA pin-pong Buffer B is not full
  • 1 RAM DMA ping-pong Buffer B is full
RBF016RAM DMA Buffer B Full Status bits for ADC0
  • 0 RAM DMA pin-pong Buffer B is not full
  • 1 RAM DMA ping-pong Buffer B is full
DMACEN15
RAFIEN513RAM DMA Buffer A Full Interrupt Enable bits for ADC5
  • 0 Disable ping-pong DMA Buffer A interrupt requests for ADC
  • 1 Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN412RAM DMA Buffer A Full Interrupt Enable bits for ADC4
  • 0 Disable ping-pong DMA Buffer A interrupt requests for ADC
  • 1 Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN311RAM DMA Buffer A Full Interrupt Enable bits for ADC3
  • 0 Disable ping-pong DMA Buffer A interrupt requests for ADC
  • 1 Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN210RAM DMA Buffer A Full Interrupt Enable bits for ADC2
  • 0 Disable ping-pong DMA Buffer A interrupt requests for ADC
  • 1 Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN19RAM DMA Buffer A Full Interrupt Enable bits for ADC1
  • 0 Disable ping-pong DMA Buffer A interrupt requests for ADC
  • 1 Enable ping-pong DMA Buffer A interrupt requests for ADC
RAFIEN08RAM DMA Buffer A Full Interrupt Enable bits for ADC0
  • 0 Disable ping-pong DMA Buffer A interrupt requests for ADC
  • 1 Enable ping-pong DMA Buffer A interrupt requests for ADC
RAF55RAM DMA Ping-Pong Buffer A Full Status bits for ADC5
  • 0 RAM DMA ping-pong Buffer A is not full
  • 1 RAM DMA ping-pong Buffer A is full
RAF44RAM DMA Ping-Pong Buffer A Full Status bits for ADC4
  • 0 RAM DMA ping-pong Buffer A is not full
  • 1 RAM DMA ping-pong Buffer A is full
RAF33RAM DMA Ping-Pong Buffer A Full Status bits for ADC3
  • 0 RAM DMA ping-pong Buffer A is not full
  • 1 RAM DMA ping-pong Buffer A is full
RAF22RAM DMA Ping-Pong Buffer A Full Status bits for ADC2
  • 0 RAM DMA ping-pong Buffer A is not full
  • 1 RAM DMA ping-pong Buffer A is full
RAF11RAM DMA Ping-Pong Buffer A Full Status bits for ADC1
  • 0 RAM DMA ping-pong Buffer A is not full
  • 1 RAM DMA ping-pong Buffer A is full
RAF00RAM DMA Ping-Pong Buffer A Full Status bits for ADC0
  • 0 RAM DMA ping-pong Buffer A is not full
  • 1 RAM DMA ping-pong Buffer A is full
DMAEN31Global ADC DMA Enable bit
  • 0 DMA interface is disabled
  • 1 DMA interface is enabled

ADCCNTBADC Channel Sample Count Base Address Register

Address
0xBF887320
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCNTB31:0

ADCDMABADC Channel Sample Count Base Address Register

Address
0xBF887330
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCDMAB31:0

ADCTRGSNSADC Trigger Level/Edge Sensitivity Register

Address
0xBF887340
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
LVL2727Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL2626Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL2525Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL2424Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL2323Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL2222Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL2121Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL2020Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1919Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1818Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1717Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1616Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1515Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1414Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1313Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1212Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1111Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL1010Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL99Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL88Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL77Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL66Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL55Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL44Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL33Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL22Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL11Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
LVL00Trigger Level and Edge Sensitivity bits
  • 0 Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
  • 1 Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)

ADC0TIMEDedicated High-Speed ADCx Timing Register ('x' = 0 through 5)

Address
0xBF887350
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
BCHEN23Buffer Channel Enable bit
  • 0 ADC data must be read by CPU from appropriate ADC result register
  • 1 ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * TQ = TADx
  • 2 4 * TQ = TADx
  • 3 6 * TQ = TADx
  • 127 254 * TQ = TADx
SAMC9:0ADCx Sample Time bits
  • 0 2 TADx
  • 1 3 TADx
  • 1023 1025 TADx

ADC1TIMEDedicated High-Speed ADCx Timing Register ('x' = 0 through 5)

Address
0xBF887360
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
BCHEN23Buffer Channel Enable bit
  • 0 ADC data must be read by CPU from appropriate ADC result register
  • 1 ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * TQ = TADx
  • 2 4 * TQ = TADx
  • 3 6 * TQ = TADx
  • 127 254 * TQ = TADx
SAMC9:0ADCx Sample Time bits
  • 0 2 TADx
  • 1 3 TADx
  • 1023 1025 TADx

ADC2TIMEDedicated High-Speed ADCx Timing Register ('x' = 0 through 5)

Address
0xBF887370
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
BCHEN23Buffer Channel Enable bit
  • 0 ADC data must be read by CPU from appropriate ADC result register
  • 1 ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * TQ = TADx
  • 2 4 * TQ = TADx
  • 3 6 * TQ = TADx
  • 127 254 * TQ = TADx
SAMC9:0ADCx Sample Time bits
  • 0 2 TADx
  • 1 3 TADx
  • 1023 1025 TADx

ADC3TIMEDedicated High-Speed ADCx Timing Register ('x' = 0 through 5)

Address
0xBF887380
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
BCHEN23Buffer Channel Enable bit
  • 0 ADC data must be read by CPU from appropriate ADC result register
  • 1 ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * TQ = TADx
  • 2 4 * TQ = TADx
  • 3 6 * TQ = TADx
  • 127 254 * TQ = TADx
SAMC9:0ADCx Sample Time bits
  • 0 2 TADx
  • 1 3 TADx
  • 1023 1025 TADx

ADC4TIMEDedicated High-Speed ADCx Timing Register ('x' = 0 through 5)

Address
0xBF887390
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
BCHEN23Buffer Channel Enable bit
  • 0 ADC data must be read by CPU from appropriate ADC result register
  • 1 ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * TQ = TADx
  • 2 4 * TQ = TADx
  • 3 6 * TQ = TADx
  • 127 254 * TQ = TADx
SAMC9:0ADCx Sample Time bits
  • 0 2 TADx
  • 1 3 TADx
  • 1023 1025 TADx

ADC5TIMEDedicated High-Speed ADCx Timing Register ('x' = 0 through 5)

Address
0xBF8873A0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ADCEIS28:26ADCx Early Interrupt Select bits
  • 0 The data ready interrupt is generated 1 ADC clock prior to the end of conversion
  • 1 The data ready interrupt is generated 2 ADC clocks prior to the end of conversion
  • 6 The data ready interrupt is generated 7 ADC clocks prior to the end of conversion
  • 7 The data ready interrupt is generated 8 ADC clocks prior to the end of conversion
SELRES25:24ADCx Resolution Select bits
  • 0 6 bits
  • 1 8 bits
  • 2 10 bits
  • 3 12 bits
BCHEN23Buffer Channel Enable bit
  • 0 ADC data must be read by CPU from appropriate ADC result register
  • 1 ADC data saved in DMA system ram buffer when DMAEN (ADCDSTAT) = 1
ADCDIV22:16ADCx Clock Divisor bits
  • 0 Reserved
  • 1 2 * TQ = TADx
  • 2 4 * TQ = TADx
  • 3 6 * TQ = TADx
  • 127 254 * TQ = TADx
SAMC9:0ADCx Sample Time bits
  • 0 2 TADx
  • 1 3 TADx
  • 1023 1025 TADx

ADCEIQEN1

Address
0xBF8873C0
Reset
0x00000000
Access
read/write
Size
32-bit
28 fields
FieldBitsWhat it does
EIEN2727
EIEN2626
EIEN2525
EIEN2424
EIEN2323
EIEN2222
EIEN2121
EIEN2020
EIEN1919
EIEN1818
EIEN1717
EIEN1616
EIEN1515
EIEN1414
EIEN1313
EIEN1212
EIEN1111
EIEN1010
EIEN99
EIEN88
EIEN77
EIEN66
EIEN55
EIEN44
EIEN33
EIEN22
EIEN11
EIEN00

ADCEIQEN2

Address
0xBF8873D0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
EIEN5321
EIEN5220
EIEN5119
EIEN5018
EIEN4917
EIEN4816
EIEN4715
EIEN4614
EIEN4513
EIEN419
EIEN408
EIEN397
EIEN386
EIEN375
EIEN364
EIEN353
EIEN342
EIEN331

ADCEISTAT1ADC Early Interrupt Status Register 1

Address
0xBF8873E0
Reset
0x00000000
Access
read only
Size
32-bit
28 fields
FieldBitsWhat it does
EIRDY2727Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY2626Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY2525Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY2424Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY2323Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY2222Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY2121Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY2020Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1919Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1818Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1717Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1616Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1515Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1414Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1313Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1212Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1111Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY1010Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY99Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY88Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY77Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY66Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY55Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY44Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY33Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY22Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY11Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY00Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the

ADCEISTAT2ADC Early Interrupt Status Register 2

Address
0xBF8873F0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
EIRDY5321Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY5220Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY5119Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY5018Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY4917Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY4816Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY4715Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY4614Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY4513Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY419Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY408Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY397Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY386Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY375Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY364Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY353Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY342Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the
EIRDY331Early Interrupt for Corresponding Analog Input Ready bits
  • 0 Interrupts are disabled
  • 1 This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs this bit will set as per the configuration of the ADCEIS bits in the ADCxTIME register. For the

ADCANCONADC Analog Warm-up Control Register

Address
0xBF887400
Reset
0x00000000
Access
read/write
Size
32-bit
22 fields
FieldBitsWhat it does
WKUPCLKCNT27:24Wake-up Clock Count bits
  • 0 24 = 16 clocks
  • 1 24 = 16 clocks
  • 2 24 = 16 clocks
  • 3 24 = 16 clocks
  • 4 24 = 16 clocks
  • 5 25 = 32 clocks
  • 6 26 = 64 clocks
  • 15 215 = 32768 clocks
WKIEN723Shared ADC Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDY7 status bit is set
WKIEN521ADC Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN420ADC Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN319ADC Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN218ADC Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN117ADC Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKIEN016ADC Wake-up Interrupt Enable bit
  • 0 Disable interrupt
  • 1 Enable interrupt and generate interrupt when the WKRDYx status bit is set
WKRDY715Shared ADC Wake-up Status bit
  • 0 ADC7 Analog and Bias circuitry is not ready
  • 1 ADC7 Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANEN7 to 1
WKRDY513ADC5-ADC0 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY412ADC5-ADC0 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY311ADC5-ADC0 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY210ADC5-ADC0 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY19ADC5-ADC0 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
WKRDY08ADC5-ADC0 Wake-up Status bit
  • 0 ADCx Analog and Bias circuitry is not ready
  • 1 ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANENx to 1
ANEN77Shared ADC Analog and Bias Circuitry Enable bit
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN55ADC Analog and Bias Circuitry Enable bits
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN44ADC Analog and Bias Circuitry Enable bits
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN33ADC Analog and Bias Circuitry Enable bits
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN22ADC Analog and Bias Circuitry Enable bits
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN11ADC Analog and Bias Circuitry Enable bits
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.
ANEN00ADC Analog and Bias Circuitry Enable bits
  • 0 Analog and bias circuitry disabled
  • 1 Analog and bias circuitry enabled. Once the analog and bias circuit is enabled the ADC module needs a warm-up time as defined by the WKUPCLKCNT bits.

ADCDATA0ADC Output Data Register 'x'

Address
0xBF887600
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA1ADC Output Data Register 'x'

Address
0xBF887610
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA2ADC Output Data Register 'x'

Address
0xBF887620
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA3ADC Output Data Register 'x'

Address
0xBF887630
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA4ADC Output Data Register 'x'

Address
0xBF887640
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA5ADC Output Data Register 'x'

Address
0xBF887650
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA6ADC Output Data Register 'x'

Address
0xBF887660
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA7ADC Output Data Register 'x'

Address
0xBF887670
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA8ADC Output Data Register 'x'

Address
0xBF887680
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA9ADC Output Data Register 'x'

Address
0xBF887690
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA10ADC Output Data Register 'x'

Address
0xBF8876A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA11ADC Output Data Register 'x'

Address
0xBF8876B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA12ADC Output Data Register 'x'

Address
0xBF8876C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA13ADC Output Data Register 'x'

Address
0xBF8876D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA14ADC Output Data Register 'x'

Address
0xBF8876E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA15ADC Output Data Register 'x'

Address
0xBF8876F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA16ADC Output Data Register 'x'

Address
0xBF887700
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA17ADC Output Data Register 'x'

Address
0xBF887710
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA18ADC Output Data Register 'x'

Address
0xBF887720
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA19ADC Output Data Register 'x'

Address
0xBF887730
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA20ADC Output Data Register 'x'

Address
0xBF887740
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA21ADC Output Data Register 'x'

Address
0xBF887750
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA22ADC Output Data Register 'x'

Address
0xBF887760
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA23ADC Output Data Register 'x'

Address
0xBF887770
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA24ADC Output Data Register 'x'

Address
0xBF887780
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA25ADC Output Data Register 'x'

Address
0xBF887790
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA26ADC Output Data Register 'x'

Address
0xBF8877A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA27ADC Output Data Register 'x'

Address
0xBF8877B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA33ADC Output Data Register 'x'

Address
0xBF887810
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA34ADC Output Data Register 'x'

Address
0xBF887820
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA35ADC Output Data Register 'x'

Address
0xBF887830
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA36ADC Output Data Register 'x'

Address
0xBF887840
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA37ADC Output Data Register 'x'

Address
0xBF887850
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA38ADC Output Data Register 'x'

Address
0xBF887860
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA39ADC Output Data Register 'x'

Address
0xBF887870
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA40ADC Output Data Register 'x'

Address
0xBF887880
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA41ADC Output Data Register 'x'

Address
0xBF887890
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA45ADC Output Data Register 'x'

Address
0xBF8878D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA46ADC Output Data Register 'x'

Address
0xBF8878E0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA47ADC Output Data Register 'x'

Address
0xBF8878F0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA48ADC Output Data Register 'x'

Address
0xBF887900
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA49ADC Output Data Register 'x'

Address
0xBF887910
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA50ADC Output Data Register 'x'

Address
0xBF887920
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA51

Address
0xBF887930
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA52ADC Output Data Register 'x'

Address
0xBF887940
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADCDATA53ADC Output Data Register 'x'

Address
0xBF887950
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0

ADC0CFGADC0 Configuration Register

Address
0xBF887D00
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC1CFGADC1 Configuration Register

Address
0xBF887D10
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC2CFGADC2 Configuration Register

Address
0xBF887D20
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC3CFGADC3 Configuration Register

Address
0xBF887D30
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC4CFGADC4 Configuration Register

Address
0xBF887D40
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC5CFGADC5 Configuration Register

Address
0xBF887D50
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADC7CFG

Address
0xBF887D70
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADCCFG31:0

ADCSYSCFG0ADC System Configuration Register 0

Address
0xBF887E00
Reset
0x00000000
Access
read only
Size
32-bit
28 fields
FieldBitsWhat it does
AN2727
AN2626
AN2525
AN2424
AN2323
AN2222
AN2121
AN2020
AN1919
AN1818
AN1717
AN1616
AN1515
AN1414
AN1313
AN1212
AN1111
AN1010
AN99
AN88
AN77
AN66
AN55
AN44
AN33
AN22
AN11
AN00

ADCSYSCFG1ADC System Configuration Register 1

Address
0xBF887E10
Reset
0x00000000
Access
read only
Size
32-bit
18 fields
FieldBitsWhat it does
AN5321
AN5220
AN5119
AN5018
AN4917
AN4816
AN4715
AN4614
AN4513
AN419
AN408
AN397
AN386
AN375
AN364
AN353
AN342
AN331