PIC32MK1024MCF100 CMP registers

The 6 registers of CMP (Comparator), from 0xBF82C000, with their reset value and every field. The PIC32MK1024MCF100 has 1917 registers in 121 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

CMP Comparator

CMSTATOp amp/Comparator Status Register

Address
0xBF82C000
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
C5EVT20
C4EVT19
C3EVT18
C2EVT17
C1EVT16
SIDL13Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue operation of all Op amp/Comparators when device enters Idle mode
C5OUT4Op amp/Comparator 5 Output Status bit
  • 0 (When CPOL is 0) VIN+ VTH+
  • 1 (When CPOL is 0) Vin+ > Vth+ / (When CPOL is 1) VIN+ Vth+ / (When CPOL is 1) VIN+ < VTH-
C4OUT3Op amp/Comparator 4 Output Status bit
  • 0 (When CPOL is 0) VIN+ VTH+
  • 1 (When CPOL is 0) Vin+ > Vth+ / (When CPOL is 1) VIN+ Vth+ / (When CPOL is 1) VIN+ < VTH-
C3OUT2Op amp/Comparator 3 Output Status bit
  • 0 (When CPOL is 0) VIN+ VTH+
  • 1 (When CPOL is 0) Vin+ > Vth+ / (When CPOL is 1) VIN+ Vth+ / (When CPOL is 1) VIN+ < VTH-
C2OUT1Op amp/Comparator 2 Output Status bit
  • 0 (When CPOL is 0) VIN+ VTH+
  • 1 (When CPOL is 0) Vin+ > Vth+ / (When CPOL is 1) VIN+ Vth+ / (When CPOL is 1) VIN+ < VTH-
C1OUT0Op amp/Comparator 1 Output Status bit
  • 0 (When CPOL is 0) VIN+ VTH+
  • 1 (When CPOL is 0) Vin+ > Vth+ / (When CPOL is 1) VIN+ Vth+ / (When CPOL is 1) VIN+ < VTH-

CM1MSKCONComparator 'x' Mask Control Register ('x' = 1-5)

Address
0xBF82C020
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
SELSRCC27:24
SELSRCB23:20
SELSRCA19:16Mask A Input Select bits
  • 0 PWM1L
  • 1 PWM1H
  • 2 PWM2L
  • 3 PWM2H
  • 4 PWM3L
  • 5 PWM3H
  • 6 PWM4L
  • 7 PWM4H
  • 8 PWM5L
  • 9 PWM5H
  • 10 PWM6L
  • 11 PWM6H
  • 12 Reserved
  • 13 Reserved
  • 14 FLT2 pin
  • 15 FLT4 pin
HLMS15High or Low Level Masking Select bit
  • 0 The comparator deasserted state is 0
  • 1 The comparator deasserted state is 1
OCEN13OR Gate "C" Input Enable bit
  • 0 "C" input disabled as input to OR gate
  • 1 "C" input enabled as input to OR gate
OCNEN12OR Gate "C" Input Inverted Enable bit
  • 0 "C" input (inverted) disabled as input to OR gate
  • 1 "C" input (inverted) enabled as input to OR gate
OBEN11OR Gate "B" Input Enable bit
  • 0 "B" input disabled as input to OR gate
  • 1 "B" input enabled as input to OR gate
OBNEN10OR Gate "B" Input Inverted Enable bit
  • 0 "B" input (inverted) disabled as input to OR gate
  • 1 "B" input (inverted) enabled as input to OR gate
OAEN9OR Gate "A" Input Enable bit
  • 0 "A" input disabled as input to OR gate
  • 1 "A"input enabled as input to OR gate
OANEN8OR Gate "A" Input Inverted Enable bit
  • 0 "A" input (inverted) disabled as input to OR gate
  • 1 "A" input (inverted) enabled as input to OR gate
NAGS7Negative AND Gate Output Select bit
  • 0 The negative (inverted) output of the AND gate to the OR gate is disabled
  • 1 The negative (inverted) output of the AND gate to the OR gate is enabled
PAGS6Positive AND Gate Output Select bit
  • 0 The positive output of the AND gate to the OR gate is disabled
  • 1 The positive output of the AND gate to the OR gate is enabled
ACEN5AND Gate "C" Input Enable bit
  • 0 "C" input disabled as input to AND gate
  • 1 "C" input enabled as input to AND gate
ACNEN4AND Gate "C" Inverted Input Enable bit
  • 0 "C" input (inverted) disabled as input to AND gate
  • 1 "C" input (inverted) enabled as input to AND gate
ABEN3AND Gate "B" Input Enable bit
  • 0 "B" input disabled as input to AND gate
  • 1 "B" input enabled as input to AND gate
ABNEN2AND Gate "B" Inverted Input Enable bit
  • 0 "B" input (inverted) disabled as input to AND gate
  • 1 "B" input (inverted) enabled as input to AND gate
AAEN1AND Gate "A" Input Enable bit
  • 0 "A" input disabled as input to AND gate
  • 1 "A" input enabled as input to AND gate
AANEN0AND Gate "A" Inverted Input Enable bit
  • 0 "A" input (inverted) disabled as input to AND gate
  • 1 "A" input (inverted) enabled as input to AND gate

CM2MSKCONComparator 'x' Mask Control Register ('x' = 1-5)

Address
0xBF82C040
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
SELSRCC27:24
SELSRCB23:20
SELSRCA19:16Mask A Input Select bits
  • 0 PWM1L
  • 1 PWM1H
  • 2 PWM2L
  • 3 PWM2H
  • 4 PWM3L
  • 5 PWM3H
  • 6 PWM4L
  • 7 PWM4H
  • 8 PWM5L
  • 9 PWM5H
  • 10 PWM6L
  • 11 PWM6H
  • 12 Reserved
  • 13 Reserved
  • 14 FLT2 pin
  • 15 FLT4 pin
HLMS15High or Low Level Masking Select bit
  • 0 The comparator deasserted state is 0
  • 1 The comparator deasserted state is 1
OCEN13OR Gate "C" Input Enable bit
  • 0 "C" input disabled as input to OR gate
  • 1 "C" input enabled as input to OR gate
OCNEN12OR Gate "C" Input Inverted Enable bit
  • 0 "C" input (inverted) disabled as input to OR gate
  • 1 "C" input (inverted) enabled as input to OR gate
OBEN11OR Gate "B" Input Enable bit
  • 0 "B" input disabled as input to OR gate
  • 1 "B" input enabled as input to OR gate
OBNEN10OR Gate "B" Input Inverted Enable bit
  • 0 "B" input (inverted) disabled as input to OR gate
  • 1 "B" input (inverted) enabled as input to OR gate
OAEN9OR Gate "A" Input Enable bit
  • 0 "A" input disabled as input to OR gate
  • 1 "A"input enabled as input to OR gate
OANEN8OR Gate "A" Input Inverted Enable bit
  • 0 "A" input (inverted) disabled as input to OR gate
  • 1 "A" input (inverted) enabled as input to OR gate
NAGS7Negative AND Gate Output Select bit
  • 0 The negative (inverted) output of the AND gate to the OR gate is disabled
  • 1 The negative (inverted) output of the AND gate to the OR gate is enabled
PAGS6Positive AND Gate Output Select bit
  • 0 The positive output of the AND gate to the OR gate is disabled
  • 1 The positive output of the AND gate to the OR gate is enabled
ACEN5AND Gate "C" Input Enable bit
  • 0 "C" input disabled as input to AND gate
  • 1 "C" input enabled as input to AND gate
ACNEN4AND Gate "C" Inverted Input Enable bit
  • 0 "C" input (inverted) disabled as input to AND gate
  • 1 "C" input (inverted) enabled as input to AND gate
ABEN3AND Gate "B" Input Enable bit
  • 0 "B" input disabled as input to AND gate
  • 1 "B" input enabled as input to AND gate
ABNEN2AND Gate "B" Inverted Input Enable bit
  • 0 "B" input (inverted) disabled as input to AND gate
  • 1 "B" input (inverted) enabled as input to AND gate
AAEN1AND Gate "A" Input Enable bit
  • 0 "A" input disabled as input to AND gate
  • 1 "A" input enabled as input to AND gate
AANEN0AND Gate "A" Inverted Input Enable bit
  • 0 "A" input (inverted) disabled as input to AND gate
  • 1 "A" input (inverted) enabled as input to AND gate

CM3MSKCONComparator 'x' Mask Control Register ('x' = 1-5)

Address
0xBF82C060
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
SELSRCC27:24
SELSRCB23:20
SELSRCA19:16Mask A Input Select bits
  • 0 PWM1L
  • 1 PWM1H
  • 2 PWM2L
  • 3 PWM2H
  • 4 PWM3L
  • 5 PWM3H
  • 6 PWM4L
  • 7 PWM4H
  • 8 PWM5L
  • 9 PWM5H
  • 10 PWM6L
  • 11 PWM6H
  • 12 Reserved
  • 13 Reserved
  • 14 FLT2 pin
  • 15 FLT4 pin
HLMS15High or Low Level Masking Select bit
  • 0 The comparator deasserted state is 0
  • 1 The comparator deasserted state is 1
OCEN13OR Gate "C" Input Enable bit
  • 0 "C" input disabled as input to OR gate
  • 1 "C" input enabled as input to OR gate
OCNEN12OR Gate "C" Input Inverted Enable bit
  • 0 "C" input (inverted) disabled as input to OR gate
  • 1 "C" input (inverted) enabled as input to OR gate
OBEN11OR Gate "B" Input Enable bit
  • 0 "B" input disabled as input to OR gate
  • 1 "B" input enabled as input to OR gate
OBNEN10OR Gate "B" Input Inverted Enable bit
  • 0 "B" input (inverted) disabled as input to OR gate
  • 1 "B" input (inverted) enabled as input to OR gate
OAEN9OR Gate "A" Input Enable bit
  • 0 "A" input disabled as input to OR gate
  • 1 "A"input enabled as input to OR gate
OANEN8OR Gate "A" Input Inverted Enable bit
  • 0 "A" input (inverted) disabled as input to OR gate
  • 1 "A" input (inverted) enabled as input to OR gate
NAGS7Negative AND Gate Output Select bit
  • 0 The negative (inverted) output of the AND gate to the OR gate is disabled
  • 1 The negative (inverted) output of the AND gate to the OR gate is enabled
PAGS6Positive AND Gate Output Select bit
  • 0 The positive output of the AND gate to the OR gate is disabled
  • 1 The positive output of the AND gate to the OR gate is enabled
ACEN5AND Gate "C" Input Enable bit
  • 0 "C" input disabled as input to AND gate
  • 1 "C" input enabled as input to AND gate
ACNEN4AND Gate "C" Inverted Input Enable bit
  • 0 "C" input (inverted) disabled as input to AND gate
  • 1 "C" input (inverted) enabled as input to AND gate
ABEN3AND Gate "B" Input Enable bit
  • 0 "B" input disabled as input to AND gate
  • 1 "B" input enabled as input to AND gate
ABNEN2AND Gate "B" Inverted Input Enable bit
  • 0 "B" input (inverted) disabled as input to AND gate
  • 1 "B" input (inverted) enabled as input to AND gate
AAEN1AND Gate "A" Input Enable bit
  • 0 "A" input disabled as input to AND gate
  • 1 "A" input enabled as input to AND gate
AANEN0AND Gate "A" Inverted Input Enable bit
  • 0 "A" input (inverted) disabled as input to AND gate
  • 1 "A" input (inverted) enabled as input to AND gate

CM4MSKCONComparator 'x' Mask Control Register ('x' = 1-5)

Address
0xBF82C080
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
SELSRCC27:24
SELSRCB23:20
SELSRCA19:16Mask A Input Select bits
  • 0 PWM1L
  • 1 PWM1H
  • 2 PWM2L
  • 3 PWM2H
  • 4 PWM3L
  • 5 PWM3H
  • 6 PWM4L
  • 7 PWM4H
  • 8 PWM5L
  • 9 PWM5H
  • 10 PWM6L
  • 11 PWM6H
  • 12 Reserved
  • 13 Reserved
  • 14 FLT2 pin
  • 15 FLT4 pin
HLMS15High or Low Level Masking Select bit
  • 0 The comparator deasserted state is 0
  • 1 The comparator deasserted state is 1
OCEN13OR Gate "C" Input Enable bit
  • 0 "C" input disabled as input to OR gate
  • 1 "C" input enabled as input to OR gate
OCNEN12OR Gate "C" Input Inverted Enable bit
  • 0 "C" input (inverted) disabled as input to OR gate
  • 1 "C" input (inverted) enabled as input to OR gate
OBEN11OR Gate "B" Input Enable bit
  • 0 "B" input disabled as input to OR gate
  • 1 "B" input enabled as input to OR gate
OBNEN10OR Gate "B" Input Inverted Enable bit
  • 0 "B" input (inverted) disabled as input to OR gate
  • 1 "B" input (inverted) enabled as input to OR gate
OAEN9OR Gate "A" Input Enable bit
  • 0 "A" input disabled as input to OR gate
  • 1 "A"input enabled as input to OR gate
OANEN8OR Gate "A" Input Inverted Enable bit
  • 0 "A" input (inverted) disabled as input to OR gate
  • 1 "A" input (inverted) enabled as input to OR gate
NAGS7Negative AND Gate Output Select bit
  • 0 The negative (inverted) output of the AND gate to the OR gate is disabled
  • 1 The negative (inverted) output of the AND gate to the OR gate is enabled
PAGS6Positive AND Gate Output Select bit
  • 0 The positive output of the AND gate to the OR gate is disabled
  • 1 The positive output of the AND gate to the OR gate is enabled
ACEN5AND Gate "C" Input Enable bit
  • 0 "C" input disabled as input to AND gate
  • 1 "C" input enabled as input to AND gate
ACNEN4AND Gate "C" Inverted Input Enable bit
  • 0 "C" input (inverted) disabled as input to AND gate
  • 1 "C" input (inverted) enabled as input to AND gate
ABEN3AND Gate "B" Input Enable bit
  • 0 "B" input disabled as input to AND gate
  • 1 "B" input enabled as input to AND gate
ABNEN2AND Gate "B" Inverted Input Enable bit
  • 0 "B" input (inverted) disabled as input to AND gate
  • 1 "B" input (inverted) enabled as input to AND gate
AAEN1AND Gate "A" Input Enable bit
  • 0 "A" input disabled as input to AND gate
  • 1 "A" input enabled as input to AND gate
AANEN0AND Gate "A" Inverted Input Enable bit
  • 0 "A" input (inverted) disabled as input to AND gate
  • 1 "A" input (inverted) enabled as input to AND gate

CM5MSKCONComparator 'x' Mask Control Register ('x' = 1-5)

Address
0xBF82C0A0
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
SELSRCC27:24
SELSRCB23:20
SELSRCA19:16Mask A Input Select bits
  • 0 PWM1L
  • 1 PWM1H
  • 2 PWM2L
  • 3 PWM2H
  • 4 PWM3L
  • 5 PWM3H
  • 6 PWM4L
  • 7 PWM4H
  • 8 PWM5L
  • 9 PWM5H
  • 10 PWM6L
  • 11 PWM6H
  • 12 Reserved
  • 13 Reserved
  • 14 FLT2 pin
  • 15 FLT4 pin
HLMS15High or Low Level Masking Select bit
  • 0 The comparator deasserted state is 0
  • 1 The comparator deasserted state is 1
OCEN13OR Gate "C" Input Enable bit
  • 0 "C" input disabled as input to OR gate
  • 1 "C" input enabled as input to OR gate
OCNEN12OR Gate "C" Input Inverted Enable bit
  • 0 "C" input (inverted) disabled as input to OR gate
  • 1 "C" input (inverted) enabled as input to OR gate
OBEN11OR Gate "B" Input Enable bit
  • 0 "B" input disabled as input to OR gate
  • 1 "B" input enabled as input to OR gate
OBNEN10OR Gate "B" Input Inverted Enable bit
  • 0 "B" input (inverted) disabled as input to OR gate
  • 1 "B" input (inverted) enabled as input to OR gate
OAEN9OR Gate "A" Input Enable bit
  • 0 "A" input disabled as input to OR gate
  • 1 "A"input enabled as input to OR gate
OANEN8OR Gate "A" Input Inverted Enable bit
  • 0 "A" input (inverted) disabled as input to OR gate
  • 1 "A" input (inverted) enabled as input to OR gate
NAGS7Negative AND Gate Output Select bit
  • 0 The negative (inverted) output of the AND gate to the OR gate is disabled
  • 1 The negative (inverted) output of the AND gate to the OR gate is enabled
PAGS6Positive AND Gate Output Select bit
  • 0 The positive output of the AND gate to the OR gate is disabled
  • 1 The positive output of the AND gate to the OR gate is enabled
ACEN5AND Gate "C" Input Enable bit
  • 0 "C" input disabled as input to AND gate
  • 1 "C" input enabled as input to AND gate
ACNEN4AND Gate "C" Inverted Input Enable bit
  • 0 "C" input (inverted) disabled as input to AND gate
  • 1 "C" input (inverted) enabled as input to AND gate
ABEN3AND Gate "B" Input Enable bit
  • 0 "B" input disabled as input to AND gate
  • 1 "B" input enabled as input to AND gate
ABNEN2AND Gate "B" Inverted Input Enable bit
  • 0 "B" input (inverted) disabled as input to AND gate
  • 1 "B" input (inverted) enabled as input to AND gate
AAEN1AND Gate "A" Input Enable bit
  • 0 "A" input disabled as input to AND gate
  • 1 "A" input enabled as input to AND gate
AANEN0AND Gate "A" Inverted Input Enable bit
  • 0 "A" input (inverted) disabled as input to AND gate
  • 1 "A" input (inverted) enabled as input to AND gate