The 10 registers of PMP (Parallel master port), from 0xBF82E000, with their reset value and every field. The PIC32MK1024MCF100 has 1917 registers in 121 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
PMP Parallel master port
PMCONParallel Port Control Register
Address
0xBF82E000
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
RDSTART
23
Start Read on PMP Bus bit
0 No effect
32 Start a read cycle on the PMP bus
DUALBUF
17
Dual Read/Write Buffers enable bit
0 PMP uses legacy registers (PMADDR
1 PMP uses separate registers for reads and writes (PMRADDR
EXADR
16
ON
15
Parallel Master Port Enable bit
0 PMP is disabled
1 PMP is enabled
SIDL
13
Stop in Idle Mode bit
0 Continue module operation in Idle mode
1 Discontinue module operation when device enters Idle mode
ADRMUX
12:11
Address/Data Multiplexing Selection bits
0 Address and data appear on separate pins
1 Lower 8 bits of address are multiplexed on PMD pins
2 All 16 bits of address are multiplexed on PMD pins
3 Lower 8 bits of address are multiplexed on PMD pins; upper 8 bits are not used
PMPTTL
10
PMP Module TTL Input Buffer Select bit
0 PMP module uses Schmitt Trigger input buffer
1 PMP module uses TTL input buffers
PTWREN
9
Write Enable Strobe Port Enable bit
0 PMWR/PMENB port is disabled
1 PMWR/PMENB port is enabled
PTRDEN
8
Read/Write Strobe Port Enable bit
0 PMRD/PMWR port is disabled
1 PMRD/PMWR port is enabled
CSF
7:6
Chip Select Function bits
0 PMCS1 and PMCS2 function as address bit 14 and address bit 15
1 PMCS2 functions as Chip Select and PMCS1 functions as address bit 14
1 Interrupt is generated at the end of the read/write cycle
2 Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)or on a read or write operation when PMA = 11 (Addressable Slave mode only)
3 Reserved
INCM
12:11
Increment Mode bits
0 No increment or decrement of address
1 Increment ADDR and ADDR<14> by 1 every read/write cycle
2 Decrement ADDR and ADDR<14> by 1 every read/write cycle