The 5 registers of UART4 (UART 4), from 0xBF848600, with their reset value and every field. The PIC32MK1024MCF100 has 1917 registers in 121 peripherals, one page each.
Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.
UART4 UART 4
U4MODEUARTx Mode Register
Address
0xBF848600
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
SLPEN
23
Run During Sleep Enable bit
0 UARTx BRG clock is turned off during Sleep mode
1 UARTx BRG clock runs during Sleep mode
ACTIVE
22
UARTx Module Running Status bit
0 UARTx module is not active (UxMODE register can be updated)
8 UARTx module is active (UxMODE register should not be updated)
CLKSEL
18:17
UARTx Module Clock Selection bits
0 BRG clock is PBCLK2 (turned off in Sleep mode)
1 BRG clock is SYSCLK (turned off in Sleep mode)
2 BRG clock is FRC
3 BRG clock is REFCLK1
OVFDIS
16
ON
15
UARTx Enable bit
0 UARTx module is disabled. All UARTx pins are controlled by corresponding bits in the PORTx
1 UARTx module is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN control bits
SIDL
13
Stop in Idle Mode bit
0 Continue operation in Idle mode
1 Discontinue operation when device enters Idle mode
IREN
12
IrDA Encoder and Decoder Enable bit
0 IrDA is disabled
1 IrDA is enabled
RTSMD
11
Mode Selection for UxRTS Pin bit
0 UxRTS pin is in Flow Control mode
1 UxRTS pin is in Simplex mode
UEN
9:8
UARTx Module Enable bits
0 UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register
1 UxTX
2 UxTX
3 UxTX
WAKE
7
Enable Wake-up on Start bit Detect During Sleep Mode bit
0 Wake-up disabled
1 Wake-up enabled
LPBACK
6
UARTx Loopback Mode Select bit
0 Loopback mode is disabled
1 Loopback mode is enabled
ABAUD
5
Auto-Baud Enable bit
0 Baud rate measurement disabled or completed
1 Enable baud rate measurement on the next character requires reception of Sync character (0x55); cleared by hardware upon completion
RXINV
4
Receive Polarity Inversion bit
0 UxRX Idle state is 1
1 UxRX Idle state is 0
BRGH
3
High Baud Rate Enable bit
0 Standard Speed mode 16x baud clock enabled
1 High-Speed mode 4x baud clock enabled
PDSEL
2:1
Parity and Data Selection bits
0 8-bit data, no parity
1 8-bit data, even parity
2 8-bit data, odd parity
3 9-bit data, no parity
STSEL
0
Stop Selection bit
0 1 Stop bit
1 2 Stop bits
U4STAUARTx Status and Control Register
Address
0xBF848610
Reset
0x00000110
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
ADDR
23:16
UTXISEL
15:14
TX Interrupt Mode Selection bits
0 Interrupt is generated and asserted while the transmit buffer contains at least one empty space
1 Interrupt is generated and asserted when all characters have been transmitted
2 Interrupt is generated and asserted while the transmit buffer is empty
3 Reserved
UTXINV
13
Transmit Polarity Inversion bit
0 (If IrDA mode is disabled) UxTX Idle state is 1 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 0
1 (If IrDA mode is disabled) UxTX Idle state is 0 / (If IrDA mode is enabled) IrDA encoded UxTX Idle state is 1
URXEN
12
Receiver Enable bit
0 UARTx receiver is disabled. UxRX pin is ignored by the UARTx module
1 UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
UTXBRK
11
Transmit Break bit
0 Break transmission is disabled or completed
1 Send Break on next transmission. Start bit followed by twelve 0 bits
UTXEN
10
Transmit Enable bit
0 UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset
1 UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
UTXBF
9
Transmit Buffer Full Status bit (read-only)
0 Transmit buffer is not full
1 Transmit buffer is full
TRMT
8
Transmit Shift Register is Empty bit (read-only)
0 Transmit shift register is not empty
1 Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
URXISEL
7:6
Receive Interrupt Mode Selection bit
0 Interrupt flag bit is asserted while receive buffer is not empty (i.e.
1 Interrupt flag bit is asserted while receive buffer is 1/2 or more full
2 Interrupt flag bit is asserted while receive buffer is 3/4 or more full
3 Reserved
ADDEN
5
Address Character Detect bit (bit 8 of received data = 1)
0 Address Detect mode is disabled
1 Address Detect mode is enabled. If 9-bit mode is not selected
RIDLE
4
Receiver Idle bit (read-only)
0 Data is being received
1 Receiver is Idle
PERR
3
Parity Error Status bit (read-only)
0 Parity error has not been detected
1 Parity error has been detected for the current character
FERR
2
Framing Error Status bit (read-only)
0 Framing error has not been detected
1 Framing error has been detected for the current character
OERR
1
Receive Buffer Overrun Error Status bit.
0 Receive buffer has not overflowed
1 Receive buffer has overflowed
URXDA
0
Receive Buffer Data Available bit (read-only)
0 Receive buffer is empty
1 Receive buffer has data
MASK
31:24
UARTx Address Match Mask bits
0 Corresponding ADDRx bits are not used to detect the address match.
510 Corresponding ADDRx bits are used to detect the address match
BETA