PIC32MK1024MCF100 USB2 registers

The 36 registers of USB2 (USB), from 0xBF88A040, with their reset value and every field. The PIC32MK1024MCF100 has 1917 registers in 121 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

USB2 USB

U2OTGIRUSB OTG Interrupt Status Register (x = 1 and 2)

Address
0xBF88A040
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
IDIF7ID State Change Indicator bit
  • 0 No change in ID state is detected
  • 1 Change in ID state is detected
T1MSECIF61 Millisecond Timer bit
  • 0 1 millisecond timer has not expired
  • 1 1 millisecond timer has expired
LSTATEIF5Line State Stable Indicator bit
  • 0 USB line state has not been stable for 1 millisecond
  • 1 USB line state has been stable for 1 millisecond
ACTVIF4Bus Activity Indicator bit
  • 0 Activity has not been detected
  • 1 Activity on the D+
SESVDIF3Session Valid Change Indicator bit
  • 0 Vbus voltage has not dropped below the session end level
  • 1 Vbus voltage has dropped below the session end level
SESENDIF2B-Device
  • 0 No change on the session end input was detected
  • 1 A change on the session end input was detected
VBUSVDIF0A-Device
  • 0 No change on the session valid input is detected
  • 1 Change on the session valid input is detected

U2OTGIEUSB OTG Interrupt Enable Register (x = 1 and 2)

Address
0xBF88A050
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
IDIE7ID Interrupt Enable bit
  • 0 ID interrupt is disabled
  • 1 ID interrupt is enabled
T1MSECIE61 Millisecond Timer Interrupt Enable bit
  • 0 1 millisecond timer interrupt is disabled
  • 1 1 millisecond timer interrupt is enabled
LSTATEIE5Line State Interrupt Enable bit
  • 0 Line state interrupt is disabled
  • 1 Line state interrupt is enabled
ACTVIE4Bus Activity Interrupt Enable bit
  • 0 ACTIVITY interrupt is disabled
  • 1 ACTIVITY interrupt is enabled
SESVDIE3Session Valid Interrupt Enable bit
  • 0 Session valid interrupt is disabled
  • 1 Session valid interrupt is enabled
SESENDIE2B-Session End Interrupt Enable bit
  • 0 B-session end interrupt is disabled
  • 1 B-session end interrupt is enabled
VBUSVDIE0A- Vbus Valid Interrupt Enable bit
  • 0 A-Vbus valid interrupt is disabled
  • 1 A-Vbus valid interrupt is enabled

U2OTGSTATUSB OTG Status Register (x = 1 and 2)

Address
0xBF88A060
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
ID7ID Pin State Indicator bit
  • 0 A Type-A cable has been plugged into the USB receptacle
  • 1 No cable is attached or a Type-B cable has been plugged into the USB receptacle
LSTATE5Line State Stable Indicator bit
  • 0 USB line state (SE0 and JSTATE) has not been stable for the previous 1 ms
  • 1 USB line state (SE0 (UxCON) and JSTATE (UxCON<7>)) has been stable for the previous 1 ms
SESVD3Session Valid Indicator bit
  • 0 Vbus voltage is below Session Valid on the A or B device
  • 1 Vbus voltage is above Session Valid on the A or B device
SESEND2B-Device Session End Indicator bit
  • 0 Vbus voltage is above Session Valid on the B device
  • 1 Vbus voltage is below Session Valid on the B device
VBUSVD0A-Device Vbus Valid Indicator bit
  • 0 Vbus voltage is below Session Valid on the A device
  • 1 Vbus voltage is above Session Valid on the A device

U2OTGCONUSB OTG Control Register (x = 1 and 2)

Address
0xBF88A070
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
DPPULUP7D+ Pull-Up Enable bit
  • 0 D+ data line pull-up resistor is disabled
  • 1 D+ data line pull-up resistor is enabled
DMPULUP6D- Pull-Up Enable bit
  • 0 D- data line pull-up resistor is disabled
  • 1 D- data line pull-up resistor is enabled
DPPULDWN5D+ Pull-Down Enable bit
  • 0 D+ data line pull-down resistor is disabled
  • 1 D+ data line pull-down resistor is enabled
DMPULDWN4D- Pull-Down Enable bit
  • 0 D- data line pull-down resistor is disabled
  • 1 D- data line pull-down resistor is enabled
VBUSON3Vbus Power-on bit
  • 0 Vbus line is not powered
  • 1 Vbus line is powered
OTGEN2OTG Functionality Enable bit
  • 0 DPPULUP
  • 1 DPPULUP
VBUSCHG1Vbus Charge Enable bit
  • 0 Vbus line is not charged through a resistor
  • 1 Vbus line is charged through a pull-up resistor
VBUSDIS0Vbus Discharge Enable bit
  • 0 Vbus line is not discharged through a resistor
  • 1 Vbus line is discharged through a pull-down resistor

U2PWRCUSB Power Control Register (x = 1 and 2)

Address
0xBF88A080
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
UACTPND7USB Activity Pending bit
  • 0 An interrupt is not pending
  • 1 USB hardware has detected a change in link status; however
USLPGRD4USB Sleep Entry Guard bit
  • 0 USB module does not block Sleep entry
  • 1 Sleep entry is blocked if USB bus activity is detected or if a notification is pending
USBBUSY3USB Module Busy bit
  • 0 USB module is not active and is ready to be enabled
  • 1 USB module is active or disabled
USUSPEND1USB Suspend Mode bit
  • 0 USB module operates normally
  • 1 USB module is placed in Suspend mode (The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
USBPWR0USB Operation Enable bit
  • 0 USB module is disabled (Outputs held inactive
  • 1 USB module is turned on

U2IRUSB Interrupt Register (x = 1 and 2)

Address
0xBF88A200
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
STALLIF7STALL Handshake Interrupt bit
  • 0 STALL handshake has not been sent
  • 1 In Host mode
ATTACHIF6Peripheral Attach Interrupt bit
  • 0 Peripheral attachment was not detected
  • 1 Peripheral attachment was detected by the USB module
RESUMEIF5Resume Interrupt bit
  • 0 K-State is not observed
  • 1 K-State is observed on the D+ or D- pin for 2.5 s
IDLEIF4Idle Detect Interrupt bit
  • 0 No Idle condition detected
  • 1 Idle condition detected (constant Idle state of 3 ms or more)
TRNIF3Token Processing Complete Interrupt bit
  • 0 Processing of current token not complete
  • 1 Processing of current token is complete; a read of the UxSTAT register will provide endpoint information
SOFIF2SOF Token Interrupt bit
  • 0 SOF token was not received nor threshold reached
  • 1 SOF token received by the peripheral or the SOF threshold reached by the host
UERRIF1USB Error Condition Interrupt bit
  • 0 Unmasked error condition has not occurred
  • 1 Unmasked error condition has occurred
URSTIF_DETACHIF0(Device mode) USB Reset Interrupt bit Device mode / (Host mode)USB Detach Interrupt bit Host mode
  • 0 (Device mode)o USB Reset has occurred / (Host mode)Peripheral detachment was not detected
  • 1 (Device mode)Valid USB Reset has occurred / (Host mode)Peripheral detachment was detected by the USB module

U2IEUSB Interrupt Enable Register (x = 1 and 2)

Address
0xBF88A210
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
STALLIE7STALL Handshake Interrupt Enable bit
  • 0 STALL interrupt is disabled
  • 1 STALL interrupt is enabled
ATTACHIE6ATTACH Interrupt Enable bit
  • 0 ATTACH interrupt is disabled
  • 1 ATTACH interrupt is enabled
RESUMEIE5RESUME Interrupt Enable bit
  • 0 RESUME interrupt is disabled
  • 1 RESUME interrupt is enabled
IDLEIE4Idle Detect Interrupt Enable bit
  • 0 Idle interrupt is disabled
  • 1 Idle interrupt is enabled
TRNIE3Token Processing Complete Interrupt Enable bit
  • 0 TRNIF interrupt is disabled
  • 1 TRNIF interrupt is enabled
SOFIE2SOF Token Interrupt Enable bit
  • 0 SOFIF interrupt is disabled
  • 1 SOFIF interrupt is enabled
UERRIE1USB Error Interrupt Enable bit
  • 0 USB Error interrupt is disabled
  • 1 USB Error interrupt is enabled
URSTIE_DETACHIE0(Device mode) USB Reset Interrupt Enable bit Device mode / (Host mode)USB Detach Interrupt Enable bit Host Mode
  • 0 (Device mode) URSTIF interrupt is disabled / (Host mode) DATTCHIF interrupt is disabled
  • 1 (Device mode) URSTIF interrupt is enabled / (Host mode) DATTCHIF interrupt is enabled

U2EIRUSB Error Interrupt Status Register (x = 1 and 2)

Address
0xBF88A220
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BTSEF7Bit Stuff Error Flag bit
  • 0 Packet accepted
  • 1 Packet rejected due to bit stuff error
BMXEF6Bus Matrix Error Flag bit
  • 0 No address error
  • 1 The base address
DMAEF5DMA Error Flag bit
  • 0 No DMA error
  • 1 USB DMA error condition detected
BTOEF4Bus Turnaround Time-Out Error Flag bit
  • 0 No bus turnaround time-out
  • 1 Bus turnaround time-out has occurred
DFN8EF3Data Field Size Error Flag bit
  • 0 Data field received is an integral number of bytes
  • 1 Data field received is not an integral number of bytes
CRC16EF2CRC16 Failure Flag bit
  • 0 Data packet accepted
  • 1 Data packet rejected due to CRC16 error
CRC5EF_EOFEF1(Device mode)CRC5 Host Error Flag bit / (Host mode)EOF Error Flag bit
  • 0 (Device mode)Token packet accepted / (Host mode)No EOF error condition
  • 1 (Device mode)Token packet rejected due to CRC5 error / (Host mode)EOF error condition detected
PIDEF0PID Check Failure Flag bit
  • 0 PID check passed
  • 1 PID check failed

U2EIEUSB Error Interrupt Enable Register (x = 1 and 2)

Address
0xBF88A230
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BTSEE7Bit Stuff Error Interrupt Enable bit
  • 0 BTSEF interrupt is disabled
  • 1 BTSEF interrupt is enabled
BMXEE6Bus Matrix Error Interrupt Enable bit
  • 0 BMXEF interrupt is disabled
  • 1 BMXEF interrupt is enabled
DMAEE5DMA Error Interrupt Enable bit
  • 0 DMAEF interrupt is disabled
  • 1 DMAEF interrupt is enabled
BTOEE4Bus Turnaround Time-out Error Interrupt Enable bit
  • 0 BTOEF interrupt is disabled
  • 1 BTOEF interrupt is enabled
DFN8EE3Data Field Size Error Interrupt Enable bit
  • 0 DFN8EF interrupt is disabled
  • 1 DFN8EF interrupt is enabled
CRC16EE2CRC16 Failure Interrupt Enable bit
  • 0 CRC16EF interrupt is disabled
  • 1 CRC16EF interrupt is enabled
CRC5EE_EOFEE1(Device mode) CRC5 Host Error Interrupt Enable bit / (Host mode) EOF Error Interrupt Enable bit
  • 0 (Device mode)CRC5EF interrupt is disabled / (Host mode)EOF interrupt is disabled
  • 1 (Device mode)CRC5EF interrupt is enabled / (Host mode)EOF interrupt is enabled
PIDEE0PID Check Failure Interrupt Enable bit
  • 0 PIDEF interrupt is disabled
  • 1 PIDEF interrupt is enabled

U2STATUSB Status Register (x = 1 and 2)

Address
0xBF88A240
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
FieldBitsWhat it does
ENDPT4Encoded Number of Last Endpoint Activity bits
  • 0 Endpoint 0
  • 1 Endpoint 1
  • 14 Endpoint 14
  • 15 Endpoint 15
DIR3Last BD Direction Indicator bit
  • 0 Last transaction was a receive transfer (RX)
  • 1 Last transaction was a transmit transfer (TX)
PPBI2Ping-Pong BD Pointer Indicator bit
  • 0 The last transaction was to the EVEN BD bank
  • 1 The last transaction was to the ODD BD bank

U2CONUSB Control Register (x = 1 and 2)

Address
0xBF88A250
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
JSTATE7Live Differential Receiver JSTATE flag bit
  • 0 No JSTATE detected
  • 1 JSTATE detected on the USB
SE06Live Single-Ended Zero flag bit
  • 0 No Single Ended Zero detected
  • 1 Single Ended Zero detected on the USB
PKTDIS_TOKBUSY5(Device mode) Packet Transfer Disable bit / (Host mode) Token Busy Indicator bit
  • 0 (Device mode)Token and packet processing enabled / (Host mode)No token being executed
  • 1 (Device mode)Token and packet processing disabled (set upon SETUP token received) / (Host mode)Token being executed by the USB module
USBRST4Module Reset bit
  • 0 USB reset is terminated
  • 1 USB reset is generated
HOSTEN3Host Mode Enable bit
  • 0 USB host capability is disabled
  • 1 USB host capability is enabled
RESUME2RESUME Signaling Enable bit
  • 0 RESUME signaling is disabled
  • 1 RESUME signaling is activated
PPBRST1Ping-Pong Buffers Reset bit
  • 0 Even/Odd buffer pointers not being Reset
  • 1 Reset all Even/Odd buffer pointers to the EVEN BD banks
USBEN_SOFEN0(Device mode)USB Module Enable bit / (Host mode)
  • 0 (Device mode)USB module and supporting circuitry is disabled / (Host mode)SOF token disabled
  • 1 (Device mode)USB module and supporting circuitry is enabled / (Host mode)SOF token sent every 1 ms

U2ADDRUSB Address Register (x = 1 and 2)

Address
0xBF88A260
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
LSPDEN7Low Speed Enable Indicator bit
  • 0 Next token command to be executed at Full Speed
  • 1 Next token command to be executed at Low Speed
DEVADDR6:0

U2BDTP1USB BDT Page 1 Register (x = 1 and 2)

Address
0xBF88A270
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BDTPTRL7:1

U2FRMLUSB Frame Number Low Register (x = 1 and 2)

Address
0xBF88A280
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
FRML7:0

U2FRMHUSB Frame Number High Register (x = 1 and 2)

Address
0xBF88A290
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
FRMH2:0

U2TOKUSB Token Register (x = 1 and 2)

Address
0xBF88A2A0
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
PID7:4Token Type Indicator bits
  • 0 reserved
  • 1 OUT (TX) token type transaction
  • 2 reserved
  • 3 reserved
  • 4 reserved
  • 5 reserved
  • 6 reserved
  • 7 reserved
  • 8 reserved
  • 9 IN (RX) token type transaction
  • 10 reserved
  • 11 reserved
  • 12 reserved
  • 13 SETUP (TX) token type transaction
  • 14 reserved
  • 15 reserved
EP3:0

U2SOFUSB SOF Threshold Register (x = 1 and 2)

Address
0xBF88A2B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CNT7:0SOF Threshold Value bits
  • 18 8-byte packet
  • 26 16-byte packet
  • 42 32-byte packet
  • 74 64-byte packet

U2BDTP2USB BDT PAGE 2 Register (x = 1 and 2)

Address
0xBF88A2C0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BDTPTRH7:0

U2BDTP3USB BDT PAGE 3 Register (x = 1 and 2)

Address
0xBF88A2D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
BDTPTRU7:0

U2CNFG1USB Configuration 1 Register (x = 1 and 2)

Address
0xBF88A2E0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
UTEYE7USB Eye-Pattern Test Enable bit
  • 0 Eye-Pattern Test is disabled
  • 1 Eye-Pattern Test is enabled
UOEMON6USB
  • 0 OE signal is inactive
  • 1 OE signal is active; it indicates intervals during which the D+/D- lines are driving
USBSIDL4Stop in Idle Mode bit
  • 0 Continue module operation in Idle mode
  • 1 Discontinue module operation when device enters Idle mode
LSDEV3Low-Speed Device Enable bit
  • 0 USB module to operate in OTG
  • 1 USB module to operate in Low-Speed Device mode
UASUSPND0Automatic Suspend Enable bit
  • 0 USB module does not automatically suspend upon entry to Sleep mode. Software must use the USUSPEND bit (UxPWRC) to suspend the module
  • 1 USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit (UxPWRC) in

U2EP0USB Endpoint Control Register 0

Address
0xBF88A300
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
LSPD7Low-Speed Direct Connection Enable bit
  • 0 Direct connection to a low-speed device is disabled; hub required with PRE_PID
  • 1 Direct connection to a low-speed device is enabled
RETRYDIS6Retry Disable bit
  • 0 Retry NAKed transactions is enabled; retry done in hardware
  • 1 Retry NAKed transactions is disabled
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP1USB Endpoint Control Register 1

Address
0xBF88A310
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP2USB Endpoint Control Register 2

Address
0xBF88A320
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP3USB Endpoint Control Register 3

Address
0xBF88A330
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP4USB Endpoint Control Register 4

Address
0xBF88A340
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP5USB Endpoint Control Register 5

Address
0xBF88A350
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP6USB Endpoint Control Register 6

Address
0xBF88A360
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP7USB Endpoint Control Register 7

Address
0xBF88A370
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP8USB Endpoint Control Register 8

Address
0xBF88A380
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP9USB Endpoint Control Register 9

Address
0xBF88A390
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP10USB Endpoint Control Register 10

Address
0xBF88A3A0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP11USB Endpoint Control Register 11

Address
0xBF88A3B0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP12USB Endpoint Control Register 12

Address
0xBF88A3C0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP13USB Endpoint Control Register 13

Address
0xBF88A3D0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP14USB Endpoint Control Register 14

Address
0xBF88A3E0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled

U2EP15USB Endpoint Control Register 15

Address
0xBF88A3F0
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EPCONDIS4Bidirectional Endpoint Control bit
  • 0 (If EPTXEN is 1 and EPRXEN is 1)Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed / (else)bit is ignored
  • 1 (If EPTXEN is 1 and EPRXEN is 1)Disable Endpoint n from Control transfers; only TX and RX transfers allowed / (else)bit is ignored
EPRXEN3Endpoint Receive Enable bit
  • 0 Endpoint n receive is disabled
  • 1 Endpoint n receive is enabled
EPTXEN2Endpoint Transmit Enable bit
  • 0 Endpoint n transmit is disabled
  • 1 Endpoint n transmit is enabled
EPSTALL1Endpoint Stall Status bit
  • 0 Endpoint n was not stalled
  • 1 Endpoint n was stalled
EPHSHK0Endpoint Handshake Enable bit
  • 0 Endpoint Handshake is disabled (typically used for isochronous endpoints)
  • 1 Endpoint Handshake is enabled