PIC32MK1024MCM064 DMAC registers

The 6 registers of DMAC (DMA controller), from 0xBF811000, with their reset value and every field. The PIC32MK1024MCM064 has 2203 registers in 115 peripherals, one page each.

Most PIC32 SFRs have three more registers right after them: CLR at +4, SET at +8 and INV at +C (T1CONCLR, T1CONSET, T1CONINV), which clear, set or flip just the bits written as 1, in one write.

DMAC DMA controller

DMACONDMA Controller Control Register

Address
0xBF811000
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
ON15DMA On bit
  • 0 DMA module is disabled
  • 1 DMA module is enabled
SUSPEND12DMA Suspend bit
  • 0 DMA operates normally
  • 1 DMA transfers are suspended to allow CPU uninterrupted access to data bus
DMABUSY11DMA Module Busy bit
  • 0 DMA module is disabled and not actively transferring data
  • 1 DMA module is active and is transferring data

DMASTATDMA Status Register

Address
0xBF811010
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
DMACH2:0
RDWR31Read/Write Status bit
  • 0 Last DMA bus access when an error was detected was a write
  • 1 Last DMA bus access when an error was detected was a read

DMAADDRDMA Address Register

Address
0xBF811020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
DMAADDR31:0

DCRCCONDMA CRC Control Register

Address
0xBF811030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BYTO29:28CRC Byte Order Selection bits
  • 0 No swapping
  • 1 Endian byte swap on word boundaries
  • 2 Swap half-words on word boundaries
  • 3 Endian byte swap on half-word boundaries
WBO27CRC Write Byte Order Selection bit
  • 0 Source data is written to the destination unaltered
  • 1 Source data is written to the destination re-ordered as defined by BYTO
BITO24CRC Bit Order Selection bit
  • 0 (When CRCTYP is 1)The IP header checksum is calculated Most Significant bit (LSb) first / (When CRCTYP is 0)The LFSR CRC is calculated Most Significant bit first
  • 1 (When CRCTYP is 1)The IP header checksum is calculated Least Significant bit (LSb) first / (When CRCTYP is 0)The LFSR CRC is calculated Least Significant bit first
PLEN12:8Polynomial Length bits
  • 2 (CRC module is in IP Header mode)These bits are unused / (CRC module is in LFSR mode)Denotes the polynomial length is 1
  • 3 (CRC module is in IP Header mode)These bits are unused / (CRC module is in LFSR mode)Denotes the polynomial length is 2
CRCEN7CRC Enable bit
  • 0 CRC module is disabled and channel transfers proceed normally
  • 1 CRC module is enabled and channel transfers are routed through the CRC module
CRCAPP6CRC Append Mode bit
  • 0 The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination
  • 1 The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA
CRCTYP5CRC Type Selection bit
  • 0 The CRC module will calculate a LFSR CRC
  • 1 The CRC module will calculate an IP header checksum
CRCCH2:0CRC Channel Select bits
  • 0 CRC is assigned to Channel 0
  • 1 CRC is assigned to Channel 1
  • 2 CRC is assigned to Channel 2
  • 3 CRC is assigned to Channel 3
  • 4 CRC is assigned to Channel 4
  • 5 CRC is assigned to Channel 5
  • 6 CRC is assigned to Channel 6
  • 7 CRC is assigned to Channel 7

DCRCDATADMA CRC Data Register

Address
0xBF811040
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DCRCDATA31:0

DCRCXORDMA CRCXOR Enable Register

Address
0xBF811050
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
DCRCXOR31:0CRC XOR Register bits
  • 0 (When CRCTYP is 0) Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register/ When CRCTYP is 1) This register is unused
  • 1 (When CRCTYP is 0) Enable the XOR input to the Shift register / (When CRCTYP is 1) This register is unused